JPH0629750A - Switching noise preventing method for digital delay circuit - Google Patents

Abstract

PURPOSE:To prevent the step of the output of a digital attenuator from being freely changed even in the case of an external factor by narrowing down the gain of the digital attenuator connected to a delay circuit at the time of changing the delay time and gradually releasing narrowing-down of the digital attenuator after wait of a maximum delay time. CONSTITUTION:The input side of a microphone amplifier 11 is connected to a microphone terminal 10, and the output side of the microphone amplifier 11 is branched into two routes 12 and 13, and they are so connected that they joined in the part of a terminal 14. The route 13 is used for processed sounds to be delayed, and a VCA 17, a terminal 18, and a digital relay 19 which function as the attenuator are successively connected. A VCA 20 is connected as a feedback circuit between the input side and the output side of the digital relay 19. When the delay time is intentionally varied by the operation of the VCA 17, corresponding data is outputted, but unnecessary data output does not occur by the hysteresis characteristic of the VCA 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching noise preventing method for a digital delay circuit, which can be applied to, for example, a karaoke apparatus.

[0002]

2. Description of the Related Art In a karaoke apparatus or the like, an echo effect is generated by delaying a part of a voice signal from a microphone so as to enhance a production effect. In this way, the audio signal is delayed by digitizing the signal, temporarily storing it in a memory element, and delaying it for a predetermined time before taking it out.

According to such a digital delay circuit,
Although it can be delayed for an arbitrary time, there is a problem that noise is generated when switching the delay time. This will be explained. FIG. 5 shows a general digital delay circuit that sets a delay time. In this figure, 1 is an input terminal, 2 is an output terminal, and the integrated circuit 3 and the memory element 4 connected between them form a delay circuit. The integrated circuit 3 has a configuration in which two low-pass filters 5 and 6, an A / D converter 7, a D / A converter 8 and a control logic 9 are connected in the order shown. The memory element 4 is connected to the control logic 9.

In the above circuit, the delay operation is performed between the input terminal 1 and the output terminal 2. Therefore, the input terminal 1 and the output terminal 2 are connected in parallel with the original sound circuit which is not subjected to the delay processing. The low-pass filter 5 on the input side in FIG. 5 is for removing unnecessary high frequency components so as not to malfunction during A / D conversion. The signal converted into the digital signal enters the memory element 4 through the control logic 9, is stored therein, is read out by the control logic 9 after a lapse of a certain time, and is returned to the analog signal by the D / A converter 8. And is output to the output terminal 2 via the low-pass filter 6. That is, it is delayed by the time stored in the memory element 4.

When the delay operation is performed in this way, the delay time is represented by the number of bits of the memory element 4 divided by the sampling frequency. Therefore, if the number of bits of the memory element 4 is fixed, the delay time can be changed by changing the sampling frequency. Also, the delay time can be changed by fixing the sampling frequency and changing the number of bits of the memory element 4. According to the latter method, if the read pointer is changed for the purpose of changing the delay time while the memory element 4 is being accessed, the volume level does not have to change before and after that, but generally the volume level changes. , Data of different volume levels will be connected, and noise will be generated.

No noise occurs when the number of bits of the memory element 4 is fixed and the sampling frequency is changed, but when the number of bits is changed while the sampling frequency is fixed, the noise is generated as described above. If possible, noise should not occur in both equations. However, this noise is generated in a short time when changing the pitch, so in the past, no measures have been taken to solve this, and it is the actual situation to put up with the noise or to mute it to eliminate it. It was

Therefore, even when the sampling frequency is fixed and the number of bits is changed, a method of preventing noise generation without performing any mute operation or the like would suffice. From this point of view, the inventor has already invented and applied for a patent to the original sound circuit that directly connects the input terminal and the output terminal, and the digital delay circuit provided between the input terminal and the output terminal. In a digital delay method in which the signal passed through the digital delay circuit is mixed with the output signal of the original sound circuit in parallel, the gain of the attenuator connected to the delay circuit is narrowed down at the same time when the delay time is changed, and the maximum delay time is increased. There is a method for preventing switching noise of a digital delay circuit, which is characterized by gradually releasing the aperture of the attenuator after the standby (Japanese Patent Application No. 3-011399).
issue).

A circuit for realizing the switching noise prevention method of the digital delay circuit is shown in FIG. To explain this, 10 is a microphone terminal to which a microphone is connected. The input side of the microphone amplifier 11 is connected to the microphone terminal 10, and the microphone amplifier 11
The output side of is branched into two paths 12 and 13 and connected so as to join at the terminal 14. Path 12 is the original sound system, and path 13 is the delayed sound system. A for terminal 14
A speaker 16 is connected via an F amplifier 15.

Since the system path 12 is an original sound system, the output side of the microphone amplifier 11 and the terminal 14 are directly connected. On the other hand, the system path 13 is a delayed sound system, in which a VCA (voltage control amplifier) 17 functioning as an attenuator, a terminal 18, and a digital relay (corresponding to the integrated circuit 3 described above) 19 are sequentially connected. ing. And between the input side and the output side of this digital relay 19,
VCA20 is connected as a feedback circuit.

In the circuit thus constructed, the VCA 17 is operated to change the delay time,
The signal level of the processing sound circuit will be narrowed down.

FIG. 2 shows the time for changing the signal level. In this figure, T ₁ is the operation time of the VCA 17, and indicates that the level of the signal of the processing sound circuit passing through the system path 13 is narrowed down from the start to the time T ₁ . After the lapse of time T ₁ , the signal level is sufficiently low. The time T ₂ is the maximum delay time in which the signal taken into the memory element 4 (see FIG. 3) is shifted and finally becomes empty. This time there is access pointer operation time T ₃ of after a T _2, after where the access pointer operation, to return to the original state gradually increase the signal level is narrowed over again time T _1. The VCA 20 works together with the VCA 17 to change the feedback amount of the digital relay 19. As described above, in the circuit of the present invention, the access pointer is operated while the signal level is narrowed down. Therefore, even if there is a voice signal at that time, this does not appear as noise.

With the above arrangement, when changing the delay time, that is, when noise is generated, the attenuator lowers the volume level of only the processed sound, and the attenuator diaphragm is released after waiting for the maximum delay time. As a result, the volume level is restored. As a result, noise does not appear as sound, but one problem occurs here. That is, when a digital type attenuator is used and the gain is narrowed down and released stepwise, the level may automatically change at a certain level.

This will be described. In the switching noise prevention method described above, the VCA 17 is used as an attenuator for narrowing down the signal level of the processed sound circuit, but the time for changing the signal level is as shown in FIG. Now, if the operation of the access pointer continuously occurs within the period of T ₂ + T ₃ , the VCA 17 continues to be narrowed down, and the processed sound is not mixed with the original sound.

As a situation where the operation of the access pointer continuously occurs without depending on the operation of the operator, an analog voltage supplied from a volume (volume control) (not shown) connected to the rear stage of the microphone terminal 10 or the like is used. Assuming that the number of delay time points is determined by A / D conversion as an input, when the volume is set near the threshold of points, the boundary line may be changed due to the performance of the volume, environmental changes, etc. However, the access pointer is operated by determining that the delay time changes each time.

This is apparent from FIG. 3, considering that when the analog input voltage applied to the input side of the VCA 17 is 0 to 5 volts, this is divided into 16 steps and the delay time is switched. Although it is possible to use 4-bit binary data, the LSB 1 bit is added to this as a state detection bit, and the delay time can be switched by A / D conversion of 5 bits. In this case, step 8
An analog voltage corresponding to (indicated by a circled character in the drawing; the same applies hereinafter) is 1.175 to 1.325 V, and similarly, 9 steps are 1.325 to 1.475 V. When each of these is represented by a binary number, it becomes "00111" in 8 steps and "01000" in 9 steps.

As is clear from FIG. 3, the boundary between step 8 and step 9 is 1.325V. So around here A
/ D input voltage and volume applied voltage, resistance value, etc. move from step 8 to step 9 or step 9 to step 8 due to external factors. I'm concerned. Possible external factors include power supply voltage fluctuations and temperature changes.

[0017]

SUMMARY OF THE INVENTION The present invention has been made for the purpose of solving such a problem of the switching noise preventing method for a digital delay circuit according to the previous application, and even if an external factor Even if there is, there is a need to provide a switching noise prevention method in which the steps do not change arbitrarily.

[0018]

As a means for solving the above problems, the present invention provides an original sound circuit for directly connecting an input terminal and an output terminal, and a digital signal provided between the input terminal and the output terminal. A digital delay method in which a delay circuit is connected in parallel and a signal passed through the digital delay circuit is mixed with an output signal of the original sound circuit, wherein the digital delay circuit has a digital characteristic having hysteresis characteristics when the control voltage rises and falls. When the attenuator is connected and the delay time is changed, the gain of the digital attenuator connected to the delay circuit is reduced at the same time, and the aperture of the digital attenuator is gradually released after waiting the maximum delay time in the delay circuit. This is a method for preventing switching noise of a characteristic digital delay circuit.

[0019]

With this configuration, the hysteresis characteristic of the digital attenuator (VCA) does not cause an unstable state when the control voltage rises and falls, so that there is no change in voltage or temperature. Depending on the physical factor, the step switching may not be performed, and stable operation of the digital attenuator may be obtained.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiment of the present invention is carried out in the circuit of FIG. 1 by the program routine of FIG. Now, if the analog voltage in step 9 is input to the A / D due to some situation change (external factor described above) from the state set in step 8, the following calculation is performed by the program routine of FIG. .

[0021]

[Equation 1] ADREAD + LSB1BIT = ADC → 01000 + 00001 = 0100 1 (1)

## EQU00002 ## ADREAD-LSB1BIT = ADC.fwdarw.01000-00001 = 0011 1 (2)

In the above equation, ADC is data that is temporarily saved for comparison with ADOUT (data read at setting). Since the condition of (5) in FIG. 4 is satisfied by the calculation result of the equation (2) and the program routine ends, new data is not sent out. Also, considering the changes from step 8 to step 6 and step 10, similarly, the calculation results of (1) and (2) are
Since none of the conditions (3) to (5) is satisfied, when the data saved as the comparison data is newly set, it is saved as the read data and then the upper 4 bits are output as the new delay time. In the change from step 8 to step 7, the condition of (5) is satisfied according to the calculation result of equation (1), and the value is the same as that of step 9.

According to the method for preventing switching noise of the digital delay circuit according to the present invention, when the delay time is varied by intentionally performing the volume operation by the operation of the VCA 17 described above, the data corresponding to the delay time is changed. Output is performed, but unnecessary data output due to an external fluctuation factor near the threshold between steps does not occur.

[0024]

As described above, according to the present invention, the original sound circuit which directly connects the input terminal and the output terminal and the digital delay circuit which is provided between the input terminal and the output terminal are connected in parallel. A digital delay method of mixing a signal passed through a digital delay circuit with an output signal of the original sound circuit,
A method for preventing switching noise in a digital delay circuit, which comprises narrowing down the gain of an attenuator connected to a delay circuit at the same time when changing the delay time, and gradually releasing the throttle of the attenuator after waiting for the maximum delay time. . With this configuration, there is an effect that noise does not occur when operating the access pointer. In this case, unnecessary data output due to external fluctuation factors does not occur near the threshold between steps.

[Brief description of drawings]

FIG. 1 is a circuit diagram for explaining a method of the present invention.

FIG. 2 is an explanatory diagram for explaining an operating time of that of FIG.

FIG. 3 is a numerical diagram for explaining the method of the present invention.

FIG. 4 is a flowchart showing the operation of the method of the present invention.

FIG. 5 is a circuit diagram showing a general circuit of a digital delay circuit.

[Explanation of symbols]

 10 Microphone terminal 11 Microphone amplifier 12 System path 13 System path 14 terminal 18 Terminal 15 AF amplifier 17 VCA 19 Digital relay 20 VCA

Claims (1)

[Claims] 1. An original sound circuit that directly connects an input terminal and an output terminal, and a digital delay circuit provided between the input terminal and an output terminal are connected in parallel, and the signal that has passed through the digital delay circuit is said. In the digital delay method of mixing with an output signal of an original sound circuit, a digital attenuator having a hysteresis characteristic is connected to the digital delay circuit when the control voltage rises and falls, and simultaneously connected to the delay circuit when changing a delay time. A switching noise preventing method for a digital delay circuit, wherein the gain of the digital attenuator is narrowed down, and the narrowing of the digital attenuator is gradually released after waiting the maximum delay time in the delay circuit.