KR200156132Y1 - Apparatus of regenerating sound for electronic instrument - Google Patents

Abstract

The present invention relates to a sound reproducing apparatus of an electronic musical instrument. In the conventional apparatus, when a loop point of a sample is taken, the level of the sample point shows a drastic difference when the loop point is connected to the loop start point. There was a problem that could not be played. In order to solve this problem, the present invention can reduce the level difference between the pointer of the loop start address register and the loop end address register. will be.

Description

Electronic music player

1 is a block diagram of a sound reproducing apparatus of a conventional electronic musical instrument.

2 is a block diagram of a sound reproducing apparatus of the present invention musical instrument.

3 is a diagram illustrating a loop start point and a loop end point of a looping section.

4 is a diagram showing the next sample point according to the value of the looping restart following point register.

* Explanation of symbols for main parts of the drawings

100: MPU 101: current address register

102: frequency address register 103: loop start address register

104: loop end address register

105: looping restarting point register

106: Next sample point signal output section 107: Buffer section

108: control unit 109: data processor

110: sampling memory AND1: AND gate

B1-B4: Buffer CP1, CP2: Comparator

T1-T3: Temporary register SUB1: Subtractor

MUL1: Multiplier ADD1, ADD2: Adder

The present invention relates to a sound reproduction circuit of an electronic musical instrument. In particular, the sound reproduction apparatus of an electronic musical instrument capable of reducing the level difference between a pointer of a loop start address register and a loop end address register pointer to enable natural sound to be reproduced. It is about.

FIG. 1 is a block diagram of a sound reproducing apparatus of a conventional electronic musical instrument. As shown therein, a current address register (2) (CA), a frequency address register (3) (FA), and a loop start address register in MPU 1 are shown in FIG. (4) Write values into the LS and loop end address registers 5 and LE.

The loop start, which is a register indicating a loop start point and a loop end point in one sample of the current address register 2 and the frequency address register 3, indicates a start point for one sample in the sampling memory 11. The address register 4 and the loop end address register 5 are operated.

When reproducing a sample sound, the current address is generated in the current address register 2 to access one point and go out serially through the data processor 10.

Then, the current address register 2 and the frequency address register 3 are added through the adder 8 to access the points, and the current address register 2 is updated through the buffer 6 to the current address register 2.

This operation is repeatedly performed, and the output of the adder 8 and the loop end address register 5 are compared through the comparator 9, and if the AB is enabled, the buffer 6 is enabled and the loop end address register ( The value of 5) is loaded into the current address register 2.

In this way, the loop start point and loop end point are repeated, looping, sample access, and sound reproduction.

However, such a conventional device has a problem in that smooth sound cannot be reproduced because the level of the sample point shows a sharp difference when the loop point is taken from the loop end point to the loop start point.

In order to solve this problem, the present invention can reduce the level difference between the loop start address register and the loop end address register pointer. will be.

FIG. 2 is a block diagram of the sound reproducing apparatus of the present invention, as shown in this figure. The MPU 100 for overall control of the system, such as writing a corresponding address in each register, and a current indicating the start address of the current sample. An address register 101 (CA), a frequency address register 102 (FA) for storing a value relating to a sound reproduction frequency, and a loop start address register 103 indicating a loop start point and a loop end point of a sample ( LS) and loop end address register 104 (LE), and a looping list polting for outputting a control signal for eliminating a sudden level difference between the loop end address register 104 and the next loop start address register 103. A loop end point sample and a loop start point sample are opened in accordance with an output signal from the point register 105 (LR) and the looping restart following point register 105. A next sample point signal output section 106 for outputting a next sample point signal, a buffer section 107 for buffering and outputting the output signal of the next sample point signal output section 106 and the last loop end sample signal; And a control unit 108 for controlling data access to the next sample point signal output unit 106 during a sample looping period, and a data processor 109 for outputting the output signal of the buffer unit 107 in series. .

The next sample point signal output unit 106 subtracts the output signals of the temporary registers T1 and T3 and T2 for temporarily storing the loop end point sample and the loop start point sample and the temporary registers T1 and T2. A multiplier MUL1 multiplying the output signal of the subtractor SUB1, the output signal of the subtractor SUB1 and the output signal of the looping restart falling point register 105, and the temporary register T3 and the multiplier MUL1. It is characterized by consisting of an adder (ADD2) for adding the output signal of the output). Reference numeral 110 is a sampling memory.

When described in detail with reference to Figures 3 and 4 with respect to the operation and effect of the present invention configured as described above.

After holding the loop section, MPU 100 writes the current address of the current sample to the current address register 101. The frequency address register 102 writes a value relating to the sound reproduction frequency, and the loop start address register 103 and the loop end address register 104 write the address of the loop section.

At this time, the looping restart polting point register 105 is tuned while listening to the sound to use the value.

The first sample point is a value of the current address register 101, and the next address is a value obtained by adding the current address register 101 and the frequency address register 102 through the adder ADD1.

At this time, the comparator CP1 compares the output value of the adder ADD1 with the loop end address register 104 and, if greater than or equal to, the buffer B2 is enabled by the output of the comparator CP1 and the loop start address register 103. Value is loaded into the current address register 101.

When this looping is repeated, the loop end address register 104 and the loop start address register 103 are controlled as a looping restart following point register 105 in order to eliminate the sudden level difference between the loop start address register 103 and the loop start address register 103.

The looping section, loop start point and loop end point are shown in FIG. And points ⓓ and ⓔ in FIG. 4 are points of samples in the prior art.

At this time, if a value of 0.5 is set in the looping restarting point register 105, the SE (loop end point sample) is loaded into the temporary registers T1 and T3, and the next sample SS (loop start point sample) is temporary. It is loaded into the register T2.

Then, the subtractor SUB1 subtracts and outputs the output signals of the temporary registers T1 and T2, and the multiplier MUL1 outputs the output signal of the subtractor SUB1 and the looping restarting floating point register 105. Output by multiplying output signal.

The adder ADD2 adds and outputs the output signals of the multiplier MUL1 and the temporary register T3.

At this time, the controller 108 controls data access to the temporary registers T1-T3 during the looping period of the sample. The buffer B3 outputs the output signal of the adder ADD2 and the buffer B4 outputs SE, which is the last sample of the loop, through the data processor 109.

At this time, the output of the adder ADD2 is as follows.

ADD2 = SE + Fr × (SS-SE) (1)

Where Fr is the value of the looping list floating point register.

Therefore, the output of the adder ADD2 becomes the next sample point (loop start point).

For example, when Fr is 0.5, the next sample point becomes ⓑ in FIG.

If Fr value is 0, it becomes ⓐ point. If Fr value is 1, ⓒ point is output as next sample point.

Therefore, in order to prevent the sudden change of the next sample point, the looping list floating point register 105 is loaded with an appropriate value by tuning.

As described in detail above, the present invention can reduce the level difference between the loop start address register pointer and the loop end address register pointer using the looping address floating point, so that natural sound can be reproduced. .

Claims (2)

MPU for overall control of the system, such as writing the corresponding address in each register, a current address register indicating the start address of the current sample, a frequency address register storing a value relating to the negative reproduction frequency, and a loop start point of the sample. And a loop start address register and a loop end address register indicating a loop end point, and a looping start floating point register for outputting a control signal for eliminating a sudden level difference between the loop end address register and the next loop start address register. A next sample point signal output unit for outputting a next sample point signal in association with a loop end point sample and a loop start point sample according to an output signal of the looping list floating point register, and an output signal and a last signal of the next sample point signal output unit A buffer unit for buffering and outputting the membrane loop end point sample signal, a control unit for controlling data access of the next sample point signal output unit during the lupine period of the sample, and a data processor for serially outputting the output signal of the buffer unit. An electronic musical instrument sound reproduction device. The signal generator of claim 1, wherein the next sample point signal output unit is configured to temporarily store the loop end point sample and the loop start point sample, and output signals of the temporary registers T1 and T2. A subtractor for subtracting, a multiplier for multiplying an output signal of the subtractor and an output signal of the looping list floating point register, an output signal of the temporary register T3 and the multiplier and an output of the looping list floating point register And a multiplier for multiplying and outputting a signal, and an adder for adding and outputting the temporary register (T3) and the output signal of the multiplier.