JP2626315B2 - Signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing apparatus for performing a delay process and a filter process on an audio signal or a tone signal by a program operation.

[0002]

2. Description of the Related Art A digital signal processor (DSP) has been put into practical use as a device for performing a filtering process such as a delay process or a high-frequency cut on a time-series signal such as an audio signal. In this device, a time-series analog signal is quantized at each sampling timing, and a digitized signal is programmed by a high-speed microprocessor. That is, when performing the delay processing, a memory area for the sampling timing corresponding to the delay time is set, and data is stored in this memory area by the FI.
This is performed by reading and writing data in the FO (first in first out). When processing a tone signal or the like, sampling is performed at a sampling frequency of about 40 kHz to maintain the sound quality. Therefore, 40,000 data storage areas are required to obtain a delay time of about 1 second. As such a device, there is a reverberation sound adding device described in JP-B-62-55158.

[0003] Different reverberation characteristics and filter characteristics can be realized by rewriting the control program and coefficient data of the DSP. However, when the control program and the coefficient data are rewritten while the DSP is continuously operated, the program before rewriting is obtained. If the data processed and written in the RAM remains, the data is read out at the beginning of a new process, causing noise. Therefore, in such a case, conventionally, processing for clearing all the delay RAMs has been performed at the same time as rewriting the processing program.

As described above, the operation of rewriting the control program and the coefficient data during the operation of the DSP is frequently performed in recent electronic musical instruments because the tone generation channels are randomly assigned. Random assignment means that a plurality of musical tones can be produced simultaneously with different tones, and a channel that produces each musical tone is not specified. An empty channel is searched each time a KON signal is received, and key-on is performed for that channel. This is a technique for transmitting a tone signal together with a signal and a key code. As a result, it has become possible to effectively use the pronunciation channel.

[0005]

However, as described above, when a long delay time is to be obtained or when a complicated filter characteristic is to be obtained, a large amount of data must be stored. Although a large-capacity RAM is connected, in the conventional method, the control program and coefficient data are frequently rewritten, and it is necessary to clear the entire area of the RAM each time. However, there is a disadvantage that real-time signal processing becomes difficult.

An object of the present invention is to provide a signal processing apparatus which does not clear data even when a processing program is changed and does not generate noise.

[0007]

According to the present invention, a delay means for delaying an input signal by a predetermined time and outputting the same, a setting means for setting a delay time of the delay means, and a setting means for setting the delay time of the delay means Means for rewriting the output of the delay means to a specific value until the changed new delay time elapses after the setting of the delay time is changed.

[0008]

The signal processing device according to the present invention includes a delay unit and a setting unit for setting the delay time of the delay unit. When the setting unit changes the setting of the delay time of the delay unit, a new delay is set. Until the time elapses, the output of the delay means is rewritten to a specific value. The delay means is, for example,
It is configured by means for reading and writing data in the area of the RAM by FIFO. The setting means is constituted by means for determining the number of stages of the memory area. When the setting of the delay time is changed, a new signal input immediately thereafter is not read out until the delay time has elapsed, so that the signal read out before that is the old setting signal. Therefore, while this signal is being output, a specific value is output instead of the output. Specific value may be set to the data (such as 0 or FF _H) representing the state signal is not.

The signal processing device according to the present invention comprises, for example, a program storage means for storing a plurality of types of programs for executing a multi-stage delay operation on an input signal;
Delay time storage means for storing delay times at each stage for each of the plurality of types of programs; a plurality of signal storage means for storing signals that are separately set and delayed for each of the plurality of stages of delay operations; Selecting means for selecting one of the types of programs; and, when the selection of the program is changed by the selecting means, in each of the steps after the change, the steps are repeated until a delay time of the changed new program elapses. And a means for rewriting the output of the signal storage means corresponding to (i) to a specific value. The signal processing device configured as described above executes a delay operation in a plurality of stages by a program. The multi-stage delay operation is a case where, for example, an FIR filter, an IIR filter, or the like is realized by a DSP. In this case, the delay time corresponding to each step is stored corresponding to the program (delay time storage means), and when the program is selected, the output signal is output until the delay time elapses in each step. Rewrite to a predetermined value. by this,
In each step, noise caused by reading out old data can be eliminated, and the time required for rewriting a program can be reduced.

[0010]

FIG. 1 is a block diagram of an electronic musical instrument provided with a signal processing device according to an embodiment of the present invention. This electronic musical instrument can generate a plurality of musical tones simultaneously by operating the keyboard 15, and can impart different effects such as delay and filter processing to each musical tone. The operation of the entire electronic musical instrument is performed by the CPU 10
Controls. The CPU 10 has a ROM 1 via a bus 11.
2, a RAM 13, a keyboard interface 14, a panel interface 16, a tone synthesis circuit 18, and an effect imparting circuit 19 are connected. The keyboard 15 is connected to the keyboard interface. The panel interface 16 is connected to keys and indicators on the operation panel 17 of the electronic musical instrument. The ROM 12 stores an operation program shown by a flowchart described below. R
A register area for storing data generated by operating the keyboard 15 and the panel 17 is set in the AM 13. Data such as a key code and velocity data is generated by operating the keyboard 15, and the data is transmitted to the CPU 10 via the keyboard interface 14.

The panel 17 includes a tone color selection switch, an effect selection switch, and the like. The tone synthesis circuit 18 is 8
It has up to 16 sound channels, and forms tone signals based on key-on signals and key codes transmitted from the CPU 10. When the key-on is detected, the CPU 10 searches for an inactive channel among the sounding channels, and instructs the channel to form a tone signal corresponding to the key-on. Therefore, which tone generation channel is responsible for forming a tone of a tone color is determined at all at random. The effect giving circuits 19 are provided in the same number as the tone generation channels, and can give different effects to each of the formed tone signals. The tone signal provided with the effect is input to the sound system 20 and amplified, and then output from the speaker 21.

FIG. 2 shows the FI realized by the effect applying circuit 19.
It is a figure showing an example of an R filter.

This filter converts the input tone signal to t
Delay is performed by a four-stage shift register of 1d to t4d, an output is taken out from each delay stage, and synthesized by an adder. As a result, a finite number of reverberation sounds such as an early reflection sound can be added. If such a fixed circuit is configured in an actual electronic musical instrument, it cannot be used for other effects. Therefore, such a filter characteristic is realized by a program using a DSP.

FIG. 3 shows an example in which the FIR filter of FIG. 2 is realized by a microprogram. The operation of this program is as follows. The value of the input port INP is loaded (LD) into the accumulator Acc (step 0). A
Write the value of cc to the address T1W of the external RAM (MW:
Step 1). The external R is stored in the internal register IW2 in the DSP.
Read and write the contents of address T1R of AM (MR:
Step 2). Steps 3 to 5 write the contents of the address T2R of the external RAM to the internal register IW3, write the contents of the address T3R of the external RAM to the internal register IW4, and write the contents of the address T4R of the external RAM to the internal register. Write to IW5.

Here, the table shown in FIG. 4 corresponds to the write address T1 of the read addresses T1R, T2R, T3R, T4R.
9 is a table in which the number of shifts from W is stored. The table shown in FIG. 4 is always stored in correspondence with the microprogram as shown in FIG. According to this table, the read address T1R is a position shifted by 3120 areas from the write address T1W. That is, the data written to the external RAM is read out only after elapse of 3120 DAC cycles, and thereafter, the data is read out by 21369 DAC cycles (T2
R), 36519 DAC cycle (T3R), 5949
It is read out when 5 DAC cycles (T4R) have elapsed.

Next, at step 6 in FIG. 3, the internal register IW2 is multiplied by the coefficient K1 and loaded into Acc (ML). In step 7, the internal register IW3 is multiplied by the coefficient K2 and integrated with the current contents of Acc (MA).
In steps 8 and 9, as in step 7, the contents of the internal registers IW4 and IW5 at each stage are multiplied by the coefficients K3 and K4 and integrated. That is, the output of the shift register of each step is added by this operation. K1
K4 corresponds to the impulse response. Finally, in step 10, the contents of the accumulator Acc are output to the output port OUT. The above operation is repeatedly executed every DAC cycle. In this case, the external RAM
Write address T1W and read address T
1R, T2R, T3R, T4R are constant every time,
In the DAC cycle, that is, when the microprogram makes one cycle, the reference point for calculating the address is shifted by one instead of shifting all the data by one address. This relatively shifts the address (FIG. 5).
reference).

When a microprogram is rewritten as shown in FIG. 3 in a DSP in which another microprogram is operating, the DSP addresses data input from the tone synthesis circuit in step 1 of the first DAC cycle. Write to T1W.

Next, at step 2, the data at the address T1R is read. At this point, the data stored at the previous microprogram has been written in the T1R data. Output of the data, which causes noise. Further, the same holds true even if the address is shifted by one in the next DAC cycle. The new program data is read from the read address T1R at 3120 as shown in FIG.
After the DAC cycle. Until then, the newly input data is only sent to the delay cycle and is not output, so the output in the read step should be 0 (data corresponding to 0). Therefore, D in FIG.
Until the number of AC cycles elapses, 0 is output regardless of the read data.

FIG. 6 is a block diagram of one channel of the effect imparting circuit 19 for realizing such an operation. DSP
A control circuit 31, a selector 33, and a RAM 34 are connected to 30. The register area of FIG. 5 is set in the RAM 34. A RAM 32 is connected to the control circuit 31. The RAM 32 stores the delay cycle number data of FIG. The microprogram in FIG.
0 is loaded into the program memory. The tone signal WAVEIN input from the tone synthesis circuit 18 is a DSP3
At 0, various processes (for example, processes shown by the microprogram in FIG. 3) are performed. As a result, the tone signal is given various effects and output as WAVEOUT. The DSP 30 reads and writes data from and to the RAM 34, but until the timing at which correct data is actually output when a new control program is started, the selector 33 replaces the data read from the RAM 34 with 0 data. Is input to the DSP 30.

FIG. 7 is a detailed diagram of the control circuit 31.
The control circuit 31 includes a memory control circuit 40, a counter 41,
AND gate 42, maximum value detection circuit 43, inverter 4
4, a comparator 45 and a NAND gate 46 are provided.
When the microprogram of the DSP 30 is changed, the DSP 30 outputs a CHANGE signal. This signal is supplied to the counter 41 to reset the count value. The value of the counter is compared by the comparator 45. When the count value is smaller than the value given from the memory control circuit and when the DSP requests the RAM 34 to read, the selector 33 of FIG. Outputs 0. TH represents through, and when TH = 1, RA
This indicates that the value of M34 is directly input to the DSP 30. Therefore, when TH = 0, 0 is input to the DSP 30 regardless of the value output from the RAM 34.

In this way, the data in the RAM 34 is input to the DSP 30 in steps with a short delay cycle. The counter 41 is configured to be able to count up to a maximum value that can be set as a delay step,
When the maximum value detection circuit 43 detects the maximum value, the operation is automatically stopped. Note that a signal input as a clock of this counter is an S signal synchronized with the DAC cycle.
This is the YNC signal.

FIGS. 8 to 10 are flowcharts showing the operation of the electronic musical instrument. FIG. 8 shows the main routine. First, when the power switch is turned on, an initialization operation (n1) is executed. This operation is an operation such as resetting a register. Thereafter, a key scan (n2) and a panel scan (n8) are performed, and if there is a key event and a panel event, the corresponding operation is executed. If there is a key event, the operation of n4 to n7 is executed according to the judgment of n3. First, in n4, data indicating whether the event is a key-on event or a key-off event is stored in the key event register KEV, the key code is stored in the key code register KC, and the initial touch data is stored in the initial touch register IT. Next, if it is a key-on event, key-on processing (n6: FIG. 9) is executed, and if it is a key-off event, key-off processing (n7:
(FIG. 10) is executed. If there is a panel event, n
The operations of n10 to n14 are executed based on the judgment of 9. n10,
At n11, it is determined whether or not the event is a switch event for specifying the tone of the upper and lower keys. If it is an upper keyboard tone specifying event, the set tone color number is set in the UTC register (n14). If it is a lower keyboard tone specifying event, the set tone color number is set in the LTC register (n14).
13). If it is another panel event, the corresponding operation is executed (n12).

FIG. 9 is a flowchart showing the key-on processing operation. When the key is turned on, a search is made for a sounding channel that produces the tone of the key-on (n20). If there is a vacant channel, the sound generation process is executed on that channel.
If there is no free channel, the truncation process (n2
Perform 2). The truncation process is a process for forcibly silencing a tone having the lowest tone level among all tone tones generated at that time, and assigning the channel to generate a tone based on the new key-on.
In n23, it is determined whether or not the key code of the turned on key is above KSP. KSP is the key code of the highest note of the lower keyboard. If it is larger than this, it is a key-on event of the upper keyboard, and if it is less than this, it is a key-on event of the lower keyboard. In the case of the upper keyboard, UTC is set in the tone color register TC (n24), and in the case of the lower keyboard, LTC is set in TC (n25). The microprogram according to the set tone number TC is applied to the effect giving circuit 19.
And the delay cycle number data of the microprogram is transferred to the DSP of the corresponding channel of R.
The data is transferred to the AM 32 (n26). By this operation, a unique effect can be provided for each tone while employing a random assignment method. Data such as IT, KC, and TC is output to the corresponding channel of the tone synthesis circuit 18 to start synthesis of tone signals (n27).

FIG. 10 is a flowchart showing the key-off process. When the key is turned off, a search is made to see if there is a channel that is producing the tone of the key code (n3
0).

If there is, a key-off signal is output to the tone generation channel to stop the synthesis of the tone signal (n31). In the case of truncation processing or attenuation-type musical tones, since there are musical tones already muted even if the key is turned on, the judgment of n30 is made.

In the method of randomly assigning a sounding channel in this manner, since it is not known what effect applying function has been assigned immediately before to the effect applying circuit of that channel, a new tone signal is output. 0 is output until

In this embodiment, the effect imparting circuit 19 has a configuration in which DSPs are provided in parallel for each tone generation channel. However, time division processing may be performed by one DSP.
Such a process is not limited to an electronic musical instrument played in real time, but can be applied to an automatic performance device such as a sequencer. Further, the effect imparted by the effect imparting circuit 19 is not limited to the effect of the FIR filter,
Other algorithms such as filters are equally applicable.

Further, in this embodiment, a counter for counting the number of delay steps and a RAM for storing the number of delay steps
And the like are externally attached to the DSP 30, but all of these circuits (functions) may be built in the DSP.

[0029]

As described above, according to the signal processing apparatus of the present invention, the delay time is changed during delay processing, and a new delay time elapses when the input signal changes. Until then, the read signal is ignored and rewritten to a predetermined value. As a result, for example, even when the effect to be applied is switched in a randomly assigned effect applying circuit or the like, the old signal is not read out as it is and does not cause noise. Further, since it is not necessary to clear all the memories for executing the delay processing, there is an advantage that the processing speed is remarkably improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of an electronic musical instrument incorporating a signal processing device according to an embodiment of the present invention;

FIG. 2 is an FIR realized by an effect imparting circuit of the electronic musical instrument.
Diagram showing the concept of a filter,

FIG. 3 is a diagram showing a microprogram executed by a DSP of the effect providing circuit;

FIG. 4 is a diagram showing a table storing the number of delay steps processed by the microprogram;

FIG. 5 is a view for explaining an address shift method executed by the DSP.

FIG. 6 is a block diagram of the effect imparting circuit;

FIG. 7 is a detailed block diagram of a control circuit of the effect providing circuit;

FIG. 8 is a flowchart showing the operation of the electronic musical instrument;

FIG. 9 is a flowchart showing the operation of the electronic musical instrument;

FIG. 10 is a flowchart showing the operation of the electronic musical instrument.

[Explanation of symbols]

30-DSP, 31-control circuit, 32-RAM (in which the number of delay steps is stored), 33-selector, 34-RAM in which a delay data storage area is set.

Claims (1)

(57) [Claims] A delay means for delaying an input signal by a predetermined time and outputting the delayed signal; a setting means for setting a delay time of the delay means; and when the setting means changes the delay time setting of the delay means. And a means for rewriting the output of the delay means to a specific value after the change and until the changed new delay time elapses.