JPH06296135A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To operate the phase locked loop circuit at almost under an optimum condition in any operating state with respect to the phase locked loop circuit used, e.g. for a radio equipment. CONSTITUTION:The phase locked loop circuit having a phase lock loop means 2 which uses a 1st phase comparator 21 to extract a 1st phase comparison output corresponding to a phase difference between an input signal and an output signal of a voltage controlled oscillator 24 and applying it to the voltage controlled oscillator 24 to extract an output signal synchronously with the input signal and having a synchronization state monitor means 3 providing an out of synchronism signal when a 2nd phase comparison output corresponding to a phase difference between a 90 deg. shift output signal obtained by shifting a phase of the output signal by 90 deg. and the input signal reaches the outside of a permissible range is provided with a storage means 4 in which proper operating conditions set corresponding to all combinations of the 2nd phase comparison output and the operating conditions of the phase locked loop means 2 to activate the phase locked loop means 2 at the proper operating condition read from the storage means 4 with the reception of the 2nd phase comparison output and the operating condition of the phase locked loop means 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit used in, for example, a wireless device. To generate a phase reference for synchronous detection on the receiving side of the wireless device, for example, an independent voltage controlled oscillator is provided in the receiver and the reference carrier wave is obtained by controlling the phase of this oscillation output.

At this time, there are pull-in state, steady state, steady phase error state, and out-of-synchronization state as the operating states of the phase locked loop. However, in any operating state, the phase locked loop should be able to operate under almost optimum conditions. With the goal.

[0003]

2. Description of the Related Art FIG. 3 is a configuration diagram of a conventional example, and FIG. 4 is an operation explanatory diagram of first and second phase comparators in FIG.

The reference numeral on the left side of FIG. 4 indicates the output waveform of the portion with the same reference numeral in FIG. The operation of FIG. 3 will be described below with reference to FIG. First, the first phase comparator 11
Input signal and voltage controlled oscillator (hereinafter abbreviated as VCXO) 16
The phase comparison result corresponding to the phase difference with the output signal of the
Input to VCXO via 15 as control signal. So VC
XO is the output signal of the oscillation frequency corresponding to the control signal, that is,
The output signal synchronized with the input signal is sent to the outside.

The second phase comparator 12 receives the input signal and
Outputs the phase comparison result corresponding to the phase difference with the output signal of the VCXO that has passed through the 90-degree phase shifter 13, but when the phase comparison result falls below the threshold value, it is determined to be out of sync and the out-of-sync signal is output. Is sent.

Here, as shown in FIG. 4, in the out-of-synchronization state, the outputs of the first and second phase comparators become sinusoidal waves whose phases differ by 90 degrees. Further, in the steady state, the output of the first phase comparator changes to ± with 0 as the center,
The outputs of the second phase comparator both decrease around the maximum value.

[0007]

Here, the bandwidth of the low-pass filter 14, the gain of the amplifier 15, and the oscillation frequency of the voltage controlled oscillator 16 in the phase locked loop are the pull-in state, the steady state, and the steady phase due to the frequency shift. There is an appropriate value for each of the error occurrence state and the out-of-sync state, but it is fixed (
That is, the operating conditions are constant). Therefore, there is a problem that the pull-in may be delayed and the out-of-sync may become long.

In the present invention, the operating states of the phase-locked loop include the pull-in state and the out-of-sync state. However, it is necessary to operate the phase-locked loop under almost optimal conditions in any operating state.

[0009]

FIG. 1 is a block diagram showing the principle of the present invention. In the figure, 2 is a first phase comparison output corresponding to the phase difference between the input signal and the output signal of the voltage-controlled oscillator.
Is a phase synchronizing means for taking out an output signal synchronized with the input signal by taking it out by the phase comparator and adding it to the voltage controlled oscillator.

Reference numeral 3 indicates an out-of-sync signal when the second phase comparison output corresponding to the phase difference between the 90-degree shifted output signal obtained by shifting the phase of the output signal by 90 degrees and the input signal is out of the allowable range. Synchronous state monitoring means 4 for sending are storage means for storing proper operating conditions set corresponding to all combinations of the second phase comparison output and operating conditions of the phase synchronizing means.

Then, when the second phase comparison output and the operating condition of the phase synchronizing means are applied, the phase synchronizing means is operated under the proper operating condition read from the storage means.

[0012]

In the present invention, the storage means stores the proper operating conditions calculated in advance or experimentally corresponding to all combinations of the operating conditions of the second phase comparison output and the phase synchronizing means. Then, when the second phase comparison output and the operating condition of the phase synchronizing means are applied, the phase synchronizing means is operated using the proper control condition read from the storage means. As a result, the time for the pull-in process and the out-of-sync state can be shortened.

[0013]

FIG. 2 is a block diagram of an embodiment of the present invention. Here, resistors R ₁ , R ₂ , capacitors C _{1 to} C ₃ , switches 221, 222
Are components of the low-pass filter 22, amplification part 231, resistance
R ₃ and variable resistor Rv ₁ are components of amplifier 23 and oscillator 24
1, the variable capacitance diode D ₁ and the resistor R ₅ are components of the voltage controlled oscillator 24. Further, the phase detector 31 and the 90-degree phase shifter 32 are constituent parts of the synchronization status monitor 3, the low-pass filter 41, the amplifier 42, the analog / digital converter 43, and the ROM 44 are constituent means of the storage means 4. .

The operation of the drawings will be described below. The parts described in detail above will be briefly described, and the parts of the present invention will be described in detail. First, the voltage-controlled oscillator (hereinafter VCXO
Since the output signal synchronized with the input signal is sent, the phase synchronization circuit must operate in the synchronization pull-in state, steady state, steady phase error occurrence state due to frequency deviation, and out of synchronization state. Bandwidth of low pass filter 22, amplifier gain, varactor diode
The bias voltage applied to D ₁ has an optimum value.

For example, in the synchronized state and the out-of-synchronized state, it is necessary to change the bandwidth of the low-pass filter 22 and the gain of the amplifier 23 and slightly shift the oscillation frequency of the VCXO 24. Therefore, the information of the sync state / out-of-sync state output from the phase comparator 31 and the operating conditions of the low-pass filter 22, the amplifier 23, and the voltage-controlled oscillator 24 (for example, the on / off state of the switch in the low-pass filter) , The gain for the amplifier, and the bias voltage of the variable capacitance diode for the VCXO) are stored in the ROM 44 in advance, which are appropriate operating conditions calculated in advance or experimentally obtained.

For example, when the output of the phase comparator 31 is out of synchronization, the switches 221 and 222 of the low-pass filter are on, the gain of the amplifier 23 is A ₀ , and the bias voltage of VCXO is V ₀ , this information is Since it is added to the ROM 44 as an address, the proper operating condition corresponding to this address is read.

Thus, for example, the low-pass filter 22
, The built-in switch 222 is turned off to widen the bandwidth, the gain of the amplifier 23 increases as A ₀ → A ₁ , and the VCXO 24 has the bias voltage of V ₀ → V ₁ and the oscillation frequency slightly. The input frequency will be shifted, and the pull-in range will be expanded.

That is, even if the bandwidth of the phase-locked loop is widened, the gain of the amplifier is increased to enable the pull-in operation without lowering the loop gain, and the time required to transit from the out-of-sync state to the sync state is shortened. To be done.

Further, in the steady phase error state, as shown on the right side of FIG. 4, the output lower than the maximum output from the phase comparator 31 and the operating conditions of the low pass filter 22, the amplifier 23 and the VCXO 24 are added. Therefore, the corresponding proper operating conditions are read from the ROM.

Thus, for example, the low-pass filter 22
Turns on all the built-in switches to reduce the bandwidth,
The amplifier 23 reduces the gain from A ₁ → A ₀ , and the VCXO 24 shifts the bias voltage so that the steady phase error is reduced.

In other words, the operating conditions of the phase locked loop have been constant in the past and are optimal under certain conditions, but some points must be compromised under other conditions. According to the present invention, the phase locked loop can be operated under almost optimal conditions in each of the pull-in state and the out-of-sync state.

[0022]

As described in detail above, according to the present invention,
In each state, there is an effect that the phase synchronization means can be operated under almost optimum conditions.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a configuration diagram of a conventional example.

FIG. 4 is an operation explanatory diagram of first and second phase comparators in FIG.

[Explanation of symbols]

2 phase synchronization means 3 synchronization state monitoring means 4 storage means 21 first phase comparator 22 low pass filter 23 amplifier 24 voltage controlled oscillator

Claims (1)

[Claims] 1. A first phase comparison output corresponding to a phase difference between an input signal and an output signal of a voltage controlled oscillator (24) is taken out by a first phase comparator (21) and added to the voltage controlled oscillator. Thus, the phase synchronization means (2) for extracting the output signal synchronized with the input signal, and the second phase corresponding to the phase difference between the 90-degree shift output signal obtained by shifting the phase of the output signal by 90 degrees and the input signal. In a phase synchronization circuit having a synchronization state monitoring means (3) for transmitting an out-of-synchronization signal when the phase comparison output is out of the allowable range, all combinations of the second phase comparison output and the operating conditions of the phase synchronization means Is provided with a storage means (4) storing the proper operating conditions set corresponding to the above, and when the operating conditions of the second phase comparison output and the phase synchronizing means are applied, the phase synchronizing is performed under the proper operating conditions read from the storing means. That the means to operate means Phase locked loop circuit and butterflies.