JP2020182084A - Phase synchronization circuit - Google Patents

Abstract

To provide a phase synchronization circuit and a method for controlling phase synchronization, capable of detecting and recovering an unlocked state in phase synchronization in a high frequency region with a large frequency drift.SOLUTION: A phase synchronization circuit 100 of an embodiment of the present invention includes a control circuit 1 for detecting and recovering an unlocked state in phase synchronization of an output signal. The control circuit 1 includes: a first distributor 10 distributing the output signal OUT1 into two output signals OUT3, OUT 4; a delay line 12 delaying one output signal OUT3 of the first distributor 10; a first phase comparator 14 outputting a voltage S1 according to a phase difference between the other output signal OUT4 of the first distributor 10 and an output signal delayed by the delay line 12; and a logic circuit 16 that receives an output of the first phase comparator 14 and outputs a control signal for detecting and recovering an unlocked state in phase synchronization of the output signal.SELECTED DRAWING: Figure 1

Description

The present invention relates to a phase-locked loop, and more specifically, to a phase-locked loop including a control circuit for detecting and restoring the unlock of the phase-locked loop.

Conventionally, there are many methods for detecting a phase-locked unlock. In many of the conventional methods, the presence or absence of unlock is determined by detecting the phase difference between the signal to be locked and the reference signal or counting the frequency.

Patent Document 1 discloses an unlock signal detection method in a PLL circuit. In the unlock signal detection method, sampling is performed at a predetermined cycle, if unlocked, the counter counts up, and the value counted up at a predetermined number of cycles and a predetermined threshold value are set in the control unit. When the value counted up exceeds a predetermined threshold value, an alarm signal is output.

Patent Document 2 discloses an unlock detection circuit that detects an unlocked state of a PLL. In the unlock detection circuit, the reference signal to the PLL and the feedback signal from the PLL are adjusted by a pair of duty adjustment circuits for pulses having a constant duty ratio, and the phase error between the reference signal and the feedback signal is after the duty adjustment. If it is larger than the pulse width of the reference signal and the feedback signal after duty adjustment, it is output as an unlock signal, and unlock detection is possible with arbitrary sensitivity by the external control signal to the duty adjustment circuit.

Most of the conventional PLL phase synchronizations disclosed in Patent Documents 1 and 2 and the like relate to the phase synchronization in the RF region (for example, several tens of KHz to several hundreds of GHz) in which the frequency of the oscillator is stable, for example, a laser. It does not perform unlock detection and recovery of the phase synchronization in a high frequency region (for example, several tens to several hundreds THz) where the frequency drift is large.

JP-A-2008-104012 JP-A-2007-243736

An object of the present invention is to provide a phase-locked loop and a phase-locked loop control method capable of detecting and restoring the unlock of the phase-locked loop in a high-frequency region where the frequency drift is large.

The phase-locked loop of one aspect of the present invention includes a control circuit for detecting and restoring the unlock of the phase-locked loop of the output signal. The control circuit is composed of a first distributor that divides the output signal into two output signals, a delay line that delays one of the output signals of the first distributor, and a delay line that delays the other of the output signals of the first distributor. A first phase comparator that outputs a voltage corresponding to the phase difference from the delayed output signal, and a control for detecting the unlocking of the phase synchronization of the output signal and recovering from the output of the first phase comparator. Includes a logic circuit that outputs signals.

The control method of the phase-locked loop according to one aspect of the present invention includes a step of dividing the output signal of the phase-locked loop into two, a step of delaying one output signal after distribution by a delay line, and a step of delaying the output signal of the other after distribution. Phase synchronization of the output signal depending on the step of generating a voltage according to the phase difference between the output signal and one of the output signals after delay and whether or not the generated voltage is within a predetermined voltage range corresponding to the capture range. Includes a step to detect the presence or absence of unlocking.

The phase-locked loop of the present invention can achieve the following effects.
(A) Since the unlock of the phase synchronization can be detected by including the distributor, the delay line and the phase comparator in the control circuit, it is relatively easy and low cost.
(B) By including a logic circuit in the control circuit, not only unlock detection but also a mechanism for returning to the capture range and automatically returning to the capture range can be provided.
(C) Since the unlock detection is performed by detecting the frequency (more accurately, the voltage corresponding to the frequency) instead of the phase of the output signal, it is possible to prevent accidentally locking to another frequency.

It is a figure which shows the structure of the phase-locked loop of one Embodiment of this invention. It is a figure which shows the relationship between the frequency f of one Embodiment of this invention, and the signal (voltage) S1 corresponding to a phase difference. It is a figure which shows the flow of the control method of the phase-locked loop of one Embodiment of this invention. It is a figure which shows the time change of the signal (voltage) S1 according to the phase difference of one Embodiment of this invention, and the control signal S3 to the actuator which has a wide dynamic range.

An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration of a phase-locked loop according to an embodiment of the present invention. The phase-locked loop 100 includes the following configuration in addition to the phase comparator 22, the loop filter 24, and the oscillator 26 that form a so-called frequency negative feedback circuit. That is, the phase synchronization of the output signal OUT with the distributor (power splitter, hereinafter also simply referred to as a splitter) 20 that distributes the output signal OUT that feeds back the output of the oscillator 26 and the output signal OUT1 distributed by the splitter 20 as inputs. A control circuit 1 (enclosed part with a broken line) for detecting and recovering the unlocking of the above is included.

In the phase comparator 22, the loop filter 24, and the oscillator 26 that form the negative feedback circuit, the phase comparator 22 that receives one OUT2 of the output signal first distributed by the distributor 20 compares the phase difference with the reference signal. , The voltage corresponding to the phase difference is output to the loop filter 24 as a signal S4. The loop filter 24 has a function of proportionally and integratingly controlling (processing) the signal S4 from the phase comparator 22. The function (processing) of proportional and integral control can be switched off to integral control only by the logic circuit 16 described later in the control circuit 1. The loop filter 24 outputs a signal after proportional and integral control (processing) to the oscillator 26 as a control signal S5. The fast actuator A of the oscillator 26 receives the control signal S5 to change the oscillation frequency.

The oscillator 26 includes a fast actuator A (hereinafter, also simply referred to as actuator A) and an actuator B having a wide dynamic range (hereinafter, also simply referred to as actuator B). "Fast" in a fast actuator means that the frequency control speed is fast, and means a function that can quickly adjust a relatively small frequency range (deviation) such as within the capture range. "Wide dynamic range" in an actuator with a wide dynamic range means a range in which a relatively large frequency shift can be adjusted. For example, it means a function to return the frequency to the capture range when the capture range is greatly deviated. .. The capture range means a frequency width at which the phase synchronization can be returned (pulled in) to the locked state, and is a frequency width that serves as a reference for determining whether or not the phase synchronization is unlocked.

Examples of the oscillator 26 include a voltage controlled oscillator (VCO) and an external resonator type semiconductor laser (ECLD). In the case of VCO, the actuator A corresponds to the voltage applied to the crystal oscillator, and the actuator B corresponds to the temperature of the crystal oscillator. In the case of ECLD, the actuator A corresponds to the injection current of the semiconductor laser used, and the actuator B corresponds to the applied voltage of the piezo element that changes the length of the external resonator. The actuators A and B are controlled by the VCO or ECLD by changing the applied voltage, temperature, or injection current described above by the control signals S5 and S3 from the loop filter 24 or the logic circuit 16.

The control circuit 1 includes a splitter 10, a delay line 12, a phase comparator (mixer) 14, and a logic circuit 16. The splitter 10 is a power splitter similar to the splitter 20. The splitter 10 receives the output signal OUT1 distributed by the splitter 20 and further distributes it to the two output signals OUT3 and OUT4. The delay line 12 delays OUT3 on one side of the distributed output signal. For the delay line 12, a cable having a uniform characteristic impedance can be used. The delay amount (delay time) can be set according to the length of the cable. As the cable, for example, a coaxial cable can be used. Coaxial cable has a delay time of about 5 ns per meter, for example.

The phase comparator 14 outputs an output S1 (voltage V) according to the phase difference between the other OUT4 of the output signal of the splitter 10 and the output signal OUT3 delayed by the delay line 12. Voltage V is
V ∝ cos (2πft)
It changes with. f is the frequency of the signal and t is the delay time. When t is constant, V changes depending on f, so that the frequency f of the output signal is converted into the voltage V.

The logic circuit 16 can be configured by, for example, an FPGA (field-programmable gate array). The logic circuit 16 receives the output S1 of the phase comparator 14 and detects the unlocking of the phase synchronization of the output signal OUT of the oscillator 26. The detection of the unlock of the phase synchronization is determined by whether or not the voltage of the output S1 of the phase comparator 14 is within a predetermined voltage range corresponding to the capture range. In the following description, it may be described as "whether or not the frequency of the output signal is within the capture range", but it is used in the same meaning.

FIG. 2 is a diagram showing the relationship between the frequency f (Hz) of the embodiment of the present invention and the output (voltage) S1 (V) according to the phase difference. The voltage width ΔV corresponding to the frequency width of the capture range of the output (voltage) S1 (V) is preset as shown in FIG. The logic circuit 16 determines that the phase-locked loop is unlocked when the voltage S1 (V) is not within the predetermined voltage width ΔV.

When the logic circuit 16 detects the unlocking of the phase synchronization, the logic circuit 16 outputs a control signal for its recovery. Specifically, the logic circuit 16 outputs a logic signal S2 for turning off the integration control to the loop filter 24. The loop filter 24 performs only proportional control with respect to the signal S4 output from the phase comparator 22 and outputs the control signal S5 to the actuator A of the oscillator 26. At the same time, the logic circuit 16 outputs a control signal S3 for returning the unlock to the actuator B of the oscillator 26.

In the oscillator 26, the actuator B that has received the control signal S3 forcibly changes the frequency so that the frequency of the output signal OUT falls within the capture range. The output signal OUT is sequentially fed back, distributed by the splitter 10, and then input to the control circuit 1. In the logic circuit 16, it is determined whether or not the capture range is within the above-mentioned capture range. When the frequency of the output signal OUT enters the capture range, only the proportional control of the loop filter 24 is enabled, so that the actuator A receiving the control signal S5 immediately draws the frequency to the frequency of the reference signal. After that, the logic circuit 16 outputs a logic signal S2 for turning on the integral control to the loop filter 24, and restarts the proportional and integral control of the loop filter 24.

When the frequency of the output signal OUT is within the capture range, more accurately, when the voltage of the output S1 of the phase comparator 14 is within the predetermined voltage range corresponding to the capture range, the phase synchronization of the output signal OUT Is performed as follows using the phase comparator 22, the loop filter 24, and the oscillator 26 constituting the negative feedback circuit of FIG. The phase comparator 22 that receives one OUT2 of the distributed output signal compares the phase difference with the reference signal, and outputs the voltage (error signal) corresponding to the phase difference to the loop filter 24 as the signal S4. The loop filter 24 performs proportional integration control so that the voltage of the error signal becomes zero, and outputs the control signal S5 to the actuator A of the oscillator 26. Actuator A adjusts the frequency of oscillator 26.

When the oscillator 26 is an external resonator type semiconductor laser (ECLD), the frequency generally drifts slowly due to the influence of room temperature, atmospheric pressure, etc., and the actuator A alone often exceeds the dynamic range and the lock is dropped. Therefore, the logic circuit 16 receives the signal S6 for drift correction from the loop filter 24 and outputs the control signal S3 to the actuator B. The actuator B adjusts the oscillation frequency of the oscillator 26 so that the voltage of the control signal S5 to the actuator A becomes a constant value. When the oscillator 26 is a voltage controlled oscillator (VCO), the actuator B is not always required for phase synchronization, but it is required for automatic recovery of phase synchronization.

Next, the flow of the control method of the phase-locked loop according to the embodiment of the present invention will be described with reference to FIG. In the following description, an example in which the phase-locked loop 100 of the embodiment of FIG. 1 is used is also described.

In step S10, the output signal of the oscillator is divided into two. In the phase-locked loop 100 of FIG. 1, the output signals OUT1 and 2 of the oscillator 26 divided into two by the splitter 20 are further distributed to the two output signals OUT3 and OUT4 by the splitter 10.

In step S11, one output signal after distribution is delayed by a delay line. In the phase-locked loop 100 of FIG. 1, it corresponds to delaying the output signal OUT3 after distribution by the splitter 10 by the delay line 12. As for the example of the delay line 12 and its delay amount (delay time), as described above, for example, a coaxial cable can be used, and the delay time can be set according to the length thereof.

In step S12, a voltage V1 corresponding to the phase difference between the other output signal after distribution and the one output signal after delay is generated. In the phase-locked loop 100 of FIG. 1, the phase comparator 14 outputs a signal S1 having a voltage V1 according to the phase difference between the output signal 4 and the delayed output signal OUT3.

In step S13, it is detected whether or not the voltage V1 is within a predetermined voltage range corresponding to the capture range. In the phase-locked loop 100 of FIG. 1, the logic circuit 16 detects whether or not the voltage V1 of the signal S1 received from the phase comparator 14 is within a predetermined voltage range corresponding to the capture range. For example, the voltage width ΔV in FIG. 2 described above corresponds to the predetermined voltage width.

In step S14, if the determination in step S13 is No, that is, if the voltage V1 is not within the predetermined voltage range corresponding to the capture range, it is determined that the phase synchronization is unlocked and the integration control of the loop filter is turned off. .. In the phase-locked loop 100 of FIG. 1, the logic circuit 16 outputs the logic signal S2 for turning off the integration control to the loop filter 24. The loop filter 24 receives the logic signal S2, turns off the integration control, and performs only proportional control of the input signal S4.

In step S15, the oscillation frequency of the oscillator is controlled by an actuator having a wide dynamic range. In the phase-locked loop 100 of FIG. 1, the logic circuit 16 outputs a control signal S3 for returning the unlock to the actuator B of the oscillator 26. In the oscillator 26, the actuator B that has received the control signal S3 forcibly changes the frequency so that the frequency of the output signal OUT falls within the capture range.

After step 15, the process returns to step S10, and steps S10 and subsequent steps are further executed. When it is detected in step S13 that the voltage V1 is within a predetermined voltage range corresponding to the capture range, in step S17, a voltage V2 corresponding to the phase difference between the output signal of the oscillator and the reference signal is generated. In the phase-locked loop 100 of FIG. 1, the phase comparator 22 that receives one OUT2 of the distributed output signals compares the phase difference with the reference signal, and the loop filter 24 is used as the signal S4 of the voltage V2 according to the phase difference. Output to.

In step S18, the loop filter performs proportional integration control according to the voltage V2. In the phase-locked loop 100 of FIG. 1, the loop filter 24 performs proportional integration control so that the voltage V2 of the signal S4 becomes zero, and outputs the control signal S5 to the actuator A of the oscillator 26.

In step S19, the oscillation frequency of the oscillator is controlled by a fast actuator. In the phase-locked loop 100 of FIG. 1, the actuator A that receives the control signal S5 adjusts the frequency of the oscillator 26. The frequency of the output signal is drawn into the frequency of the reference signal by controlling the oscillation frequency based on the control signal S5.

In the execution of step S18, when the off state of the integral control of the loop filter in step S14 is maintained, the loop filter 24 performs only proportional control so that the voltage V2 of the signal S4 becomes zero, and the control signal thereof. S5 is output to the actuator A of the oscillator 26. The frequency of the output signal is drawn into the frequency of the reference signal by controlling the oscillation frequency based on the control signal S5. After that, the integration control of the loop filter in step 16 is turned on. In the phase-locked loop 100 of FIG. 1, the logic circuit 16 outputs the logic signal S2 for turning on the integration control to the loop filter 24. The loop filter 24 receives the logic signal S2, turns on the integration control, and returns to the state of performing the proportional integration control of the input signal S4.

In step S20, the oscillation frequency of the oscillator is controlled by an actuator having a wide dynamic range. The control in step S20 is performed when the oscillator is an external cavity type semiconductor laser (ECLD). The reason is as described above. In the phase-locked loop 100 of FIG. 1, the logic circuit 16 outputs the control signal S3 to the actuator B of the oscillator 26. In the oscillator 26, the actuator B that receives the control signal S3 adjusts the oscillation frequency of the oscillator 26 so that the voltage of the control signal S5 to the actuator A becomes a constant value.

Using the phase-locked loop of the present invention, experiments were conducted to detect and restore the phase-locked unlock of the external cavity type semiconductor laser (ECLD). In the experiment, an optical frequency comb based on a Nd: YAG laser (1064 nm) stabilized in a ULE (Ultra Low Expansion) optical resonator was used as a reference master laser. The 1156 nm component of the optical frequency comb was wavelength-converted to 578 nm by generating a second harmonic using a non-linear element. ECLD (1156 nm) was used as a slave laser to be controlled, and the wavelength was converted to 578 nm by generating a second harmonic. The output lights of the 578 nm optical frequency comb and ECLD were superposed, and the beat signal was detected by a photodetector. The phase synchronization of the oscillation frequency of the ECLD was performed by performing the phase synchronization of the frequency of the beat signal with respect to the reference signal of 30 MHz.

FIG. 4 is a diagram in which the time change of the signal (voltage) S1 according to the phase difference of one embodiment of the present invention and the control signal S3 to the actuator having a wide dynamic range at that time is measured. An actuator with a wide dynamic range is an applied voltage to a piezo element that changes the length of the external cavity. In FIG. 4, the optical frequency comb of the second harmonic of 578 nm is blocked between 0.6 and 0.7 seconds indicated by A to forcibly create an unlocked state. The control of the external resonator length by the control signal S3 starts from 0.6 seconds, and at the time of 1 second, the signal S1 enters the voltage width ΔV (0.22 to 0.32 V) corresponding to the capture range, and the phase is synchronized. It can be seen that the unlock is released and the lock state is set.

Through this experiment, the phase synchronization of the oscillation frequency of ECLD could be maintained unattended for one day or more. Unlike the crystal oscillator used in the RF region, the laser, which is an oscillator in the optical region, is vulnerable, and it has been difficult to maintain phase synchronization for a long period of time by conventional methods. The method of the present invention was able to confirm the long-term duration of the phase synchronization of the oscillation frequency of the laser, which was not easy until now.

An embodiment of the present invention has been described with reference to the drawings. However, the present invention is not limited to these embodiments. Further, the present invention can be carried out in a mode in which various improvements, modifications and modifications are added based on the knowledge of those skilled in the art without departing from the spirit of the present invention.

The phase-locked loop of the present invention can be used to detect and restore the phase-locked loop of an oscillator in technical fields such as lasers, high-frequency semiconductors, computers, and wireless communications.

1 Control circuit 10 1st distributor (splitter)
12 Delay line 14 First phase comparator (mixer)
16 Logic circuit 20 Second distributor (splitter)
22 Second phase comparator (mixer)
24 Loop filter 26 Oscillator 100 Phase-locked loop

Claims (7)

A phase-locked loop that includes a control circuit for detecting and restoring the phase-locked loop of the output signal.
The control circuit
A first distributor that distributes the output signal into two output signals,
A delay line that delays one of the output signals of the first distributor, and
A first phase comparator that outputs a voltage corresponding to the phase difference between the other output signal of the first distributor and the output signal delayed by the delay line.
A phase-locked loop including a logic circuit that receives the output of the first phase comparator and outputs a control signal for detecting the unlocking of the phase synchronization of the output signal and returning the output signal. Oscillator and
A second distributor that distributes the output signal of the oscillator into two output signals and outputs one of them to the first distributor.
A second phase comparator that outputs a voltage corresponding to the phase difference between the other of the output signals of the second distributor and the reference signal, and
The phase-locked loop according to claim 1, further comprising a loop filter that receives the output of the second phase comparator and outputs a control signal for phase synchronization of the output signal to the oscillator. The loop filter has a function of proportionally and integratingly controlling the output of the second phase comparator, and the logic circuit turns off the integrating control to the loop filter in response to the detection of unlocking of the phase synchronization. The phase-locked loop according to claim 2, which outputs the logic signal of the above. The logic circuit according to claim 2 or 3, wherein the logic circuit determines the detection of the unlock of the phase synchronization based on whether or not the output voltage of the first phase comparator is within a predetermined voltage range corresponding to the capture range. Phase-locked loop. The phase-locked loop according to any one of claims 1 to 4, wherein the delay line includes a coaxial cable whose length is set according to a delay amount. It is a control method of a phase-locked loop.
The step of dividing the output signal of the phase-locked loop into two,
A step of delaying one output signal after distribution by a delay line,
A step of generating a voltage corresponding to the phase difference between the other output signal after distribution and one output signal after delay,
A control method including a step of detecting whether or not the phase synchronization of the output signal is unlocked depending on whether or not the generated voltage is within a predetermined voltage range corresponding to the capture range. The control method according to claim 6, wherein the delay line includes a coaxial cable whose length is set according to the amount of delay.

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