JP7291376B2 - Phase lock circuit - Google Patents

Description

The present invention relates to a phase locked loop circuit, and more particularly to a phase locked loop circuit including a control circuit for detecting and restoring unlocked phase lock.

Conventionally, there are many methods for detecting unlocking of phase lock. Many of the conventional methods determine whether or not the lock is unlocked by detecting the phase difference between the signal to be locked and the reference signal or by counting the frequency.

Patent document 1 discloses an unlock signal detection method in a PLL circuit. In the unlock signal detection method, sampling is performed at a predetermined period, a counter counts up when the unlock signal is unlocked, and the value counted up at the predetermined number of times and a predetermined threshold value are calculated by a control unit. and outputs an alarm signal when the counted-up value exceeds a predetermined threshold value.

Patent Document 2 discloses an unlock detection circuit that detects the unlocked state of the PLL. In the unlock detection circuit, the reference signal to the PLL and the feedback signal from the PLL are adjusted to pulses with a constant duty ratio by a pair of duty adjustment circuits, and the phase error between the reference signal and the feedback signal after duty adjustment is When the reference signal is larger than the pulse width of the feedback signal after duty adjustment, it is output as an unlock signal so that unlock detection can be performed with arbitrary sensitivity by an external control signal to the duty adjustment circuit.

Most of the conventional PLL phase synchronization disclosed in Patent Documents 1 and 2 are related to phase synchronization in the RF region (for example, several tens of kHz to several hundreds of GHz) where the frequency of the oscillator is stable. However, it does not detect and restore the unlocking of phase synchronization in a high frequency region (for example, several tens to several hundred THz) where frequency drift is large.

JP 2008-104012 JP 2007-243736

SUMMARY OF THE INVENTION It is an object of the present invention to provide a phase locked loop circuit and a phase locked control method capable of detecting and recovering unlocked phase lock in a high frequency region where frequency drift is large.

A phase locked loop circuit of one aspect of the present invention includes a control circuit for detecting and restoring unlocked phase synchronization of an output signal. The control circuit comprises a first divider that divides an output signal into two output signals, a delay line that delays one of the output signals of the first divider, and a delay line that delays one of the output signals of the first divider. A first phase comparator that outputs a voltage corresponding to the phase difference with the delayed output signal, and detection of unlocking of phase synchronization of the output signal in response to the output of the first phase comparator and control for recovery thereof. and a logic circuit that outputs a signal.

A method for controlling a phase locked loop circuit according to one aspect of the present invention includes the steps of: dividing an output signal of the phase locked loop circuit into two; delaying one of the divided output signals by a delay line; A step of generating a voltage corresponding to the phase difference between the output signal and one of the delayed output signals, and phase synchronization of the output signal based on whether the generated voltage is within a predetermined voltage width corresponding to the capture range. and detecting the presence or absence of unlocking.

The phase locked loop circuit of the present invention can have the following effects.
(a) Since the control circuit includes a distributor, a delay line and a phase comparator, it is possible to detect the unlocking of the phase synchronization, so that it is relatively simple and inexpensive.
(b) By including a logic circuit in the control circuit, it is possible to provide not only unlock detection but also a mechanism for automatically returning to the capture range.
(c) Unlock detection is performed by detecting the frequency (more precisely, the voltage corresponding to the frequency) rather than the phase of the output signal, thereby preventing erroneous locking to a different frequency.

It is a figure which shows the structure of the phase locked loop circuit of one Embodiment of this invention. It is a figure which shows the relationship between the frequency f of one Embodiment of this invention, and signal (voltage) S1 according to a phase difference. It is a figure which shows the flow of the control method of the phase synchronous circuit of one Embodiment of this invention. FIG. 4 is a diagram showing temporal changes of a signal (voltage) S1 corresponding to a phase difference and a control signal S3 to an actuator having a wide dynamic range according to an embodiment of the present invention;

An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing the configuration of a phase locked loop circuit according to one embodiment of the present invention. The phase synchronization circuit 100 includes the following configuration in addition to the phase comparator 22, the loop filter 24, and the oscillator 26, which form a so-called frequency negative feedback circuit. Namely, a splitter (power splitter, hereinafter simply referred to as a splitter) 20 for splitting the output signal OUT obtained by feeding back the output of the oscillator 26, and a phase synchronization of the output signal OUT which receives the output signal OUT1 split by the splitter 20 as an input. and a control circuit 1 (enclosed by a dashed line) for detecting and restoring unlocking of the .

In the phase comparator 22, the loop filter 24 and the oscillator 26 that constitute the negative feedback circuit, the phase comparator 22 that first receives OUT2, one of the output signals distributed by the distributor 20, compares the phase difference with the reference signal. , and outputs a voltage corresponding to the phase difference to the loop filter 24 as a signal S4. The loop filter 24 has the function of proportional and integral control (processing) of the signal S4 from the phase comparator 22 . The proportional and integral control function (processing) can be switched to only proportional control by turning off the integral control by a logic circuit 16 in the control circuit 1, which will be described later. The loop filter 24 outputs the signal after proportional and integral control (processing) to the oscillator 26 as the control signal S5. The fast actuator A of the oscillator 26 receives its control signal S5 and changes its oscillation frequency.

The oscillator 26 includes a fast actuator A (hereinafter simply referred to as actuator A) and a wide dynamic range actuator B (hereinafter simply referred to as actuator B). "Fast" in the case of a fast actuator means that the frequency control speed is fast, and means the ability to quickly adjust a relatively small frequency range (deviation) such as within the capture range. "Wide dynamic range" in terms of actuators with a wide dynamic range means a range in which relatively large frequency deviations can be adjusted. . Note that the capture range means a frequency width capable of returning (pulling in) the phase synchronization to a locked state, and is a frequency width used as a reference for determining whether or not the phase synchronization is unlocked.

Examples of the oscillator 26 include a voltage controlled oscillator (VCO) and an external cavity semiconductor laser (ECLD). In the case of the VCO, actuator A corresponds to the voltage applied to the crystal oscillator, and actuator B corresponds to the temperature of the crystal oscillator. In the case of ECLD, the actuator A corresponds to the injection current of the semiconductor laser used, and the actuator B corresponds to the applied voltage of the piezoelectric element that changes the external cavity length. The control of the actuators A and B in the VCO and ECLD is performed by changing the applied voltage, temperature, or injected current with the control signals S5 and S3 from the loop filter 24 or the logic circuit 16. FIG.

Control circuit 1 includes splitter 10 , delay line 12 , phase comparator (mixer) 14 and logic circuit 16 . Splitter 10 is a power splitter similar to splitter 20 . The splitter 10 receives the output signal OUT1 split by the splitter 20 and further splits it into two output signals OUT3 and OUT4. A delay line 12 delays one of the split output signals OUT3. The delay line 12 can use a cable with uniform characteristic impedance. The amount of delay (delay time) can be set according to the length of the cable. A coaxial cable, for example, can be used as the cable. A coaxial cable, for example, has a delay time of about 5 ns per meter.

The phase comparator 14 outputs an output S1 (voltage V) corresponding to the phase difference between the other output signal OUT4 of the splitter 10 and the output signal OUT3 delayed by the delay line 12 . The voltage V is
V ∝ cos(2πft)
change with f is the signal frequency and t is the delay time. When t is constant, V changes depending on f, so the frequency f of the output signal is converted to voltage V.

The logic circuit 16 can be composed of, for example, an FPGA (field-programmable gate array). The logic circuit 16 receives the output S1 of the phase comparator 14 and detects unlocking of the phase synchronization of the output signal OUT of the oscillator 26 . Detection of unlocking of phase synchronization is determined by whether or not the voltage of the output S1 of the phase comparator 14 is within a predetermined voltage width corresponding to the capture range. In the following description, "whether or not the frequency of the output signal is within the capture range" may be used with the same meaning.

FIG. 2 is a diagram showing the relationship between the frequency f (Hz) and the output (voltage) S1 (V) according to the phase difference in one embodiment of the present invention. A voltage width ΔV corresponding to the frequency width of the capture range of the output (voltage) S1 (V) is preset as shown in FIG. Logic circuit 16 determines that the phase lock is unlocked when voltage S1 (V) is not within a predetermined voltage range ΔV.

When the logic circuit 16 detects unlocking of the phase synchronization, it outputs a control signal for the recovery. Specifically, the logic circuit 16 outputs a logic signal S2 for turning off integration control to the loop filter 24 . The loop filter 24 performs only proportional control on the signal S4 output from the phase comparator 22 and outputs it to the actuator A of the oscillator 26 as a control signal S5. The logic circuit 16 simultaneously outputs a control signal S3 for returning the unlock to the actuator B of the oscillator 26. FIG.

In the oscillator 26, the actuator B, which receives the control signal S3, forcibly changes the frequency of the output signal OUT so that it falls within the capture range. The output signal OUT is sequentially fed back and input to the control circuit 1 after being distributed by the splitter 10 . The logic circuit 16 determines whether or not it is within the capture range described above. When the frequency of the output signal OUT enters the capture range, it is immediately pulled into the frequency of the reference signal by the actuator A receiving the control signal S5 because only the proportional control of the loop filter 24 is valid. After that, the logic circuit 16 outputs the logic signal S2 for turning on the integral control to the loop filter 24, and restarts the proportional and integral control of the loop filter 24. FIG.

When the frequency of the output signal OUT falls within the capture range, more precisely, when the voltage of the output S1 of the phase comparator 14 falls within a predetermined voltage width corresponding to the capture range, the phase synchronization of the output signal OUT is performed as follows using the phase comparator 22, the loop filter 24, and the oscillator 26 that constitute the negative feedback circuit of FIG. Phase comparator 22 receives one of the distributed output signals OUT2, compares the phase difference with the reference signal, and outputs a voltage (error signal) corresponding to the phase difference to loop filter 24 as signal S4. The loop filter 24 performs proportional integral control so that the voltage of the error signal becomes zero, and outputs the control signal S5 to the actuator A of the oscillator 26. FIG. Actuator A adjusts the frequency of oscillator 26 .

When the oscillator 26 is an external cavity semiconductor laser (ECLD), the frequency generally drifts slowly under the influence of room temperature and atmospheric pressure, and actuator A alone often exceeds the dynamic range and loses lock. Therefore, logic circuit 16 receives signal S6 for drift correction from loop filter 24 and outputs control signal S3 to actuator B. FIG. Actuator B adjusts the oscillation frequency of oscillator 26 so that the voltage of control signal S5 to actuator A is constant. If oscillator 26 is a voltage controlled oscillator (VCO), actuator B is not necessarily required for phase locking, but is required for automatic recovery of phase locking.

Next, the flow of the control method for the phase locked loop circuit according to one embodiment of the present invention will be described with reference to FIG. In the following description, an example of using the phase locked loop circuit 100 of the embodiment of FIG. 1 is also described.

In step S10, the output signal of the oscillator is divided into two. In the phase synchronization circuit 100 of FIG. 1, the output signals OUT1 and 2 of the oscillator 26 split into two by the splitter 20 are further split by the splitter 10 into two output signals OUT3 and OUT4.

In step S11, one of the distributed output signals is delayed by a delay line. In the phase synchronization circuit 100 of FIG. 1, delaying the output signal OUT3 after being split by the splitter 10 by the delay line 12 corresponds to this. As for the example of the delay line 12 and its delay amount (delay time), for example, a coaxial cable can be used and the delay time can be set according to its length.

In step S12, a voltage V1 is generated according to the phase difference between the other output signal after distribution and the one output signal after delay. In the phase locked loop circuit 100 of FIG. 1, the phase comparator 14 outputs the signal S1 of the voltage V1 corresponding to the phase difference between the output signal 4 and the delayed output signal OUT3.

At step S13, it is detected whether or not the voltage V1 is within a predetermined voltage width corresponding to the capture range. In the phase locked loop circuit 100 of FIG. 1, the logic circuit 16 detects whether the voltage V1 of the signal S1 received from the phase comparator 14 is within a predetermined voltage width corresponding to the capture range. The predetermined voltage width corresponds to, for example, the voltage width ΔV in FIG. 2 described above.

In step S14, if the determination in step S13 is No, that is, if the voltage V1 is not within the predetermined voltage width corresponding to the capture range, it is determined that the phase synchronization is unlocked, and the integral control of the loop filter is turned off. . In the phase locked loop circuit 100 of FIG. 1, the logic circuit 16 outputs a logic signal S2 to the loop filter 24 for turning off integration control. The loop filter 24 receives the logic signal S2, turns off the integral control, and performs only the proportional control of the input signal S4.

In step S15, the oscillation frequency of the oscillator is controlled by an actuator with a wide dynamic range. In the phase locked loop circuit 100 of FIG. 1, the logic circuit 16 outputs a control signal S3 for restoring the unlock to the actuator B of the oscillator 26. FIG. In the oscillator 26, the actuator B, which receives the control signal S3, forcibly changes the frequency of the output signal OUT so that it falls within the capture range.

After step S15, the process returns to step S10, and steps after step S10 are further executed. If it is detected in step S13 that the voltage V1 is within a predetermined voltage range corresponding to the capture range, then in step S17 a voltage V2 is generated according to the phase difference between the output signal of the oscillator and the reference signal. In the phase locked loop circuit 100 of FIG. 1, the phase comparator 22 that receives one of the distributed output signals OUT2 compares the phase difference with the reference signal, and the loop filter 24 generates a signal S4 of voltage V2 corresponding to the phase difference. Output to

At step S18, the loop filter performs proportional integral control according to the voltage V2. In the phase locked loop circuit 100 of FIG. 1, the loop filter 24 performs proportional integral control so that the voltage V2 of the signal S4 becomes zero, and outputs the control signal S5 to the actuator A of the oscillator 26. FIG.

In step S19, a fast actuator controls the oscillation frequency of the oscillator. In the phase locked loop circuit 100 of FIG. 1, the actuator A that receives the control signal S5 adjusts the frequency of the oscillator 26. In FIG. The frequency of the output signal is drawn to the frequency of the reference signal by controlling the oscillation frequency based on the control signal S5.

In the execution of step S18, if the off state of the integration control of the loop filter in step S14 is maintained, the loop filter 24 performs only proportional control so that the voltage V2 of the signal S4 becomes zero, and the control signal S5 is output to actuator A of oscillator 26 . The frequency of the output signal is drawn to the frequency of the reference signal by controlling the oscillation frequency based on the control signal S5. Thereafter, step 16 of turning on integration control of the loop filter is executed. In the phase locked loop circuit 100 of FIG. 1, the logic circuit 16 outputs a logic signal S2 to the loop filter 24 for turning on integration control. The loop filter 24 receives the logic signal S2, turns on the integral control, and returns to the state of performing the proportional integral control of the input signal S4.

In step S20, the oscillation frequency of the oscillator is controlled by an actuator with a wide dynamic range. The control in step S20 is executed when the oscillator is an external cavity semiconductor laser (ECLD). The reason for this is already mentioned above. In phase locked loop 100 of FIG. 1, logic circuit 16 outputs control signal S3 to actuator B of oscillator . In the oscillator 26, the actuator B that receives the control signal S3 adjusts the oscillation frequency of the oscillator 26 so that the voltage of the control signal S5 to the actuator A becomes constant.

Using the phase locked loop circuit of the present invention, an experiment was conducted to detect and restore the phase locked state of an external cavity semiconductor laser (ECLD). In the experiment, an optical frequency comb based on a Nd:YAG laser (1064 nm) stabilized in a ULE (Ultra Low Expansion) optical resonator was used as a reference master laser. The 1156 nm component of the optical frequency comb was wavelength-converted to 578 nm by second harmonic generation using a nonlinear element. An ECLD (1156 nm) was used as a slave laser to be controlled, and the wavelength was converted to 578 nm by second harmonic generation. The output light from the 578 nm optical frequency comb and the ECLD were superimposed, and a beat signal was detected with a photodetector. The oscillation frequency of the ECLD was phase-locked by synchronizing the frequency of the beat signal with respect to the reference signal of 30 MHz.

FIG. 4 is a graph showing time changes of the signal (voltage) S1 according to the phase difference and the control signal S3 to the actuator having a wide dynamic range in the embodiment of the present invention at that time. A wide dynamic range actuator is the applied voltage to the piezo element that changes the external resonator length. In FIG. 4, an unlocked state is forcibly created by interrupting the optical frequency comb of the second harmonic of 578 nm between 0.6 and 0.7 seconds indicated by A. In FIG. Control of the external resonator length by the control signal S3 starts from 0.6 seconds, and at the time of 1 second, the signal S1 enters the voltage width ΔV (0.22 to 0.32 V) corresponding to the capture range, and the phase synchronization is stopped. It can be seen that the unlock is canceled and the lock state is reached.

Through this experiment, the phase synchronization of the oscillation frequency of the ECLD could be maintained unattended for more than one day. Unlike crystal oscillators used in the RF region, lasers, which are oscillators in the optical region, are fragile, and it has been difficult to maintain phase synchronization for a long period of time using conventional methods. The method of the present invention was able to confirm the long-term maintenance of the phase synchronization of the oscillation frequency of the laser, which was not easy until now.

Embodiments of the present invention have been described with reference to the drawings. However, the invention is not limited to these embodiments. Furthermore, the present invention can be implemented in aspects with various improvements, modifications, and variations based on the knowledge of those skilled in the art without departing from the scope of the invention.

INDUSTRIAL APPLICABILITY The phase locked loop circuit of the present invention can be used to detect and restore the phase locked state of oscillators in technical fields such as lasers, high frequency semiconductors, computers, and wireless communications.

1 control circuit 10 first distributor (splitter)
12 delay line 14 first phase comparator (mixer)
16 logic circuit 20 second distributor (splitter)
22 second phase comparator (mixer)
24 loop filter 26 oscillator 100 phase synchronization circuit

Claims (7)

an oscillator;
a second distributor that distributes the output signal of the oscillator into two output signals and outputs one of them to the first distributor;
a second phase comparator that outputs a voltage corresponding to a phase difference between the other output signal of the second divider and a reference signal;
a loop filter having a function of proportionally and integrally controlling the output of the second phase comparator and outputting a first control signal for phase synchronization of the output signal to the oscillator;
a control circuit;
The control circuit is
the first distributor receiving the output signal from the second distributor and distributing it into two output signals;
a delay line for delaying one of the output signals of the first distributor according to the frequency of the output signal ;
a first phase comparator that outputs a voltage corresponding to the phase difference between the other output signal of the first distributor and the output signal delayed by the delay line;
a logic circuit that detects whether or not the phase synchronization is unlocked according to the output of the first phase comparator, whether the output signal is out of a predetermined frequency range ,
When the logic circuit detects that the output signal is out of a predetermined frequency range, second control for forcing the oscillator to change the frequency so that the output signal falls within the predetermined frequency range. A phase locked loop that outputs a signal to the oscillator . The oscillator includes a first actuator that receives the first control signal and adjusts a frequency deviation of the output signal, and a second actuator that receives the second control signal and adjusts a frequency deviation larger than that of the first actuator. , including
2. The phase locked loop circuit according to claim 1, wherein said second actuator forcibly changes the frequency of said output signal so as to fall within said predetermined frequency range upon receiving a second control signal from said logic circuit. The loop filter has a function of proportionally and integrally controlling the output of the second phase comparator, and the logic circuit turns off integral control of the loop filter in response to detection of unlocking of the phase synchronization. 3. The phase locked loop circuit according to claim 1 , which outputs a logic signal of . 4. Of claims 1 to 3 , wherein said logic circuit determines whether or not said unlocked state of said phase synchronization is detected based on whether the output voltage of said first phase comparator is within a predetermined voltage width corresponding to a capture range. A phase locked loop circuit according to any one of the preceding claims. 5. The phase locked loop circuit according to claim 1, wherein said delay line includes a coaxial cable whose length is set according to the amount of delay. an oscillator, a second divider that divides the output signal of the oscillator into two output signals and outputs one of them to the first divider, and the phase difference between the other of the output signals of the second divider and the reference signal a second phase comparator that outputs a corresponding voltage; and a function of proportionally and integrally controlling the output of the second phase comparator, and a first control signal for phase synchronization of the output signal to the oscillator. A control method for a phase locked loop circuit comprising a loop filter that outputs and a control circuit ,
By the control circuit,
receiving and dividing the output signal from the second splitter into two output signals;
delaying one of the distributed output signals by a delay line according to the frequency of the output signal ;
generating a voltage corresponding to a phase difference between the other output signal after distribution and the one output signal after delay;
a step of detecting whether the output signal is out of a predetermined frequency range according to the generated voltage, that is, whether or not the phase synchronization is unlocked;
upon detecting that the output signal is out of the predetermined frequency range, sending a second control signal to the oscillator to force the oscillator to change frequency so that the output signal falls within the predetermined frequency range; and outputting . 7. The control method according to claim 6, wherein said delay line includes a coaxial cable whose length is set according to the amount of delay.

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