RU2814213C1 - Frequency-phase detector with minimum duration of control pulses - Google Patents

Abstract

FIELD: measurement.

SUBSTANCE: invention relates to frequency-phase detectors (FPD). Frequency-phase detector circuit consists of two triggers with asynchronous reset 1, 2, three logic elements with a logic multiplication function 3, 6, 7, two delay elements 4, 5. At that, to the first input of trigger 1 the signal of the adjusted frequency is supplied, and a reference frequency signal is supplied to the first input of trigger 2, wherein the output of trigger 1 is connected to the first input of logic element 3, and to the first input of logic element 6, and the input of delay element 5. Output of trigger 2 is connected to the second input of logic element 3, and to the second input of logic element 7, and to the input of delay element 4; output of delay element 4 is connected to the second inverse input of logic element 6, and the output of delay element 5 is connected to the first inverse input of logic element 7; wherein control voltage pulses are generated at outputs of logic elements 6, 7.

EFFECT: providing the possibility of independent adjustment of duration of actuation of control pulses of FPD voltage irrespective of actuation time of circuit of asynchronous reset of triggers.

1 cl, 3 dwg

Description

Field of technology to which the invention relates

The invention relates to the field of automatic control, startup, synchronization and stabilization of generators of electronic oscillations or pulses.

State of the art

Among the existing methods for synthesizing harmonic signals, phase-locked loop (PLL) circuits have become widespread. Systems with PLL refer to tracking systems with a comparing device made in the form of a phase discriminator (phase detector). A passive balanced mixer, a subharmonic mixer, an exclusive OR logic element, etc. can be used as a phase comparison circuit. The disadvantage of such circuits is the limited capture bandwidth, which requires the introduction of additional measures to ensure loop synchronism.

A known circuit is a frequency-phase detector (FPD) according to patent US 4322643, March 30, 1982, which proposes a phase comparator circuit based on digital logic circuits with a feedback loop and reset of the trigger state, which provides, in addition to comparing the phases of input signals, also a comparison of signal frequencies. This feature maximizes the PLL loop bandwidth to the limit that a voltage controlled oscillator (VCO) can provide. The PFD circuit generates short control pulses for the keys of the charge-discharge unit (CDB), the duration of which corresponds to the phase difference of the input signals.

The disadvantage of this scheme is the artificially increased duration of control pulses due to the delay in propagation of the trigger reset signal, which leads to the simultaneous activation of the drain and source modes of the ZRB block, which leads to an increase in the average effective value of the noise voltage.

The closest to the claimed technical solution is a PFD circuit with two signal delay blocks, differing in that they are triggered by the rise or fall of the signal. In this case, the duration of the reset pulse is determined by the difference in the delay time of the two blocks and is selected so as to have a minimum value sufficient to trigger the reset circuit in the trigger blocks US 6192094 B1, 02/20/2001. The disadvantage of this solution is the extended time of control pulses, which consists of the reset time of the triggers, the additional delay time during which the switches of the charge-discharge unit operate and other effects that further delay the time of active operation of the keys.

Disclosure of the invention

The problem to be solved by the claimed invention is the creation of a PFD circuit with a minimum duration of control pulses to reduce the average effective value of the noise voltage.

This problem is solved due to the fact that the claimed circuit of the frequency-phase detector, characterized in that it consists of a trigger with an asynchronous reset, synchronized by the edge (1), is fed to the input of a clock pulse, of which a signal of an adjustable frequency is supplied, and a trigger with an asynchronous reset, synchronized by front (2), to the input of the clock pulse, to which a reference frequency signal is supplied, the trigger output (1) is connected to the first input of a logical element with a logical multiplication function (3), the trigger output (2) is connected to the second input of a logical element with a logical multiplication function ( 3), the output of the element (3) is connected to the inputs of the asynchronous reset signal of the triggers (1) and (2), the output of the trigger (1) is connected to the first input of the logical element with the logical multiplication function (6) and to the input of the delay element (5), the trigger output (2) is connected to the second input of the logical element with the logical multiplication function (7) and to the input of the delay element (4), the output of the delay element (4) is connected to the second inverse input of the logical element with the logical multiplication function (6), the output of the element delay (5) is connected to the first inverse input of the logical element with the logical multiplication function (7), the output of the logical element with the logical multiplication function (6) goes to the first control input of the charge-discharge unit (8), the output of the logical element with the logical multiplication function ( 7) is supplied to the second control input of the charge-discharge unit (8).

The technical result provided by the above set of features is to provide the ability to independently adjust the duration of the response time of the PFD control voltage pulses, regardless of the response time of the asynchronous trigger reset circuit. The duration of the PFD voltage control pulses is determined by the response time in the delay elements (4) and (5) and can be selected independently of each other, which ensures independent adjustment of the duration for each control pulse separately.

Circuit of a frequency-phase detector with a minimum duration of control pulses, characterized in that it consists of two triggers with asynchronous reset 1, 2, three logical elements with a logical multiplication function 3, 6, 7, two delay elements 4, 5, and on the first input trigger 1 receives a signal of an adjustable frequency, and the first input of trigger 2 receives a reference frequency signal, while the output of trigger 1 is connected to the first input of logic element 3 and to the first input of logic element bis input of delay element 5; the output of trigger 2 is connected to the second input of logic element 3 and to the second input of logic element 7 and to the input of delay element 4; the output of the delay element 4 is connected to the second inverse input of the logical element 6, and the output of the delay element 5 is connected to the first inverse input of the logical element 7; in this case, control voltage pulses are formed at the outputs of logic elements 6, 7.

Brief description of drawings

The essence of the invention is illustrated by drawings, which show:

In fig. 1 - block diagram of a phase-locked loop;

In fig. 2 - schematic diagram of a PFD with a minimum duration of control pulses;

In fig. 3 time-pulse diagram of PFD operation with a minimum duration of control pulses.

Carrying out the invention

The frequency-phase detector circuit generates two pulse control signals, which are supplied to the input of the charge-discharge unit. Each of the control pulses is responsible for increasing or decreasing the control voltage of the voltage controlled generator. The change in control voltage is proportional to the difference in the duration of the PFD control pulses. In the phase auto-frequency control loop synchronization mode, after the frequency locking process, adjustment of the control voltage is no longer required, so the duration of the two control pulses at the PFD output will be almost the same. The input of trigger 1 clock pulse receives a signal of an adjustable frequency, which causes the trigger state to switch to a state with a logical one. A similar state switching occurs in trigger 2 when a reference frequency signal arrives at its input. After logically high level signals are generated at the outputs of flip-flops 1 and 2, logic element 3 will switch to the logical zero state, which will trigger the asynchronous reset circuit in both flip-flops 1 and 2 and switch both to the logical zero state after some delay associated with propagation of the trigger reset signal. After the reset, when signals of the reference and adjusted frequencies arrive, the process of switching the states of the triggers is repeated. Signals from the output of triggers 1 and 2 are supplied to the inputs of elements 4 and 5, at the output of which copies of the trigger output signals are formed with a certain delay τ. In logic element 6, the process of logical multiplication of the output signal of trigger 1 and an inverse copy of the output signal of trigger 2 with a delay τ is carried out, and in logic element 7 the process of logical multiplication of the output signal of trigger 2 and an inverse copy of the output signal of trigger 1 is carried out with a delay τ. At the outputs of logic elements 6 and 7, control voltage pulses are generated, which are supplied to the input of the ZRB. In synchronism mode, the duration of the control pulses is the same and is equal to the delay time t and can be selected with a minimum duration.

Claims (1)

Frequency-phase detector circuit with a minimum duration of control pulses, characterized in that it consists of two triggers with asynchronous reset 1, 2, three logic elements with a logical multiplication function 3, 6, 7, two delay elements 4, 5, and on the first input trigger 1 receives a signal of an adjustable frequency, and the first input of trigger 2 receives a reference frequency signal, while the output of trigger 1 is connected to the first input of logic element 3, and to the first input of logic element 6, and to the input of delay element 5; the output of trigger 2 is connected to the second input of logic element 3, and to the second input of logic element 7, and to the input of delay element 4; the output of the delay element 4 is connected to the second inverse input of the logical element 6, and the output of the delay element 5 is connected to the first inverse input of the logical element 7; in this case, control voltage pulses are formed at the outputs of logic elements 6, 7.