JPH0629432A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0629432A
JPH0629432A JP18223992A JP18223992A JPH0629432A JP H0629432 A JPH0629432 A JP H0629432A JP 18223992 A JP18223992 A JP 18223992A JP 18223992 A JP18223992 A JP 18223992A JP H0629432 A JPH0629432 A JP H0629432A
Authority
JP
Japan
Prior art keywords
semiconductor device
fixed
semiconductor element
metal
metal cap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18223992A
Other languages
Japanese (ja)
Other versions
JP3013612B2 (en
Inventor
Takashi Kinoshita
高志 木下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4182239A priority Critical patent/JP3013612B2/en
Publication of JPH0629432A publication Critical patent/JPH0629432A/en
Application granted granted Critical
Publication of JP3013612B2 publication Critical patent/JP3013612B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To reduce thermal resistance by improving dissipation performance of a semiconductor device mounting a high-power driving semiconductor element, and to prevent deformation of an outer lead which is caused by a larger-size heat sink, and further to prevent it from becoming a larger-scale system in which the semiconductor device is mounted. CONSTITUTION:The surface forming the circuit of a semiconductor 1 is fixed on a Cu-W block 13 provided in the central part of a metal cap 6 through a polyimide film 11.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、高パワー駆動を必要と
する半導体装置に関し、特に、大型の放熱板を有する半
導体装置の構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which requires high power driving, and more particularly to the structure of a semiconductor device having a large heat sink.

【0002】[0002]

【従来の技術】従来、この種のヒートシンクを有する半
導体装置の構造は図3に示すように構成されていた。す
なわち、図3において1はシリコンより成る半導体素子
を示し、Au−Siろう材2によってセラミック基体3
に固着されており、半導体素子1とセラミック基体3は
Alワイヤ4によって電気的に接続されている。また、
6は金属キャップを示し、セラミック基体3に設けられ
た金属製シールリング5にシームウェルド法等によって
固着され、セラミック基体3を気密封止している。
2. Description of the Related Art Conventionally, the structure of a semiconductor device having this type of heat sink has been constructed as shown in FIG. That is, in FIG. 3, reference numeral 1 denotes a semiconductor element made of silicon.
The semiconductor element 1 and the ceramic substrate 3 are electrically connected by an Al wire 4. Also,
Reference numeral 6 denotes a metal cap, which is fixed to a metal seal ring 5 provided on the ceramic base 3 by a seam weld method or the like to hermetically seal the ceramic base 3.

【0003】また、7はセラミック基体3に設けられた
外部電極取出し用の外部リードを示す。さらに19はア
ルミニウム等から成る金属放熱板を示し、シリコーン系
樹脂8によってセラミック基体3に固着されている。
Reference numeral 7 denotes an external lead provided on the ceramic substrate 3 for taking out an external electrode. Reference numeral 19 denotes a metal heat dissipation plate made of aluminum or the like, which is fixed to the ceramic base 3 with a silicone resin 8.

【0004】この際、半導体装置を所定の実装基板に実
装後に、通電状態において半導体素子1で生じた熱はセ
ラミック基体3を介して放熱板19より放熱されてお
り、特に強制的に放熱板に風を当てることにより放熱効
果を上げている。
At this time, after the semiconductor device is mounted on a predetermined mounting board, the heat generated in the semiconductor element 1 in the energized state is dissipated from the heat dissipation plate 19 through the ceramic base body 3, and especially the heat dissipation plate is forcibly forced to the heat dissipation plate. The heat radiation effect is improved by applying wind.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上述し
た従来の放熱板を有する半導体装置は、以下のような欠
点を有していた。
However, the above-described semiconductor device having the conventional heat sink has the following drawbacks.

【0006】すなわち、近年、特に高性能ECLゲート
アレイ等の半導体素子を搭載する半導体装置において
は、電気的特性を高めるために、できる限りセラミック
基体3を小型化せざるを得ず、一方、高パワー駆動の必
要性より、放熱機能を最大限に高めるために、放熱板1
9は大型化せざるを得ない。この場合、放熱板19を固
着した後の半導体装置を取扱う包装工程や輸送工程で金
属放熱板19の重量で外部リード7が変形し易いという
欠点を有している。
That is, in recent years, particularly in a semiconductor device having a semiconductor element such as a high-performance ECL gate array mounted thereon, the ceramic substrate 3 has to be miniaturized as much as possible in order to improve the electrical characteristics, while at the same time, high In order to maximize the heat dissipation function from the necessity of power drive, the heat dissipation plate 1
The size of 9 is inevitable. In this case, there is a drawback that the external lead 7 is easily deformed by the weight of the metal heat dissipation plate 19 in a packaging process or a transportation process of handling the semiconductor device after the heat dissipation plate 19 is fixed.

【0007】また、消費電力が数十ワットを越える様な
高パワー駆動が必要な半導体素子を搭載した際に、放熱
板19の大きさは10cmを越えるような高さになって
しまい、これらの半導体装置を実装するコンピュータ等
のセットの実装基板間隔がおおきくなってしまい、それ
に伴い、システムの小型化の実現も困難であるという欠
点を有していた。
Further, when a semiconductor element which requires high power driving such that power consumption exceeds several tens of watts is mounted, the size of the heat dissipation plate 19 becomes higher than 10 cm. There has been a drawback in that the mounting board spacing of a set such as a computer in which a semiconductor device is mounted becomes large, and accordingly, it is difficult to realize the miniaturization of the system.

【0008】本発明は従来の上記実情に鑑みてなされた
ものであり、従って本発明の目的は、従来の技術に内在
する上記欠点を解消することを可能とした新規な半導体
装置を提供することにある。
The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to provide a novel semiconductor device capable of solving the above-mentioned drawbacks inherent in the conventional technique. It is in.

【0009】[0009]

【課題を解決するための手段】上記目的を達成する為
に、本発明に係る半導体装置は、半導体素子が搭載され
たセラミック基体に固着された放熱板を有し、かつ半導
体素子の回路形成面が絶縁フィルムを介して金属キャッ
プ内壁の突起部分に固着されている。これにより、半導
体装置の通電時に半導体素子で生じた熱は放熱板と金属
キャップの両方からの放熱が可能となる。
In order to achieve the above object, a semiconductor device according to the present invention has a heat dissipation plate fixed to a ceramic substrate on which a semiconductor element is mounted, and a circuit forming surface of the semiconductor element. Is fixed to the protruding portion on the inner wall of the metal cap via the insulating film. As a result, the heat generated in the semiconductor element when the semiconductor device is energized can be dissipated from both the heat dissipation plate and the metal cap.

【0010】[0010]

【実施例】次に本発明をその好ましい各実施例について
図面を参照して具体的に説明する。
BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be specifically described with reference to the drawings for each of its preferred embodiments.

【0011】図1は本発明による第1の実施例を示す断
面図である。
FIG. 1 is a sectional view showing a first embodiment according to the present invention.

【0012】図1において、参照番号1はシリコンより
成る半導体素子、2は半導体素子1がAu−Siろう材
2を介して固着されているセラミック基体、4は半導体
素子1とセラミック基体3を電気的に接続するAlワイ
ヤをそれぞれ示し、5はセラミック基体3に固着された
コバール等から成るシールリングであり、金属キャップ
6がシームウェルド法等によって固着されセラミック基
体3を気密封止している。7はセラミック基体3に固着
された外部電極取出し用の外部リード、9はアルミニウ
ム等から成る金属放熱板であり、熱伝導率が良好なシリ
コーン系樹脂8によってセラミック基体3に固着されて
いる。
In FIG. 1, reference numeral 1 is a semiconductor element made of silicon, 2 is a ceramic substrate to which the semiconductor element 1 is fixed via an Au-Si brazing material 2, and 4 is a semiconductor element 1 and a ceramic substrate 3. 5A and 5B respectively show the Al wires that are electrically connected to each other, and 5 is a seal ring made of Kovar or the like fixed to the ceramic base 3, and the metal cap 6 is fixed by the seam weld method or the like to hermetically seal the ceramic base 3. Reference numeral 7 is an external lead for taking out an external electrode fixed to the ceramic base 3, 9 is a metal heat dissipation plate made of aluminum or the like, and fixed to the ceramic base 3 by a silicone resin 8 having a good thermal conductivity.

【0013】11はポリイミドフィルムであり、このポ
リイミドフィルム11は半導体素子1の回路形成面上に
絶縁性シリコーン系樹脂10を介して固着されており、
半導体素子1と逆方向の面はシリコーン系樹脂12を介
して、金属キャップ6の中央部に組み込まれた熱伝導率
が良好なCu−Wブロック13に固着されている。
Reference numeral 11 is a polyimide film, and this polyimide film 11 is fixed on the circuit formation surface of the semiconductor element 1 through an insulating silicone resin 10.
The surface opposite to the semiconductor element 1 is fixed to a Cu-W block 13 having a good thermal conductivity incorporated in the central portion of the metal cap 6 with a silicone resin 12 interposed therebetween.

【0014】この構造であると、半導体装置の通電状態
において半導体素子1で発生する熱は、半導体素子1の
裏面からセラミック基体3を通して金属放熱板9より放
熱されると共に、半導体素子1の回路形成面側からも金
属キャップ6の中央に設けたCu−Wブロック13を通
して放熱される。
With this structure, the heat generated in the semiconductor element 1 in the energized state of the semiconductor device is radiated from the back surface of the semiconductor element 1 through the ceramic substrate 3 and the metal heat radiating plate 9, and the circuit of the semiconductor element 1 is formed. Heat is also radiated from the surface side through the Cu-W block 13 provided in the center of the metal cap 6.

【0015】このために、従来40mm□程度のセラミ
ック基体に高さ3cm程度のAl製放熱板を取付けた半
導体装置で熱抵抗(ΘJa)が5〜10°C/W(風速
3m/秒下)であったものが、本実施例の場合には、約
20〜30%程熱抵抗(ΘJa)が小さくなるという利
点を有している。
For this reason, in the conventional semiconductor device in which a heat dissipating plate made of Al and having a height of about 3 cm is attached to a ceramic substrate of about 40 mm □, the thermal resistance (ΘJa) is 5 to 10 ° C / W (wind speed is 3 m / sec. Or lower). However, in the case of the present embodiment, there is an advantage that the thermal resistance (ΘJa) is reduced by about 20 to 30%.

【0016】これに基づき、高パワー駆動の半導体素子
を搭載する場合でも金属放熱板9を大型にする必要がな
くなるために、半導体装置の包装工程や輸送工程で金属
放熱板9の重量で外部リード7が変形することを防止で
きるという利点を有している。
Based on this, it is not necessary to increase the size of the metal heat sink 9 even when a high power driven semiconductor element is mounted. Therefore, the weight of the metal heat sink 9 causes the external lead in the packaging process and the transportation process of the semiconductor device. 7 has the advantage that it can be prevented from deforming.

【0017】さらに、半導体装置を実装するコンピュー
タ等の基板同志の間隔を狭くできるという利点も有して
いる。
Further, there is an advantage that the distance between the substrates of a computer or the like on which the semiconductor device is mounted can be narrowed.

【0018】図2は本発明による第2の実施例を示す断
面図である。
FIG. 2 is a sectional view showing a second embodiment according to the present invention.

【0019】図2を参照するに、本発明による第2の実
施例は、金属キャップ6の中央部に設けられたCu−W
ブロック13とセラミック基体3上に設けられた金属放
熱板9とが、シリコーン系樹脂14、15を介して固着
された金属片16で連結された構造となっている。
Referring to FIG. 2, the second embodiment according to the present invention is a Cu-W provided at the center of the metal cap 6.
The block 13 and the metal radiating plate 9 provided on the ceramic base 3 are connected by a metal piece 16 fixed via silicone resins 14 and 15.

【0020】この金属片16は、セラミック基体3に固
着されている外部リード(図示せず)の空部分を利用し
て設けることが可能であり、例えば、外部リードが2方
向のみに固着されているSOPと呼ばれるセラミック基
体の場合には外部リードの無い側面を利用して金属片1
6を配置させればよい。
The metal piece 16 can be provided by utilizing an empty portion of an external lead (not shown) fixed to the ceramic base 3. For example, the external lead is fixed only in two directions. In the case of a ceramic substrate called SOP, the metal piece 1
6 may be arranged.

【0021】また、4方向に外部リードが固着されてい
るQFPと呼ばれるセラミック基体の場合には、セラミ
ック基体3のコーナ部分や、電気的にノンコネクトピン
である外部リードが無い部分を利用して金属片16を配
置させればよい。
Further, in the case of a ceramic substrate called QFP in which external leads are fixed in four directions, the corner portion of the ceramic substrate 3 or a portion having no external lead which is an electrically non-connect pin is used. The metal piece 16 may be arranged.

【0022】本構造であると、半導体素子1で発生した
熱はCu−Wブロック13からさらに金属片16を通し
て金属放熱板9から放熱されるために、半導体装置の熱
抵抗がさらに下がるという利点を有しており、特に強制
空冷を実施した場合に効果が大きい。
According to this structure, the heat generated in the semiconductor element 1 is radiated from the Cu-W block 13 and the metal radiating plate 9 through the metal piece 16, so that the thermal resistance of the semiconductor device is further reduced. It has a great effect, especially when forced air cooling is carried out.

【0023】[0023]

【発明の効果】以上説明したように、本発明によれば、
半導体素子の回路形成面がポリイミドフィルムを介して
金属キャップ内壁の突起部分に固着されているために、
半導体素子で動作時に発生した熱が、回路形成面側から
も半導体装置外部に放熱されるので、従来構造の半導体
素子裏面からのみセラミツク基体を通して金属放熱板か
ら放熱していた場合と比べ、約20〜30%熱抵抗(Θ
Ja)が小さくなるという効果が得れらる。これに伴
い、従来と比べ金属放熱板を小型にできるという効果も
得られる。
As described above, according to the present invention,
Since the circuit forming surface of the semiconductor element is fixed to the protruding portion of the inner wall of the metal cap through the polyimide film,
The heat generated during operation of the semiconductor element is also radiated to the outside of the semiconductor device from the circuit formation surface side. Therefore, compared to the case where heat is radiated from the metal heat sink through the ceramic substrate only from the back surface of the semiconductor element of the conventional structure, about 20 ~ 30% heat resistance (Θ
The effect that Ja) becomes small can be obtained. Along with this, it is possible to obtain an effect that the metal radiator plate can be made smaller than the conventional one.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による第1の実施例を示す断面図であ
る。
FIG. 1 is a sectional view showing a first embodiment according to the present invention.

【図2】本発明による第2の実施例を示す断面図であ
る。
FIG. 2 is a sectional view showing a second embodiment according to the present invention.

【図3】従来の半導体装置を示す断面図である。FIG. 3 is a cross-sectional view showing a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1…半導体素子 2…Au−Siろう材 3…セラミック基体 4…Alワイヤ 5…シールリング 6…金属キャップ 7…外部リード 8…シリコーン系樹脂 9…金属放熱板 10…シリコーン系樹脂 11…ポリイミドフィルム 12…シリコーン系樹脂 13…Cu−Wブロック 14…シリコーン系樹脂 15…シリコーン系樹脂 16…金属片 DESCRIPTION OF SYMBOLS 1 ... Semiconductor element 2 ... Au-Si brazing material 3 ... Ceramic base 4 ... Al wire 5 ... Seal ring 6 ... Metal cap 7 ... External lead 8 ... Silicone resin 9 ... Metal heat sink 10 ... Silicone resin 11 ... Polyimide film 12 ... Silicone type resin 13 ... Cu-W block 14 ... Silicone type resin 15 ... Silicone type resin 16 ... Metal piece

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 セラミック基体に半導体素子が固着さ
れ、金属キャップによって前記セラミック基体が気密封
止されて成る半導体装置において、前記セラミック基体
に放熱板が固着され、かつ前記半導体素子の回路形成面
上に絶縁フィルムを介して前記金属キャップの内壁に設
けられた突起部分が固着されていることを特徴とする半
導体装置。
1. A semiconductor device in which a semiconductor element is fixed to a ceramic base and the ceramic base is hermetically sealed by a metal cap, and a heat dissipation plate is fixed to the ceramic base and a circuit forming surface of the semiconductor element is provided. A semiconductor device characterized in that a protrusion provided on the inner wall of the metal cap is fixed to the inner wall of the metal cap via an insulating film.
【請求項2】 前記金属キャップの内壁に設けられた前
記突起部分は、前記金属キャップの主基板中央部に固着
された熱伝導率が良好な金属のブロックより成ることを
更に特徴とする請求項1に記載の半導体装置。
2. The method according to claim 2, wherein the protruding portion provided on the inner wall of the metal cap is made of a metal block having a good thermal conductivity, which is fixed to the central portion of the main substrate of the metal cap. 1. The semiconductor device according to 1.
【請求項3】 前記セラミック基体に固着された放熱板
と前記金属キャップは、金属片によって連結されている
ことを更に特徴とする請求項1に記載の半導体装置。
3. The semiconductor device according to claim 1, further comprising: a metal plate connecting the heat dissipation plate fixed to the ceramic base and the metal cap.
JP4182239A 1992-07-09 1992-07-09 Semiconductor device Expired - Lifetime JP3013612B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4182239A JP3013612B2 (en) 1992-07-09 1992-07-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4182239A JP3013612B2 (en) 1992-07-09 1992-07-09 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0629432A true JPH0629432A (en) 1994-02-04
JP3013612B2 JP3013612B2 (en) 2000-02-28

Family

ID=16114782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4182239A Expired - Lifetime JP3013612B2 (en) 1992-07-09 1992-07-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3013612B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5552635A (en) * 1994-01-11 1996-09-03 Samsung Electronics Co., Ltd. High thermal emissive semiconductor device package
KR19980035920A (en) * 1996-11-15 1998-08-05 구자홍 SOP Type Semiconductor Package

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61171153A (en) * 1985-01-25 1986-08-01 Fujitsu Ltd Semiconductor device
JPS61290742A (en) * 1985-06-19 1986-12-20 Hitachi Ltd Semiconductor device
JPS63186453A (en) * 1987-01-29 1988-08-02 Nec Corp Lsi

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61171153A (en) * 1985-01-25 1986-08-01 Fujitsu Ltd Semiconductor device
JPS61290742A (en) * 1985-06-19 1986-12-20 Hitachi Ltd Semiconductor device
JPS63186453A (en) * 1987-01-29 1988-08-02 Nec Corp Lsi

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5552635A (en) * 1994-01-11 1996-09-03 Samsung Electronics Co., Ltd. High thermal emissive semiconductor device package
KR19980035920A (en) * 1996-11-15 1998-08-05 구자홍 SOP Type Semiconductor Package

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