JPH0629340A - Die for forming resin-sealed semiconductor device and resin-seal of semiconductor chip used therefor - Google Patents

Die for forming resin-sealed semiconductor device and resin-seal of semiconductor chip used therefor

Info

Publication number
JPH0629340A
JPH0629340A JP4184854A JP18485492A JPH0629340A JP H0629340 A JPH0629340 A JP H0629340A JP 4184854 A JP4184854 A JP 4184854A JP 18485492 A JP18485492 A JP 18485492A JP H0629340 A JPH0629340 A JP H0629340A
Authority
JP
Japan
Prior art keywords
resin
die
semiconductor chip
chip
movable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4184854A
Other languages
Japanese (ja)
Inventor
Toru Kihira
徹 紀平
Hiroyuki Fukazawa
博之 深澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP4184854A priority Critical patent/JPH0629340A/en
Publication of JPH0629340A publication Critical patent/JPH0629340A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PURPOSE:To provide a forming die which prevents the occurrence of voids or non-fillings in a package sealed in resin, and a forming method which employs the die. CONSTITUTION:A forming die M is made up of an upper die 5 and a lower die 6, and the ends of a number of movable pins 9 are flatly formed so as to be flush with inner surfaces 5a and 6a of cavities 5A and 6A of the upper and lower dies. These pins are respectively disposed on the upper and lower dies in such a way as to be vertically movable relative to the inner surface. While an IC chip 1 mounted on a leadframe is fastened at a predetermined location within the cavities 5A and 6A by means of the die M, the movement of the IC chip 1 is regulated by drawing each movable pin 9. In this state, the cavity of the die is filled with molten sealing resin. By the end of the filling, the movable pins 9 are retracted to the position where the flat ends of the pins become flush with the inner surfaces 5a and 6a of the cavities 5A and 6A, and sealing resin is then made set.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は半導体チップをトラン
スファーモールド法により樹脂で封止する樹脂封止型半
導体装置(以下、単に「IC」と記す)用成形金型(以
下、単に「成形金型」と記す)及びこの成形金型を用い
て半導体チップを樹脂封止する樹脂封止方法に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a molding die for a resin-sealed semiconductor device (hereinafter simply referred to as "IC") for sealing a semiconductor chip with a resin by a transfer molding method (hereinafter simply referred to as "molding die"). ]) And a resin encapsulation method for encapsulating a semiconductor chip with a resin using this molding die.

【0002】[0002]

【従来の技術】従来技術の成形金型を図6乃至図8を用
いて説明する。従来の成形金型は、通常、図6の縦断面
図に示したように、上金型5と下金型6とから構成され
ている。この成形金型は2つの上下金型5、6の間に挟
まれて設置されたICチップ1を所定形状の樹脂モール
ドICとして封止するための中空部であるキャビティ5
A、6Aと、樹脂の通路となるランナー部7から各キャ
ビティ5A、6Aへの注入口となるゲート部8とから構
成されている。
2. Description of the Related Art A conventional molding die will be described with reference to FIGS. A conventional molding die is usually composed of an upper die 5 and a lower die 6, as shown in the longitudinal sectional view of FIG. This molding die is a cavity 5 which is a hollow portion for sealing the IC chip 1 sandwiched between two upper and lower dies 5 and 6 as a resin-molded IC having a predetermined shape.
A and 6A, and a gate portion 8 serving as an injection port from the runner portion 7 serving as a resin passage to each cavity 5A, 6A.

【0003】このような成形金型は、樹脂成形時、溶融
した封止樹脂がキャビティ5A、6Aの一側方から注入
されるため、ICチップ及びそれが搭載されるダイパッ
ド2が注入樹脂の圧力で設計上の位置から上下に動いた
り傾くことがある。
In such a molding die, since the molten sealing resin is injected from one side of the cavities 5A and 6A during resin molding, the pressure of the injected resin is applied to the IC chip and the die pad 2 on which the IC chip is mounted. It may move up and down or tilt from its designed position.

【0004】特に近年、ICチップ1の集積度が増大
し、ICチップ1の面積も増大して、従って、前記ダイ
パッド2も従来より大きくなってきている。その一方
で、パッケージのピン数は増えつつあり、外部リード間
ピッチも狭くなり、それに伴い、内部リードやダイパッ
ド2を吊っているサポートバーの幅も細く、かつ長くな
ってきている。このような構造になると、小さな樹脂圧
力でもICチップ1およびダイパッド2が、前記のよう
に上下動したり、傾いたりする。
Particularly in recent years, the degree of integration of the IC chip 1 has increased and the area of the IC chip 1 has also increased, so that the die pad 2 has become larger than before. On the other hand, the number of pins in the package is increasing, the pitch between the external leads is narrowing, and along with this, the width of the support bar that suspends the internal leads and the die pad 2 is becoming narrower and longer. With such a structure, the IC chip 1 and the die pad 2 move up and down or tilt as described above even with a small resin pressure.

【0005】また更に、近年、薄型化を目的として開発
が進められているフローティングチップ構造のICで
は、リードフレームにダイパッド2が存在しないため
に、このチップの上下動や傾きが、ダイパッド2を有す
るものと比較して、より頻繁に発生する。
Furthermore, in an IC having a floating chip structure, which is being developed for the purpose of thinning in recent years, since the die pad 2 does not exist in the lead frame, the vertical movement or inclination of this chip has the die pad 2. It happens more often than anything.

【0006】このようなICチップ1およびそのダイパ
ッド2の上下動および傾きが激しい場合には、 1.ICチップ1の上、またはそのダイパッド2の下
(フローティングチップ構造の場合はICチップ1の
下)の、封止樹脂が封入される空間が狭くなるために溶
融樹脂の流動性が悪くなり、その注入した溶融樹脂の表
面に未充填やボイドが発生する 2.ICの縦断面構造のバランスがくずれ、内部構成材
料間の熱膨張係数の違いによってICパッケージに反り
を発生させる
When the IC chip 1 and its die pad 2 are vertically moved and tilted significantly, 1. Since the space in which the sealing resin is filled is narrowed above the IC chip 1 or below the die pad 2 (below the IC chip 1 in the case of a floating chip structure), the fluidity of the molten resin deteriorates. 1. Unfilled or voids are generated on the surface of the injected molten resin. The longitudinal sectional structure of the IC is unbalanced, and the IC package is warped due to the difference in the coefficient of thermal expansion between the internal constituent materials.

【0007】また更に、特に半導体チップ1が上方に上
がった場合、 3.ICチップ1とリードフレームとの間をボンディン
グしているワイヤ3が封止樹脂の表面に露出する 4.ICチップ1上のボンディング点の位置が上昇する
と、ワイヤ3が倒れて、ICチップ1のエッジ部に触
れ、ショート不良を起こす 5.ワイヤ3が引っ張られて断線する など、不具合の原因になる。
Furthermore, especially when the semiconductor chip 1 is raised upward, 3. The wire 3 bonding between the IC chip 1 and the lead frame is exposed on the surface of the sealing resin. 4. When the position of the bonding point on the IC chip 1 rises, the wire 3 falls down and touches the edge portion of the IC chip 1, causing a short circuit defect. This may cause trouble such as the wire 3 being pulled and breaking.

【0008】[0008]

【発明が解決しようとする課題】このような致命的な不
良を引き起こすICチップ1の上下動を抑えるため、特
開平4−7848に開示された事例では、フローティン
グチップ構造のIC用の樹脂封止金型において、上金型
及び下金型でICチップを挟んで固定するための突起物
を設けているが、この封止方法では図7に示したよう
に、ICパッケージ10の表面上に突起物の痕跡11が
残り、場合によっては、ICチップの表面までの樹脂の
厚さが薄くなったり、更にはICチップ表面が露出する
ようなことになる。
In order to suppress the vertical movement of the IC chip 1 which causes such a fatal defect, in the case disclosed in JP-A-4-7848, resin encapsulation for an IC of a floating chip structure is adopted. In the mold, protrusions are provided for sandwiching and fixing the IC chip between the upper mold and the lower mold. In this sealing method, as shown in FIG. 7, the protrusion is formed on the surface of the IC package 10. The traces of the object 11 remain, and depending on the case, the thickness of the resin to the surface of the IC chip becomes thin, or the surface of the IC chip is exposed.

【0009】これらの現象は外観的な問題になるほか、
ICパッケージ10の機械的強度の低下、これらの部分
からの水分などの浸入によるICの信頼性の低下を招く
ことがある。また更に、前記痕跡部分から入射した外部
からの光、または薄くなった樹脂を透過してきた光の影
響で、ICの電気的特性、例えばメモリの場合、データ
保持電圧などの特性に悪影響を及ぼすことになる。
In addition to these appearance problems,
The mechanical strength of the IC package 10 may be reduced, and the reliability of the IC may be reduced due to the intrusion of moisture or the like from these portions. Furthermore, the influence of the light from the outside incident from the trace portion or the light transmitted through the thinned resin may adversely affect the electrical characteristics of the IC, such as the data holding voltage in the case of a memory. become.

【0010】また、特開平3−9538に開示された実
施例でも、前記の例と同様に樹脂封止用金型に、ICチ
ップを搭載するダイパッドを挟んで固定するための可動
式の円錐状ピンを設け、注入した樹脂が硬化し、離型す
るときに、これらの可動ピンを主型面下にまで引き込め
るとしているが、図8に示したように、この場合にもI
Cパッケージ10の表面にこれらの可動ピンの痕跡が残
って、前記の実施例で説明したような不具合が起こり、
またこれらのピンの痕跡が残らないように樹脂封止中に
可動ピンを引き込めるタイミングなどを調整しても、可
動ピンの形状が円錐状であるため、主型面上の可動ピン
の収納部に樹脂が流れ込んで、図示のようにICパッケ
ージ10の表面にバリ12が残ることになる。
Also in the embodiment disclosed in Japanese Patent Laid-Open No. 3-9538, a movable conical shape for sandwiching and fixing a die pad for mounting an IC chip in a resin sealing mold as in the above-mentioned example. It is stated that when the pins are provided and the injected resin hardens and is released from the mold, these movable pins can be retracted to below the surface of the main mold, but as shown in FIG.
Traces of these movable pins remain on the surface of the C package 10, causing the problems described in the above-mentioned embodiment,
Even if the timing of retracting the movable pin during resin sealing is adjusted so that the traces of these pins do not remain, the shape of the movable pin is conical, so the movable pin storage part on the main mold surface The resin flows into the surface, leaving burrs 12 on the surface of the IC package 10 as shown.

【0011】[0011]

【課題を解決するための手段】この発明は、上下金型で
構成された樹脂封止型半導体装置の成形金型において、
これら上下金型に形成し、封止樹脂が注入される内面が
平面なキャビティのそれぞれの主型面において、半導体
チップ及び又はダイパッドの移動を規制する複数の可動
ピンが設けられ、これらの可動ピンの前記半導体チップ
及び又は前記ダイパッドに近接する先端部が、これら可
動ピンが後退した状態の時に、前記キャビティの内面と
同一の平面を構成するように平面に形成した。
The present invention provides a molding die for a resin-sealed semiconductor device composed of upper and lower dies,
A plurality of movable pins for restricting the movement of the semiconductor chip and / or the die pad are provided on each main mold surface of the cavity formed in these upper and lower molds and having a flat inner surface into which the sealing resin is injected. The front end portion of the semiconductor chip and / or the die pad is formed in a flat surface so as to form the same plane as the inner surface of the cavity when the movable pins are retracted.

【0012】そして、そのような成形金型を用い、その
成形金型のキャビティの所定の位置に半導体チップを搭
載したリードフレームを配置し、前記上下金型を締結
し、そして前記上下金型に設けた各可動ピンを前記半導
体チップの方に可動、近接させて、前記半導体チップの
移動を規制するようにした状態で、溶融した封止樹脂を
前記成形金型に注入し、この封止樹脂が前記半導体チッ
プを殆ど覆い尽くした、或いは全て覆い尽くした状態の
時に、前記各可動ピンを、それらの先端部の前記平面が
前記上下金型の内面の平面と同一の面を構成する位置ま
で引き戻し、前記封止樹脂が前記各可動ピンが存在した
位置の空間部を埋め尽くして硬化した後、前記上下金型
を開き、樹脂封止された前記半導体チップを離型して樹
脂封止型半導体装置を得るようにして、前記課題を解決
するようにした。
Then, using such a molding die, a lead frame on which a semiconductor chip is mounted is arranged at a predetermined position of a cavity of the molding die, the upper and lower dies are fastened, and the upper and lower dies are attached to each other. Each movable pin provided is moved and brought close to the semiconductor chip to regulate the movement of the semiconductor chip, and a molten sealing resin is injected into the molding die, and the sealing resin is injected. When the semiconductor chip is almost completely covered, or when the semiconductor chips are completely covered, the movable pins are moved to a position where the flat surfaces of the tips of the movable pins form the same surface as the inner surface of the upper and lower molds. After pulling back, the sealing resin fills the space where the movable pins were present and is cured, then the upper and lower molds are opened and the resin-sealed semiconductor chip is released to form a resin-sealed mold. Semiconductor device Obtained manner and so as to solve the above problems.

【0013】[0013]

【作用】従って、成形金型のキャビティ内に存在するI
Cチップが、前記成形金型に注入された溶融した封止樹
脂の流れに速度差があって、前記ICチップが上下いず
れかの方に移動させられようとしても、前記複数の可動
ピンでその動きが規制されることになる。そして、封止
樹脂が硬化する前に前記構造の可動ピンを前記各キャビ
ティ内面と同一面に引き戻すので、硬化した封止樹脂に
は、可動ピンの極めて僅かな痕跡は残るが、従来技術に
見られたようなバリなどが発生することがない。
Therefore, I existing in the cavity of the molding die is
Even if the C chip has a speed difference in the flow of the molten sealing resin injected into the molding die and the IC chip is to be moved to either the upper or lower direction, Movement will be restricted. Since the movable pin of the above structure is pulled back to the same surface as the inner surfaces of the cavities before the sealing resin is cured, the cured pin has a very slight trace of the movable pin. There will be no burr like the one mentioned above.

【0014】[0014]

【実施例】以下、この発明の樹脂封止型半導体装置用成
形金型の実施例を図1乃至図5を用いて説明する。図1
はこの発明の実施例である樹脂封止型半導体装置用成形
金型及びその成形金型でICチップを搭載したリードフ
レームを挟んだ状態を示した断面図であって、同図Aは
ダイパッドを有するリードフレームを示したものであ
り、同図Bはダイパッドがないリードフレームを示した
ものであり、図2は図1に示した状態で、この発明の成
形金型に溶融した封止樹脂を注入しているICの製造過
程を示した断面図であり、図3は図2に示した製造過程
から次の製造過程を示した断面図であり、図4は図3に
示した製造過程から次の製造過程を示した断面図であ
り、そして図5は図4に示した製造過程から、必要に応
じて用いて効果的な製造過程を示した断面図である。な
お、図6乃至図8に示した従来技術と同一の構成部分に
は同一の符号を付し、それらの詳細な説明を省略する。
Embodiments of the resin-molded semiconductor device molding die of the present invention will be described below with reference to FIGS. Figure 1
FIG. 1A is a cross-sectional view showing a molding die for a resin-encapsulated semiconductor device according to an embodiment of the present invention and a state in which a lead frame having an IC chip mounted thereon is sandwiched by the molding die. FIG. FIG. 2B shows a lead frame having the same, FIG. 2B shows a lead frame without a die pad, and FIG. 2 shows the sealing resin melted in the molding die of the present invention in the state shown in FIG. FIG. 4 is a cross-sectional view showing a manufacturing process of the injected IC, FIG. 3 is a cross-sectional view showing a next manufacturing process from the manufacturing process shown in FIG. 2, and FIG. 4 is a manufacturing process shown in FIG. 5 is a cross-sectional view showing the next manufacturing process, and FIG. 5 is a cross-sectional view showing an effective manufacturing process using the manufacturing process shown in FIG. 4 as needed. The same components as those of the conventional technique shown in FIGS. 6 to 8 are designated by the same reference numerals, and detailed description thereof will be omitted.

【0015】先ず、図1を用いてこの発明の成形金型及
びICチップを搭載したリードフレームを説明する。I
Cチップ1は、ダイパッド2とこの周縁部に形成された
複数のインナーリード4とその他の構成要素から構成さ
れた通常のリードフレームの、前記ダイパッド2に銀ペ
ースト等で接着、固定されて搭載されており、その前記
インナーリード4の内端部に前記ICチップ1に形成さ
れている複数の電極をワイヤ3で接続されている。
First, a lead frame on which the molding die and the IC chip of the present invention are mounted will be described with reference to FIG. I
The C chip 1 is mounted on the die pad 2 of a normal lead frame composed of the die pad 2, a plurality of inner leads 4 formed on the periphery of the die pad 2, and other components by being bonded and fixed with silver paste or the like. A plurality of electrodes formed on the IC chip 1 are connected to the inner ends of the inner leads 4 by wires 3.

【0016】一方、図1に示した成形金型Mは、上金型
5と下金型6とから構成されていて、両者の相対する面
に、それぞれの内面5a、6aが平面なキャビティ5
A、6Aが形成されている。この構造は従来技術の成形
金型と同様である。この発明では、前記ICチップ1が
存在する上下金型5、6の主型面で前記複数の電極を避
けた部分に、前記ICチップ1に垂直状態でそのICチ
ップ1の方に可動する複数の可動ピン9を上金型5及び
下金型6に設けた。
On the other hand, the molding die M shown in FIG. 1 is composed of an upper die 5 and a lower die 6, and cavities 5 whose inner surfaces 5a, 6a are flat on the opposing surfaces of both.
A and 6A are formed. This structure is similar to the molding die of the prior art. According to the present invention, a plurality of movable upper and lower molds 5 and 6 in which the IC chip 1 is present, which are movable toward the IC chip 1 in a state perpendicular to the IC chip 1, in a portion of the main mold surface avoiding the plurality of electrodes. The movable pin 9 was provided on the upper mold 5 and the lower mold 6.

【0017】これらの可動ピン9の形状は、特開平3−
9538の実施例のように円錐状にするのではなく、ピ
ンを引き込めた時に上下金型5、6の主型面5a、6a
と連続になるように円柱状もしくは角柱状とする。そし
て、前記ICチップ1、または前記ダイパッド2の裏面
に近接するそれらの先端部は、これら可動ピン9が後退
した状態の時に、前記キャビティ5A、6Aの内面5
a、6aと同一の平面を構成するように平面状に形成す
る(図3及び図4)。
The shapes of these movable pins 9 are described in JP-A-3-
Rather than having the conical shape as in the 9538 embodiment, the main mold surfaces 5a, 6a of the upper and lower molds 5, 6 are drawn when the pins are retracted.
Columnar or prismatic so that it is continuous. The tip portions of the IC chip 1 and the die pad 2 which are close to the back surface of the die pad 2 have inner surfaces 5 of the cavities 5A and 6A when the movable pins 9 are retracted.
It is formed in a flat shape so as to form the same plane as a and 6a (FIGS. 3 and 4).

【0018】次に、このような構成の上下金型5、6を
用いてICチップ1を樹脂封止する方法を説明する。先
ず、図1に示したように、下金型6のキャビティ6Aの
中央部にダイパッド2に搭載されたICチップ1が位置
するようにリードフレームを下金型6の上に載置し、上
金型5も同様にして下金型6の上に重ね、各上下金型
5、6の縁で複数のインナーリード4などを挟み、固定
する。
Next, a method of resin-sealing the IC chip 1 using the upper and lower molds 5 and 6 having such a configuration will be described. First, as shown in FIG. 1, the lead frame is placed on the lower mold 6 so that the IC chip 1 mounted on the die pad 2 is located at the center of the cavity 6A of the lower mold 6, Similarly, the metal mold 5 is overlaid on the lower metal mold 6, and a plurality of inner leads 4 and the like are sandwiched between the edges of the upper and lower metal molds 5, 6 and fixed.

【0019】そして、その下金型6の方から複数の可動
ピン9を上げ、また上金型5の方から複数の可動ピン9
を下ろして、前者はダイパッド2の裏面に、後者はIC
チップ1の表面に、それぞれ極めて僅かな隙間を開けて
近接させ、ICチップ1が殆ど所定の位置で保持され、
好ましくない移動を規制するように調整する。
The lower die 6 raises the plurality of movable pins 9 and the upper die 5 raises the plurality of movable pins 9.
The former to the back of the die pad 2 and the latter to the IC.
The IC chip 1 is held almost at a predetermined position on the surface of the chip 1 with a very small gap between them to bring them close to each other.
Adjust to regulate undesired movement.

【0020】図1Bに示したように、ダイパッドレスの
リードフレームを用いた樹脂封止型半導体装置の場合に
は、前記下金型6に設けた可動ピン9を上げた場合、前
記のようにこれらの可動ピン9もICチップ1の裏面に
直接近接させる。
As shown in FIG. 1B, in the case of a resin-sealed semiconductor device using a die padless lead frame, when the movable pin 9 provided on the lower mold 6 is raised, as described above. These movable pins 9 are also brought close to the back surface of the IC chip 1 directly.

【0021】このようにして、可動ピン9を各キャビテ
ィ5A、6Aの主型面より突出させることによって、I
Cチップ1及び又はそのダイパッド2の上下方向の動き
が規制されることになる。
In this way, by projecting the movable pin 9 from the main mold surface of each cavity 5A, 6A, I
The vertical movement of the C chip 1 and / or its die pad 2 is restricted.

【0022】次に、図3に示したように、溶融した封止
樹脂10をランナー部7及びゲ−ト部8を通じて両キャ
ビティ5A、6A内に注入する。この図に示したよう
に、溶融した封止樹脂10がICチップ1をほぼ覆うま
では各可動ピン9を突出した状態にしておき、上下をほ
ぼ覆った時点で可動ピン9を引き戻していく。
Next, as shown in FIG. 3, the molten sealing resin 10 is injected into the cavities 5A and 6A through the runner portion 7 and the gate portion 8. As shown in this figure, each movable pin 9 is kept in a protruding state until the molten sealing resin 10 almost covers the IC chip 1, and when the upper and lower sides are almost covered, the movable pin 9 is pulled back.

【0023】そして溶融した封止樹脂10を成形金型M
のキャビティ5A、6Aに流し切ったときの様子を示し
たのが図4である。この時点では既に、全ての可動ピン
9の先端部の面はキャビティ5A、6Aの内面5a、6
aの一部である主型面と同一の平面を形成するまで戻さ
れており、封止樹脂10が硬化して時に、それがICパ
ッケージとなる、その表面に可動ピン9の痕跡が殆ど残
らないようにしている。
Then, the molten sealing resin 10 is molded into a molding die M.
FIG. 4 shows a state in which the cavities 5A and 6A are completely drained. At this point, the surfaces of the tips of all the movable pins 9 have already been formed on the inner surfaces 5a, 6 of the cavities 5A, 6A.
It is returned until it forms the same plane as the main mold surface that is a part of a, and when the sealing resin 10 hardens, it becomes an IC package. Almost traces of the movable pin 9 remain on the surface. I try not to.

【0024】また、各可動ピン9を引き戻すタイミング
や速さは、パッケ−ジ(硬化した封止樹脂10)の表面
に未充填やボイドが発生しないように調整することが肝
要である。従って、封止樹脂10が流動状態にあり、そ
して図2に示したような封止樹脂10が殆どICチップ
1を覆い終わる時に、各可動ピン9を引き戻すとよい。
Further, it is important to adjust the timing and speed at which each movable pin 9 is pulled back so that no unfilling or voids occur on the surface of the package (cured sealing resin 10). Therefore, each movable pin 9 may be pulled back when the sealing resin 10 is in a fluid state and the sealing resin 10 as shown in FIG. 2 almost completely covers the IC chip 1.

【0025】封止樹脂10を注入しその樹脂が充分に硬
化した後に、図4に示したように、上下金型5、6を離
して、ICを成形金型Mから離型させる。このとき可動
ピン9は引き込ませた状態のままでICを充分離型でき
るが、離型しにくい時には、図5に示したように、一部
あるいは全ての可動ピン9を再び可動、突出させて、I
Cを離型させるようにすることもできる。
After the sealing resin 10 is injected and the resin is sufficiently hardened, the upper and lower molds 5 and 6 are separated to release the IC from the molding mold M as shown in FIG. At this time, the IC can be charged and separated while the movable pin 9 is in the retracted state. However, when it is difficult to release the IC, some or all of the movable pins 9 can be moved and projected again as shown in FIG. , I
It is also possible to release C.

【0026】[0026]

【発明の効果】1.以上、説明したように、この発明の
成形金型及び製造方法によれば、樹脂からなるパッケー
ジ内部でのICチップの位置制御が可能となった。これ
によって、 1)パッケージ表面上の未充填・ボイドの発生 2)パッケージの反り 3)パッケージ表面へのボンディングワイヤの露出 4)ショート不良(ボンディングワイヤがチップのエッ
ジ部に触れる) 5)ボンディングワイヤの断線 などの不具合を低減することができた。また、
Effect of the Invention As described above, according to the molding die and the manufacturing method of the present invention, it is possible to control the position of the IC chip inside the resin package. As a result, 1) unfilling and void formation on the package surface 2) package warpage 3) exposure of bonding wire on the package surface 4) short circuit failure (bonding wire touches edge of chip) 5) bonding wire We were able to reduce problems such as disconnection. Also,

【0027】2.ICチップの位置制御がパッケージの
樹脂部に孔を付けることなく行えるようになった。これ
によって、 1)パッケージの外観上の問題がなくなる 2)パッケージの機械的強度の低下を防止することがで
きる 3)水分などの浸入の抑制によって、ICの信頼性の向
上が図れる 4)外部からの光の入射がなくなり、ICの電気的特性
に影響がなくなる などの効果が得られた。
2. The position of the IC chip can be controlled without making holes in the resin portion of the package. As a result, 1) there is no problem in the appearance of the package. 2) It is possible to prevent the mechanical strength of the package from being reduced. 3) By suppressing the ingress of moisture etc., the reliability of the IC can be improved. 4) From the outside The effect of eliminating the incidence of light and eliminating the influence on the electrical characteristics of the IC was obtained.

【0028】[0028]

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の実施例である樹脂封止型半導体装置
用成形金型及びその成形金型でICチップを搭載したリ
ードフレームを挟んだ状態を示した断面図であって、同
図Aはダイパッドを有するリードフレームを示したもの
であり、同図Bはダイパッドがないリードフレームを示
したものである。
FIG. 1 is a cross-sectional view showing a molding die for a resin-encapsulated semiconductor device according to an embodiment of the present invention and a state in which a lead frame having an IC chip mounted therein is sandwiched by the molding die. Shows a lead frame having a die pad, and FIG. 6B shows a lead frame having no die pad.

【図2】図1に示した状態で、この発明の成形金型に溶
融した封止樹脂を注入しているICの製造過程を示した
断面図である。
FIG. 2 is a cross-sectional view showing a manufacturing process of an IC in which molten sealing resin is injected into the molding die of the present invention in the state shown in FIG.

【図3】図2に示した製造過程から次の製造過程を示し
た断面図である。
3 is a cross-sectional view showing the next manufacturing process from the manufacturing process shown in FIG.

【図4】図3に示した製造過程から次の製造過程を示し
た断面図である。
FIG. 4 is a cross-sectional view showing a next manufacturing process from the manufacturing process shown in FIG.

【図5】図4に示した製造過程から、必要に応じて用い
て効果的な製造過程を示した断面図である。
FIG. 5 is a cross-sectional view showing an effective manufacturing process using the manufacturing process shown in FIG. 4 as needed.

【図6】従来の樹脂封止型半導体装置用成形金型に、I
Cチップを搭載したリードフレームを挟んだ状態の断面
図である。
FIG. 6 shows a conventional molding die for a resin-sealed semiconductor device,
It is sectional drawing of the state which pinched | interposed the lead frame carrying C chip.

【図7】従来の樹脂封止型半導体装置用成形金型で製造
した樹脂封止型半導体装置の縦断面図である。
FIG. 7 is a vertical cross-sectional view of a resin-sealed semiconductor device manufactured by a conventional molding die for a resin-sealed semiconductor device.

【図8】従来の他の樹脂封止型半導体装置用成形金型で
製造した樹脂封止型半導体装置の縦断面図である。
FIG. 8 is a vertical cross-sectional view of a resin-sealed semiconductor device manufactured by another conventional molding die for a resin-sealed semiconductor device.

【符号の説明】[Explanation of symbols]

M 成形金型 1 半導体チップ(ICチップ) 2 ダイパッド 4 インナーリード 5 上金型 5A 上金型5のキャビティ 5a キャビティ5Aの内面 6 下金型 6A 上金型6のキャビティ 6a キャビティ6Aの内面 7 ランナ−部 8 ゲ−ト部 9 可動ピン 10 モ−ルド樹脂 11 ピン痕 12 バリ M Molding die 1 Semiconductor chip (IC chip) 2 Die pad 4 Inner lead 5 Upper die 5A Cavity of upper die 5a 5a Inner surface of cavity 5A 6 Lower die 6A Cavity of upper die 6a 6a Inner surface of cavity 6A 7 Runner -Part 8 Gate part 9 Movable pin 10 Mold resin 11 Pin mark 12 Burr

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】上下金型で構成された樹脂封止型半導体装
置の成形金型において、これら上下金型に形成し、封止
樹脂が注入される内面が平面なキャビティのそれぞれの
主型面において、半導体チップ及び又はダイパッドの移
動を規制する複数の可動ピンが設けられ、これらの可動
ピンの前記半導体チップ及び又は前記ダイパッドに近接
する先端部が、これら可動ピンが後退した状態の時に、
前記キャビティの内面と同一の平面を構成するように平
面に形成したことを特徴する樹脂封止型半導体装置用成
形金型。
1. A molding die for a resin-encapsulated semiconductor device composed of upper and lower dies, each main die surface of a cavity formed in the upper and lower dies and having a flat inner surface into which a sealing resin is injected. In, a plurality of movable pins for restricting the movement of the semiconductor chip and / or the die pad are provided, and the tip portions of these movable pins in the vicinity of the semiconductor chip and / or the die pad are in a state where these movable pins are retracted,
A molding die for a resin-sealed semiconductor device, which is formed so as to be flush with the inner surface of the cavity.
【請求項2】請求項1に記載の成形金型のキャビティの
所定の位置に半導体チップを搭載したリードフレームを
配置し、前記上下金型を締結し、そして前記上下金型に
設けた各可動ピンを前記半導体チップの方に可動、近接
させて、前記半導体チップの移動を規制するようにした
状態で、溶融した封止樹脂を前記成形金型に注入し、こ
の封止樹脂が前記半導体チップを殆ど覆い尽くした、或
いは全て覆い尽くした状態の時に、前記各可動ピンを、
それらの先端部の前記平面が前記上下金型の内面の平面
と同一の面を構成する位置まで引き戻し、前記封止樹脂
が前記各可動ピンが存在した位置の空間部を埋め尽くし
て硬化した後、前記上下金型を開き、樹脂封止された前
記半導体チップを離型して樹脂封止型半導体装置を得る
ことを特徴とする半導体チップの樹脂封止方法。
2. A lead frame on which a semiconductor chip is mounted is arranged at a predetermined position of a cavity of the molding die according to claim 1, the upper and lower dies are fastened, and each movable die provided on the upper and lower dies. The molten sealing resin is injected into the molding die in a state where the pins are moved and brought close to the semiconductor chip to restrict the movement of the semiconductor chip, and the sealing resin is the semiconductor chip. When it is almost completely covered, or when it is completely covered, each movable pin,
After the flat surfaces of the tips are pulled back to a position forming the same plane as the flat surfaces of the inner surfaces of the upper and lower molds, the sealing resin fills the space at the positions where the movable pins exist and is cured. A method of resin-sealing a semiconductor chip, comprising: opening the upper and lower molds and releasing the resin-sealed semiconductor chip to obtain a resin-sealed semiconductor device.
【請求項3】請求項2に記載の半導体チップの樹脂封止
方法において、前記注入した封止樹脂が硬化した後、前
記引き戻されていた一部又は全部の可動ピンを封止樹脂
側に可動させて、前記樹脂封止型半導体装置を離型する
とを特徴とする半導体チップの樹脂封止方法。
3. The semiconductor chip resin sealing method according to claim 2, wherein after the injected sealing resin is cured, some or all of the movable pins that have been pulled back are moved to the sealing resin side. Then, the resin encapsulation type semiconductor device is released from the mold.
JP4184854A 1992-07-13 1992-07-13 Die for forming resin-sealed semiconductor device and resin-seal of semiconductor chip used therefor Pending JPH0629340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4184854A JPH0629340A (en) 1992-07-13 1992-07-13 Die for forming resin-sealed semiconductor device and resin-seal of semiconductor chip used therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4184854A JPH0629340A (en) 1992-07-13 1992-07-13 Die for forming resin-sealed semiconductor device and resin-seal of semiconductor chip used therefor

Publications (1)

Publication Number Publication Date
JPH0629340A true JPH0629340A (en) 1994-02-04

Family

ID=16160471

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4184854A Pending JPH0629340A (en) 1992-07-13 1992-07-13 Die for forming resin-sealed semiconductor device and resin-seal of semiconductor chip used therefor

Country Status (1)

Country Link
JP (1) JPH0629340A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100448659B1 (en) * 2002-04-15 2004-09-13 (주)에이치디세미테크 semiconductor molding apparatus and molding method thereof
US7319042B2 (en) 2001-12-07 2008-01-15 Yamaha Corporation Method and apparatus for manufacture and inspection of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7319042B2 (en) 2001-12-07 2008-01-15 Yamaha Corporation Method and apparatus for manufacture and inspection of semiconductor device
KR100448659B1 (en) * 2002-04-15 2004-09-13 (주)에이치디세미테크 semiconductor molding apparatus and molding method thereof

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