JPH06290022A - Shifter - Google Patents

Abstract

PURPOSE:To improve the operation speed of a shifter and to reduce power consumption. CONSTITUTION:A reference unit circuit in this shifter is constituted of a clocked inverter 1A connecting its input terminal and output terminal to an input signal line Xi and an I/O signal line Yi L, respectively, and controlled by a control signal Li, a clocked inverter 1B connecting its input terminal and output terminal to the input signal line Xi and an I/O signal line YiR, respectively, and controlled by the inversion signal of the control signal Li, a clocked inverter 1C connecting its input terminal and output terminal to an I/O signal line TiL and an output signal line Xi+1, respectively, and controlled by a control signal Ri, and a clocked inverter 1D connecting its input terminal and output terminal respectively to the I/O signal line YiR and the output signal line Xi+1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shifter, and more particularly to a shifter implemented on a microprocessor.

[0002]

2. Description of the Related Art A shifter is an arithmetic unit having a function of shifting or rotating right or left by a designated number of bits for data having a bit width.

As a shifter of a microprocessor, there is conventionally a crossbar switch type shifter in which a MOS transistor operates as a switch. Although this shifter has regularity and is easy to layout, it has a drawback in that the delay in decoding becomes a bottleneck in speeding up.

On the other hand, three types of basic units 21C, 21M, 21 obtained by modifying the selector shown in FIG.
There is a shifter configured by arranging Ls in a matrix as shown in FIG. The right shift outputs the left data, the left shift outputs the right data, and otherwise outputs the input data at the same bit position to perform the shift operation.

The shift bit number S of the 2 ^n- bit shifter is
It is expressed by the following formula.

[0006]

The selector for the digit a _i = 1 passes the shifted data, and the selector for the digit a _i = 0 passes the non-shifted data. A signal corresponding to a _i in the case of right shift is represented by R _i , and a signal in the case of left shift is represented by L _i .

[0008]

The object of the present invention is as shown in FIG.
It is an object of the present invention to provide a shifter using a basic unit circuit which has a smaller number of fan-outs, operates at a higher speed, has a smaller number of elements, and has lower power consumption, as compared with the basic unit circuit shown in FIG.

[0009]

A shifter according to the present invention includes one input signal line, one output signal line, and first and second output signal lines.
Two input / output signal lines and the first and second control signal lines, which are in an inverse relationship with each other, respectively.
And a second clocked inverter, and third and fourth clocked inverters respectively controlled by third and fourth control signal lines which are in an inversion relationship with each other, and the first clocked inverter has an input An end is connected to the input signal line, an output end is connected to the first input / output signal line, and the second clocked inverter has an input end connected to the input signal line and an output end connected to the first input / output signal line. The second clocked inverter is connected to the second input / output signal line, the third clocked inverter has an input end connected to the first input / output signal line, an output end connected to the output signal line, and the fourth clock The inverter has an input terminal connected to the second input / output signal line,
A circuit configured to connect the output terminal to the output signal line is used as a basic unit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, preferred embodiments of the present invention will be described with reference to the drawings. 1A to 1C are circuit diagrams of a basic unit circuit used in a shift register according to an embodiment of the present invention. FIG. 2 is a block diagram of a shifter using the above basic unit circuit. In FIG. 1A, 1A, 1B, 1C and 1D are clocked inverters, R _i is a right shift signal at the i-th digit, and L _i is a right shift signal.
_i is a left shift signal at the _i- th digit, Y _i R and Y _i L are input / output signals for transferring the shifted signal, X _i is a non-shifted signal, and X _{i + 1} is a shift result signal. .

When performing the left shift, it is necessary to set 0 for the number of shift bits from the LSB side. Similarly, when performing right shift, it is necessary to sign-extend or zero-extend the number of shift bits from the MSB side. Therefore, the MSB
The side 2 ⁱ bit is the MSB basic unit circuit 2M shown in FIG. 1B, and the LSB side 2 ⁱ bit is the L shown in FIG. 1C.
The SB basic unit circuit 2L is used.

[0011] Hereinafter, the shift operation of this embodiment will be described with reference to FIGS. 3, 4 and 5 showing a selected state of the data of the first digit (2 ¹ bit). When no shift is performed (see FIG. 3) When neither right shift nor left shift is performed, R ₁ = L ₁ = 0
Is. Therefore, the clocked inverters 1B / 1D drive the output signal lines, so that data flows as shown by the thick black line in FIG. That is, when R ₁ = L ₁ = 0, non-shifted data is passed. Right 2 bit shift (see FIG. 4) When right 2 bit shift is performed, R ₁ = 1 and L ₁ = 0. Therefore, since the clocked inverters 1B / 1C drive the output signal lines, data flows as shown by the thick black line and the thick white line in FIG. X ₂ [7], X
_{2 The} sign extension bit SIGN is output to [6]. That is, right 2 bit shift is performed. Left 2 bit shift (see FIG. 5) When left 2 bit shift is performed, R ₁ = 0 and L ₁ = 1. Therefore, the clocked inverters 1A / 1D drive the output signal lines, so that data flows as shown by the thick black lines and the thick white lines in FIG. X ₂

[0], X
₂ [1] becomes 0. That is, left 2 bit shift is performed.

As is clear from the above description, the basic unit circuit shown in FIG. 6 has three fan-outs, whereas the basic unit circuit according to this embodiment shown in FIG. Will be faster.

Also, the number of transistors forming the basic unit circuit of this embodiment is significantly smaller than that in the basic unit circuit of the prior art. That is, when the 8-bit shifter shown in FIG. 2 is configured using the basic unit circuit according to the conventional technique, the number of transistors is (10 × 1).
6) + (7 × 14) + (7 × 18) = 444 (pieces), while using the basic unit circuit of this embodiment, (10 × 16) + (7 × 8) + ( 7 × 20) = 35
The number is 6 (pieces), which is reduced by about 20%, and the power consumption is reduced accordingly.

Further, since control signals having an inversion relation are required for controlling the clocked inverter, a total of 6 control lines are required in the basic unit circuit according to the prior art, whereas in the present embodiment. Only four lines are needed, and the effect on the layout is great.

[0015] Incidentally, the above embodiment has been described for the case of 8-bit, 2 ^3, 2 ^4, by adding ... it is easily scalable. Further, in the basic unit circuit shown in FIG. 1, the same effect can be obtained by using a transmission gate instead of the clocked inverter.

[0016]

As described above, the basic unit circuit used in the shifter of the present invention has two clocked inverters whose input terminals are commonly connected to the input data line and the output data line whose output terminal is commonly used. And two clocked inverters connected to each other in a rectifying diode bridge form, and each of the other pair of nodes different from the pair of nodes to which the input data line and the output data line are connected is shifted data. The clocked inverters arranged on opposite sides of each other are controlled to operate simultaneously.

As a result, according to the present invention, the number of fan-outs in the basic unit circuit can be made smaller than in the conventional case, so that a shifter which is faster than the conventional case and consumes less power can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an example of a basic unit circuit used in a shifter of the present invention.

FIG. 2 is a block diagram of an 8-bit shifter using the basic unit circuit shown in FIG.

FIG. 3 is a block diagram for explaining an operation when not shifting in the embodiment of the present invention.

FIG. 4 is a block diagram for explaining an operation of right 2 bit shift in the embodiment of the present invention.

FIG. 5 is a block diagram for explaining an operation of shifting left 2 bits in the embodiment of the present invention.

FIG. 6 is a circuit diagram of an example of a basic unit circuit used in a conventional shifter.

[Explanation of symbols]

 1A, 1B, 1C, 1D Clocked inverter 2C, 2M, 2L basic unit circuit 21C, 21M, 21L basic unit circuit

Claims (1)

[Claims] 1. A single input signal line, a single output signal line, first and second two input / output signal lines, and first and second control signal lines which are in an inverted relationship with each other. The first and second clocked inverters respectively controlled by the first and second clocked inverters and the third and fourth clocked inverters respectively controlled by the third and fourth control signal lines which are in inverse relation to each other, The clocked inverter has an input end connected to the input signal line, an output end connected to the first input / output signal line, and the second clocked inverter has an input end connected to the input signal line. The output end is connected to the second input / output signal line, and the third clocked inverter has an input end connected to the first input / output signal line.
And an output end connected to the output signal line, and the fourth clocked inverter has an input end connected to the second
A shifter characterized by using as a basic unit a circuit configured to be connected to the input / output signal line of and the output terminal thereof to be connected to the output signal line.