KR0159402B1 - Digital data transmission apparatus - Google Patents

Abstract

The present invention relates to an apparatus for transmitting and receiving digital data, comprising: demultiplexers (13, 23) for encoding and outputting digital signals represented by two logic levels into one digital signal represented by a plurality of logic levels; And multiplexers 14 and 24 for decoding one digital signal represented by the plurality of logic levels and decoding the digital signal represented by two logic levels.

Accordingly, the present invention can encode and transmit a logic level of a digital signal to be transmitted in various ways, and decode the signal transmitted by encoding a variety of logic levels into original digital data. Thus, a plurality of pieces of data are transmitted through one transmission line. Simultaneously transmit the data can reduce the data transmission time.

Description

Digital data transfer device

1 is a block diagram of a conventional digital data transmission apparatus.

2 is a waveform diagram showing a transmission state of digital data in a conventional digital data transmission apparatus.

3 is a block diagram of a digital data transmission apparatus according to the present invention.

4 is a block diagram of a demultiplexer formed in a digital data transmission apparatus according to the present invention.

5 is a block diagram of a multiplexer formed in a digital data transmission apparatus according to the present invention.

* Explanation of symbols for the main parts of the drawings

1: master device 2: slab device

11, 21: processor 12, 22: data input and output device

13, 23: demultiplexer 14, 24: multiplexer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data transmission device, and more particularly, to a digital data transmission device that enables the transmission of a plurality of digital data at the same time by changing the level of digital data.

A general digital data transmission device is configured to transmit only one data through one transmission line. That is, since a digital signal is represented by a logic high or low level, a general digital data transmission device transmits necessary information data by sequentially transmitting low or high level logic on a transmission line.

1 shows an example of a device for serially transmitting data in a general digital data transmission device. As shown, the master device 1 and the slab device 2 for transmitting and receiving data include processors 11, 21, and data input / output devices 12, 22 for processing data. Each is composed. In such a device, the data input / output devices 12 and 22 transmit and receive data in synchronization with the clock CK, as shown in FIG. That is, the master device 1 applies the data D1 to the slab device 2 via the transmission line L1, and the slab device 2 transmits the data D2 through the transmission line L2 to the master device ( It is applied to 1).

In the case of the data D1 and D2 transmitted and received in FIG. 2, a logic having a high level having a voltage of 5 V and a low level having a voltage of 0 V is taken as an example.

As can be seen from the above-described configuration, the conventional digital data transmission apparatus transmits and receives data D1 and D2 via transmission lines L1 and L2, so that the number of data simultaneously transmitted and received is equal to the transmission line L1, It is limited to the number of (L2). Therefore, since the processor 11, 21 in the conventional digital transmission device takes a lot of time to transmit data even if the device is a fast execution speed, the use efficiency of the processor 11, 21 is lowered There was.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to encode and transmit a logic level of a digital signal in various ways, and to decode a digital signal transmitted by encoding a variety of logic levels in such a manner as original data. It is possible to provide a digital data transmission apparatus capable of simultaneously transmitting a plurality of data through one transmission line.

The characteristic of this invention for achieving such an object is in.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a digital data transmission apparatus according to the present invention. As can be seen from the description below, in this embodiment, digital signals represented by two logic levels processed by the processors 11 and 21 are processed. In the case of encoding and transmitting one digital signal represented by four logic levels, and decoding one digital signal represented by four logic levels back to two logic levels as an example, in the technical field of the present invention A person of ordinary skill encodes and outputs a plurality of digital signals represented by two logic levels into a single digital signal represented by a plurality of logic levels from the following description, and one digital signal represented by a plurality of logic levels. It can be easily implemented to decode to the two logic levels described above.

As shown in FIG. 3, the digital data transmission device of the present invention is a demultiplexer 13, 23 and a multiplexer 14, which is connected to a conventional master device 1 and a slab device 2. 24) further comprises.

The demultiplexers 13 and 23 are composed of two inverters I1, I2 and three end gates A11, A12, and A13 as shown in FIG. The inverters I1 and I2 are connected to the data input terminals DI1 and DI2, respectively.

The AND gate A11 is configured to logically multiply the signals applied from the data input terminal DI1 and the inverter I2 to output to the data output terminal DO. At this time, the AND gate A11 outputs a logic voltage of 2 V when the logic level of the signal multiplied and output is high, and outputs the logic voltage when the logic level of the signal multiplied and output is low. Output at 0V.

The AND gate A12 performs a logic multiplication on the signals applied from the data input terminal DI2 and the inverter I1 and outputs the result to the data output terminal DO. When the output logic signal is high, the AND gate A12 is 3V. When the logic level of the output logic signal is low, the logic voltage is output as 0V. The AND gate A13 performs a logic multiplication on the signals applied from the data input terminals DI1 and DI2 and outputs the result to the data output terminal DO. When the logic level of the output signal is high, the AND gate A13 applies the logic voltage. It outputs as 5V, and when the logic level of an output logic signal is low, it outputs the logic voltage as 0V. At this time, in the present embodiment, the logic voltage is 5V when the logic level is high, and the digital data having the logic voltage 0V is applied to the data input terminals DI1 and DI2 when the logic level is low. Assumed.

The configuration of the multiplexers 14, 24 that receive logic signals from the demultiplexers 13, 23 of the above-described configuration is shown in FIG.

As shown, the multiplexers 14, 24 are composed of three switching transistors Q1, Q2, Q3, OR gate OR1, AND gate A21, and one exclusive NOR gate. It consists of (EX-NOR1).

The switching transistors Q1, Q2, and Q3 are connected to the data input terminal DI, respectively, and the transistor Q1 is applied with a voltage of 5V or more by the bias resistors R1 and R2. When driven, it is configured to output a voltage of 5V to the emitter stage.

The transistor Q2 is configured to drive when a voltage of 3V or more is applied by the bias resistors R3 and R4 to output a voltage of 5V to the emitter stage, and the transistor Q3 is a bias resistor. It is configured to drive when a voltage of 2V or more is applied by (R5) and (R6) to output a voltage of 5V to the emitter stage.

The OR gate is connected to the emitter stages of the transistors Q1 and Q2. The OR gate OR1 performs a logic sum of the signals output from the emitter stages of the transistors Q1 and Q2 to output the data output terminal DO1. It is configured to output

In addition, the exclusive NOR gate EX-NOR1 is connected to the emitter stages of the transistors Q1 and Q2, and the exclusive NOR gate EX-NOR1 is configured to output a signal output from the emitter stages of the transistors Q1 and Q2. It is configured to output exclusive logic sum and invert. The output terminal of the exclusive NOR gate EX-NOR1 and the emitter terminal of the transistor Q3 are connected to the end gate A21, and the end gate A21 is an output terminal and the transistor of the exclusive NOR gate EX-NOR1. The signal output from the emitter end of Q3 is ANDed and output to the data output terminal DO2.

The logical table 1 of the demultiplexers 13 and 23 configured as described above is shown in Table 1).

In Table 1, L means a logic low level and H means a logic high level.

Table 2) shows the logical table 2 of the multiplexers 14 and 24 which decode the digital data encoded in the four voltage states into the voltage states of the two voltages as shown in Table 1).

In Table 2), L means a logic low level, and H means a logic high level.

As can be seen from Tables 1 and 2, the demultiplexers 13 and 23 display four digital signals represented by two logic levels input through the data input terminals D1 and D2. A digital signal represented by two logic levels is encoded and transmitted, and the multiplexers 14 and 24 are represented by four logic levels applied from the demultiplexers 14 and 24. It can be seen that the digital signal is decoded back to the original two logic levels.

As described above, the present invention allows a plurality of pieces of data through one transmission line by encoding and transmitting a logic level of a digital signal to be transmitted in a variety of ways, and decoding a transmitted signal having variously encoded logic levels into original digital data. Simultaneously transmit the data can reduce the data transmission time.

Claims (1)

An apparatus for transmitting and receiving digital signals, comprising: first and second data input terminals DI1 and DI2 to which digital data represented by a first logic level indicating a high state and a second logic level indicating a low state are applied; First and second inverters I1 and I2 which invert and output digital data applied from the first and second data input terminals DI1 and DI2, and the first data input terminal DI1 and the second inverter. A first end gate A11 for performing a logic multiplication on the output of (I2) and outputting a low level as a first logic level and a high level as a third logic level, the second data input terminal DI2 and the first inverter Outputs the second end gate A12 and the outputs of the first and second data input terminals DI1 and DI2, Logically multiply the low level by the first logical level Demultiplexers 13 and 23, each of which is a third end gate AI3 for outputting the bellow high level as a second logic level; The first switching transistor Q1 for selectively driving the second logic level and outputting the first or second logic level and the second or fourth logic level when the second logic level is applied and driving the first or second logic level when the second or fourth logic level is applied. A second switching transistor Q2 for outputting a second logic level, and a third switching transistor for driving when the second, third or fourth logic level is applied to output a first or second logic level ( Q1), a first OR gate OR1 which logically sums the logic levels applied from the first and second switching transistors Q1 and Q2 and outputs them as digital data, and the first and second switching transistors ( Exclusive NOR gate EX-NOR1 outputs the logic level applied from Q1 and Q2 by inverting the exclusive logic sum, and outputs the logic level applied from the third switch transistor Q3 and the exclusive NOR gate E. And a multiplexer (14, 24) serving as a fourth end gate (A21) for outputting by logically multiplying the logic level applied from X-NOR1.