JPH10333649A - Voltage selecting circuit, liquid crystal driving circuit, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage selecting circuit, a liquid crystal driving circuit and a semiconductor device that can inspect a short and disconnection of a wire in a short time. SOLUTION: A liquid crystal driving circuit has a shift register formed out of n-pieces of D flip-flops, a control signal output circuit 12, transfer gates, a first inspection control circuit 1 to switch the operation of the shift register 11 during inspection and a second test control circuit 2 to switch the operation of the control signal output circuit 12 during inspection. During inspection, the first inspection control circuit 1 operates the shift register 11 as an inverter chain and the second test control circuit 2 turns on one of the transfer gates in response to the output of the shift register 11. In this way, the circuits are inspected in a significantly shorter time, independently of a reference clock and a frame signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a voltage selection circuit for selecting and outputting a desired voltage based on the logic of a serial input signal and the logic of a frame signal input to a shift register, a liquid crystal driving circuit, and a semiconductor device. In particular, the present invention is directed to a circuit for selecting and outputting a voltage for inverting and driving a liquid crystal panel.

[0002]

2. Description of the Related Art When a liquid crystal panel is driven, if a voltage is always applied to the liquid crystal layer in the panel in the same direction, the arrangement of the liquid crystal is solidified, the movement of the liquid crystal is slowed, and the display becomes dark. For this reason, there has been proposed a liquid crystal display device employing an inversion driving method in which a voltage applied to a liquid crystal layer is inverted in units of, for example, one frame (one screen).

FIG. 2 is a circuit diagram of a driving circuit (LCD driver) constituting a part of a conventional inversion driving type liquid crystal display device. The circuit of FIG. 2 includes a shift register 11 for sequentially shifting pixel data based on a reference clock CLK.
A control signal output circuit 12 provided for each output terminal of the shift register 11, and transfer gates 13a to 13a.
13d. The circuit in FIG. 2 shows a block 10 for one pixel. In actuality, n illustrated circuits are cascaded, and the entire circuit is formed on a semiconductor substrate. The shift register 11 includes clocked inverters 111 to 114
And a D flip-flop comprising inverters 115 and 116, and the dashed line in the figure shows the configuration of one D flip-flop.

The control signal output circuit 12 comprises four NAND
The transfer gate 13a includes gates 121 to 124 and inverters 125 to 129 according to the output logic of the shift register 11 and the logic of the frame signal FR.
Control signal SEL1 for on / off control of .about.13d
The logic of SEL4 is switched. More specifically, the control signal output circuit 12 includes four control signals SEL1 to SEL
4, only one of the control signals is set to a low level.

[0005] Different voltages are applied to the input terminals of the transfer gates 13a to 13d, respectively, and when any of the control signals SEL1 to SEL4 from the control signal output circuit 12 becomes low level, the corresponding transfer gate is turned on. Thus, the voltage applied to the input terminal is output from the output terminal.

Next, the operation of the liquid crystal drive circuit of FIG. 2 will be described. Pixel data IN for displaying on a liquid crystal panel (not shown) is serially input to the shift register 11 in FIG. 2 in the order of display pixels. The shift register 11 stores the pixel data 1
1 is output in parallel in synchronization with the reference clock CLK.

On the other hand, the control signal output circuit 12 receives a frame signal FR whose logic is inverted for each screen of the liquid crystal panel. The control signal output circuit 12 is connected to the shift register 1
The control signals SEL1 to SEL4 are output from the NAND gates 121 to 124 based on the logic of each output terminal 1 and the logic of the frame signal FR.

The control signals SEL1 to SEL4 are input to the corresponding transfer gates 13a to 13d, and the transfer gates 13a to 13d are turned on when the output of the corresponding NAND gate is at a low level, and turned on when the output is turned on. The voltage applied to the input terminal of the transfer gate is output from its output terminal.

For example, when the output of the shift register 11 is at a high level and the frame signal FR is at a low level, the transfer gate 13a is turned on and the voltage V4 is output. When both the output of the shift register 11 and the frame signal FR are at the high level, the transfer gate 13b is turned on and the voltage V3 is output. When both the output of the shift register 11 and the frame signal FR are at low level, the transfer gate 13c is turned on and the voltage V2 is output. Also, shift register 1
When the output of 1 is low and the frame signal FR is high, the transfer gate 13d is turned on and the voltage V1 is output.

As described above, the liquid crystal driving circuit of FIG. 2 switches the voltage applied to the liquid crystal panel for each screen, and when the voltages V1 and V2 are applied when displaying one screen, the next screen is displayed. Then, voltages V3 and V4 are applied, and thereafter, voltages V1 and V2 and voltages V3 and V4 are alternately applied for each screen. As a result, voltage is not applied only in the same direction of the liquid crystal layer, and problems such as solidification of the liquid crystal alignment do not occur.

By the way, the resolution of recent liquid crystal panels tends to be high. In order to drive a high resolution liquid crystal panel, the number of output terminals of a liquid crystal drive circuit must be increased, and with the increase in the number of terminals. As a result, problems such as short-circuiting and disconnection of the wiring are likely to occur.

For this reason, in the conventional liquid crystal drive circuit shown in FIG. 2, after assembling the circuit, a short circuit or disconnection of the wiring is inspected. As a specific inspection method, for example, an inspection using a so-called staggered output in which a high-level signal and a low-level signal are alternately output from an output terminal of a liquid crystal driving circuit has been performed. .

[0013]

However, since the pixel data input to the shift register 11 cannot be inspected unless it reaches all the D flip-flops constituting the shift register 11, the number of bits of the shift register 11 cannot be increased. There is a problem that the inspection time increases as the number increases. If the inspection takes a long time, the number of liquid crystal drive circuits that can be manufactured per unit time is also limited, which may increase the chip cost.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a voltage selection circuit, a liquid crystal drive circuit, and a semiconductor device capable of performing a short-time inspection of a short circuit or disconnection of a wiring. Is to provide.

[0015]

According to a first aspect of the present invention, a serial input signal input from the outside is sequentially shifted based on a reference clock.
A shift register that outputs the shifted serial input signal in parallel, a control signal output circuit that outputs a plurality of control signals that change according to the output logic of the shift register, and the logic of a frame signal input from the outside, And a plurality of voltage switch circuits provided corresponding to each of the control signals and switching whether or not to output a voltage applied to each input terminal in accordance with the logic of the control signal. In the first aspect, when a test instruction signal is input from the outside, the serial input signal input to the shift register is output in parallel from the shift register almost in real time irrespective of the timing of the reference clock. A test control circuit, and, when the test instruction signal is input, according to an output logic of the shift register. Only certain of the voltage switch circuit and a second test control circuit for controlling the control signal output circuit to turn on.

According to a second aspect of the present invention, there is provided a shift register for sequentially shifting serial input signals arranged in the order of display pixels of a liquid crystal panel based on a reference clock, and outputting the shifted serial input signals in parallel. A control signal output circuit that outputs a plurality of control signals that change according to an output logic and a logic of a frame signal input from the outside; A plurality of voltage switch circuits for switching whether to output the output voltage according to the logic of the control signal, and driving a liquid crystal panel based on the voltage output from any of the voltage switch circuits In the circuit, when a test instruction signal is input from outside, the serial input signal input to the shift register is A first test control circuit that outputs the data in parallel from the shift register almost in real time irrespective of the timing of the reference clock, and a specific test control signal when the test instruction signal is input, according to the output logic of the shift register. A second test control circuit that controls the control signal output circuit so that only the voltage switch circuit is turned on.

According to a third aspect of the present invention, in the liquid crystal driving circuit of the second aspect, the plurality of voltage switch circuits and the control signal output circuit are provided for each output terminal of the shift register, and the control signal output circuit Respectively select one of the plurality of voltage switch circuits based on the logic of the corresponding output terminal of the shift register and the logic of the frame signal.

According to a fourth aspect of the present invention, in the liquid crystal driving circuit according to the second or third aspect, the shift register includes a clocked inverter and an inverter,
The first test control circuit is configured to control a control terminal of the clocked inverter such that when the test instruction signal is input, the shift register equivalently operates as a circuit in which a plurality of inverters are connected in series. Fix the signal logic.

According to a fifth aspect of the present invention, in the liquid crystal driving circuit according to any one of the second to fourth aspects, the output terminals of the plurality of voltage switch circuits provided for each output terminal of the shift register are connected to each other. When the test instruction signal is input, voltages of different levels are output from adjacent external output terminals.

According to a sixth aspect of the present invention, in the liquid crystal driving circuit according to any one of the second to fifth aspects, when the test instruction signal is input, the second test control circuit includes:
One of the two voltage switch circuits is turned on according to the output logic of the shift register, and the shift register receives the serial input signal that alternates between a high level and a low level.

According to a seventh aspect of the present invention, in the liquid crystal driving circuit according to any one of the second to sixth aspects, the frame signal is a signal whose logic is inverted for each screen of the liquid crystal panel, and Four voltage switch circuits are provided for each output terminal, and the control signal output circuit sets the two voltage switch circuits in groups of two and turns them on alternately for each screen.

According to an eighth aspect of the present invention, in the liquid crystal driving circuit according to the seventh aspect, the first to fourth voltage switch circuits are provided for each output terminal of the shift register,
A first logic circuit that turns on the first voltage switch circuit when the output of the shift register is at a high level and the frame signal is at a low level; and an output of the shift register is at a high level. A second logic circuit that turns on the second voltage switch circuit when the frame signal is at a high level, and the third voltage when the output of the shift register is at a low level and the frame signal is at a low level. Third to turn on the switch circuit
And a fourth logic circuit that turns on the fourth voltage switch circuit when the output of the shift register is at a low level and the frame signal is at a high level.

According to a ninth aspect of the present invention, in the liquid crystal driving circuit according to any one of the second to eighth aspects, the voltage switch circuit is a transfer gate.

According to a tenth aspect, the voltage selection circuit according to the first aspect or the liquid crystal drive circuit according to any of the second to ninth aspects is formed on a semiconductor substrate.

The invention of claims 1 and 2 will be described with reference to, for example, FIG. 1. "Shift register" is a shift register 11 in FIG. 1, "control signal output circuit" is a control signal output circuit 12, The "voltage switch circuit" corresponds to the transfer gates 13a to 13d, the "first test control circuit" corresponds to the first test control circuit 1, and the "second test control circuit" corresponds to the second test control circuit 2, respectively. I do. Also,
The “test instruction signal” means a state where the test signal TEST is at a high level.

The invention of claim 8 will be described with reference to FIG. 1, for example. The "first logic circuit" is a NAND gate of FIG.
The "second logic circuit" corresponds to the NAND gate 122, the "third logic circuit" corresponds to the NAND gate 123, and the "fourth logic circuit" corresponds to the NAND gate 124.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a voltage selection circuit, a liquid crystal drive circuit, and a semiconductor device to which the present invention is applied will be specifically described with reference to the drawings. Hereinafter, as one embodiment of the present invention, the configuration and operation of a liquid crystal drive circuit for driving an active matrix type liquid crystal panel will be described.

FIG. 1 is a circuit diagram of an embodiment of a liquid crystal drive circuit. The liquid crystal drive circuit in FIG. 1 is for inverting and driving an active matrix type liquid crystal panel, and the entire circuit is formed on a semiconductor substrate. In FIG. 1, portions common to FIG. 2 are denoted by the same reference numerals, and the following description will focus on differences.

The circuit shown in FIG. 1 has a shift register 11 composed of n D flip-flops, a control signal output circuit 12, and transfer gates 13a to 13 as in FIG.
d. In addition, the circuit of FIG. 1 newly includes a first test control circuit 1 for switching the operation of the shift register 11 at the time of inspection, and a second test control circuit 2 for switching the operation of the control signal output circuit 12 at the time of inspection. .

In FIG. 1, a shift register 1 for two pixels is provided.
1, an example is shown in which the control signal output circuit 12 and the transfer gates 13a to 13d constitute one block 100, and n such blocks 100 are connected in cascade.

The first test control circuit 1 in each block 100 includes a NOR gate G1, a NAND gate G2,
The second test control circuit 2 has inverters INV1 to INV3, and has a NOR gate and G3, a NAND gate G4, and inverters INV4 to INV6. The first test control circuit 1 includes a test signal TEST for instructing an inspection and pixel data
A reference clock CLK for shifting IN is input. Further, the second test control circuit 2 includes a test signal TEST,
A frame signal FR whose logic is inverted for each screen is input.

Next, the operation of the control signal output circuit 12 of FIG. 1 will be described. When the test signal TEST is low level,
The first test control circuit 1 outputs the reference clock CLK as it is to the outputs F1 and F4, and outputs inverted signals of the reference clock CLK to the outputs F2 and F3. Further, the second test control circuit 2 outputs the frame signal FR as it is to the outputs G1 and G3, and outputs inverted signals of the frame signal FR to the outputs G2 and G4. Therefore, the circuit of FIG. 1 operates similarly to the circuit of FIG. On the other hand, when the test signal TEST is at a high level, that is, when performing a circuit connection test, the first test control circuit 1 fixes the outputs F1 and F4 to a high level and fixes the outputs F2 and F3 to a low level. I do. Therefore, the clocked inverter of each D flip-flop constituting the shift register 11 functions as a simple inverter, and each D flip-flop equivalently operates as a circuit in which four inverters are connected in series.

When the test signal TEST is at a high level, the second test control circuit 2 fixes the outputs G1 and G3 at a high level and fixes the outputs G2 and G4 at a low level. Therefore, the outputs of the NAND gates 121 and 123 in the control signal output circuit 12 are always at the low level, while the outputs of the NAND gates 122 and 124 change according to the logic of the output terminal of the shift register 11. Therefore, the transfer gates 13a and 13c are always off, and the transfer gate 13b is
Turns on when the output of the shift register 11 is at a high level, and the transfer gate 13d turns on when the output of the shift register 11 is at a low level.

As described above, the control signal output circuit 12 shown in FIG.
Operates when the test signal TEST goes high, regardless of the reference clock CLK and the frame signal FR.
When IN is at a high level, the transfer gate 13b is turned on, and when the pixel data IN is at a low level, the transfer gate 13d is turned on. Therefore, the voltage V3 applied to the input terminal of the transfer gate 13b is output from the output terminal of the liquid crystal drive circuit when the pixel data IN is at a high level, and the input of the transfer gate 13d is output when the pixel data IN is at a low level. The voltage V1 applied to the terminal is output.

For example, when performing a short-circuit / disconnection test between output terminals of a liquid crystal drive circuit, a signal in which a high level and a low level are alternately repeated is input as pixel data IN.
When voltages of different levels are applied to the input terminals of the transfer gates 13b and 13d, the voltage level of the output terminal of the control signal output circuit 12 can be changed alternately. It is possible to easily and accurately check whether or not a disconnection has occurred.

Also, in the circuit of FIG. 1, since the shift register 11 functions as a simple inverter chain at the time of inspection, it does not take much time until pixel data is distributed to all the D flip-flops in the shift register 11. Inspection time can be greatly reduced as compared with. That is, the time from the input of the pixel data for inspection to the shift register 11 to the output of the inspection result from the liquid crystal drive circuit can be significantly reduced as compared with the circuit of FIG.

In the above-described embodiment, an example has been described in which the present invention is applied to a liquid crystal driving circuit for driving a liquid crystal panel.
The present invention can be widely applied to a voltage selection circuit that selects any one of a plurality of types of voltages.

In FIG. 1, the transfer gate is turned on at the time of inspection, but which transistor is turned on can be arbitrarily changed. Although FIG. 1 shows an example in which four transfer gates are provided for each output terminal of the shift register 11, how many transfer gates are provided for each output terminal can be arbitrarily changed.

[0039]

As described above in detail, according to the present invention, when a test instruction signal is input from the outside, the serial input signal input to the shift register is converted almost in real time irrespective of the reference clock. , So the time it takes to get a test result can be reduced,
Test time can be significantly reduced. That is, when the test instruction signal is input, the parallel data is output from the shift register almost simultaneously with the input of the serial input signal, so that the test time varies depending on the number of registers constituting the shift register. And especially
When the number of registers is large, that is, when the number of output terminals of the shift register is large, the test time can be further reduced.

When a test instruction signal is input, regardless of the logic of the frame signal, the shift register 1
Since only a specific voltage switch circuit is turned on in accordance with the output logic of No. 1, it is not necessary to input a frame signal from the outside at the time of a test, and the test can be simplified.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of a liquid crystal driving circuit.

FIG. 2 is a circuit diagram of a conventional inversion driving type liquid crystal driving circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 first test control circuit 2 second test control circuit 11 shift register 12 control signal output circuit 13 a to 13 d transfer gate

Claims (10)

[Claims] A shift register for sequentially shifting a serial input signal input from the outside based on a reference clock, and outputting the shifted serial input signal in parallel; an output logic of the shift register; A control signal output circuit that outputs a plurality of control signals that change in accordance with the logic of the frame signal, and a control signal output circuit that is provided for each of the control signals and outputs a voltage applied to each input terminal. And a plurality of voltage switch circuits that switch between the two according to the logic of the control signal, when a test instruction signal is input from outside, the serial input signal input to the shift register, A first text output from the shift register in parallel almost in real time irrespective of the timing of the reference clock. And a second test control for controlling the control signal output circuit so that only the specific voltage switch circuit is turned on according to the output logic of the shift register when the test instruction signal is input. And a voltage selection circuit. 2. A shift register for sequentially shifting serial input signals arranged in the order of display pixels of a liquid crystal panel based on a reference clock, and outputting the shifted serial input signals in parallel; an output logic of the shift register; A control signal output circuit that outputs a plurality of control signals that change in accordance with the logic of a frame signal input from the control unit; and a voltage control unit that is provided in correspondence with each of the control signals and outputs a voltage applied to each input terminal. A plurality of voltage switch circuits for switching whether or not to perform according to the logic of the control signal, and a liquid crystal drive circuit that drives a liquid crystal panel based on a voltage output from any of the voltage switch circuits. When a test instruction signal is input, the serial input signal input to the shift register is converted to the reference clock. Irrespective of the timing, a first test control circuit for performing parallel output from the shift register substantially in real time, and a specific voltage switch according to an output logic of the shift register when the test instruction signal is input. A second test control circuit for controlling the control signal output circuit so that only the circuit is turned on. 3. The shift register according to claim 2, wherein the plurality of voltage switch circuits and the control signal output circuit are provided for each output terminal of the shift register. 3. The method according to claim 2, wherein one of the plurality of voltage switch circuits is selected based on a logic of the frame signal.
3. The liquid crystal drive circuit according to 1. 4. The shift register is configured to include a clocked inverter and an inverter, and the first test control circuit causes the shift register to be equivalent when the test instruction signal is input. 4. The liquid crystal drive circuit according to claim 2, wherein a signal logic of a control terminal of the clocked inverter is fixed so that the inverter operates as a circuit in which a plurality of inverters are connected in series. 5. The output terminals of the plurality of voltage switch circuits provided for each output terminal of the shift register are connected to each other to serve as external output terminals, and are adjacent when the test instruction signal is input. 5. The liquid crystal driving circuit according to claim 2, wherein voltages of different levels are output from the external output terminal. 6. When the test instruction signal is input, the second test control circuit turns on one of the two voltage switch circuits in accordance with the output logic of the shift register, and The liquid crystal drive circuit according to claim 2, wherein the register receives the serial input signal that alternates between a high level and a low level. 7. The frame signal is a signal whose logic is inverted for each screen of a liquid crystal panel, and four voltage switch circuits are provided for each output terminal of the shift register. 7. The liquid crystal drive circuit according to claim 2, wherein the circuit is configured such that the voltage switch circuits are set in groups of two and alternately turned on for each screen. 8. An output terminal of the shift register,
First to fourth voltage switch circuits are provided, and the control signal output circuit turns on the first voltage switch circuit when an output of the shift register is at a high level and the frame signal is at a low level. A second logic circuit for turning on the second voltage switch circuit when the output of the shift register is at a high level and the frame signal is at a high level; and when the output of the shift register is at a low level. A third logic circuit that turns on the third voltage switch circuit when the frame signal is at a low level; and a fourth voltage switch when the output of the shift register is at a low level and the frame signal is at a high level. The liquid crystal drive circuit according to claim 7, further comprising a fourth logic circuit for turning on the circuit. 9. The liquid crystal drive circuit according to claim 2, wherein said voltage switch circuit is a transfer gate. 10. A semiconductor device, wherein the voltage selection circuit according to claim 1 or the liquid crystal drive circuit according to claim 2 is formed on a semiconductor substrate.