JPH05174047A - Vector processor - Google Patents

Abstract

PURPOSE:To provide a vector processor which can carry out a coded multi-level logical arithmetic with a single instruction, can flexibly deal with various coding rules and arithmetic definitions with high universal applicability, and can perform the logical simulation at a high speed and with no deterioration of accuracy. CONSTITUTION:A vector processor consists of a main storage, a scalar processing part and a vector processing part. The vector processing part includes the registers 1-4, the decoders 5-20, the AND gates 405-916, and OR gates 917-948 in the form of a multi-level logical arithmetic circuit 1121 that can carry out a 2-bit quadruple logical operation. The 2-bit logical value codes to be calculated are taken out of the registers 1 and 2 and then decoded together by the decoders 8-20 to undergo an operation based on the truth value table data on the register 3. The result of this operation is outputted through the register 4 with a single operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector processing device, and is particularly used in a field requiring a complicated and high speed logical operation for changing a processing method for each bit in one word, such as in a logic simulation. Technology effectively applied to a vector processing device.

[0002]

2. Description of the Related Art For example, with the rapid spread and increase in scale of logic devices such as computers, reduction of the time required for development has become an issue. For this reason, development of various systems to support development, high speed Is being attempted. Among them, the logic circuit simulator used for design verification and test data creation is the system that must be made the most highly efficient because it is used for a long time. There are some known examples of achieving a significant speedup.

For example, pages 305 to 321 of 1987 IE Transactions on Computer Aided Design, Vol. 6, No. 3,
From 1988 ICI magazine 1982 to 2
There is a description about this on page 01. However, the conventional vector processing device assumes scientific and technical calculation, that is, floating-point determinant operation as its main application, and fine bit operation is necessary in processing mainly involving logical operation such as logical simulation. At the expense of speed, I had no choice but to use a complicated sequence of instructions.

Further, in the logic simulation, as described in the above-mentioned literature, it is necessary to introduce an uncertain value'X 'in addition to the usual logic values'0' and '1' in order to perform a correct simulation. There is. As a result, since the logical value is represented by a code of 2 bits or more instead of 1 bit, the logical operation of one element cannot be realized by one general-purpose logical operation instruction. Therefore, when the conventional general-purpose vector processing device is used, the arithmetic table is referred to or a plurality of instructions are combined to realize a predetermined arithmetic operation.

Further, there are some examples of a method of adding an arithmetic unit dedicated to the simulation in order to speed up the processing. For example, Japanese Patent Laid-Open No. 60-140441 discloses a vector process in which a logic element function and input signal data are stored in a vector register, and a plurality of logic elements including different types can be simulated by one instruction. The device is shown. This is provided with a storage device internally defining an operation table for all combinations of inputs of all the elements to be handled, and a predetermined operation can be performed by referring to a code of a logic element function and a combination of input logical values. Has been realized.

Further, in Japanese Patent Application Laid-Open No. 61-80452, by incorporating a dedicated arithmetic unit in which a shifter, an arithmetic unit, a merging circuit for each bit, etc. are connected in series, the shift amount, the type of arithmetic operation and the bit to be merged By specifying the position appropriately, the logical value coded into 2 bits or more,
There is disclosed a vector processing device that can be applied to a logic simulator that executes a logical operation in the case where a plurality of them are stored in one word by one instruction to increase the processing speed.

Further, in Japanese Patent Laid-Open No. 62-195570, a logic simulation incorporating a dedicated arithmetic unit for performing basic logical operations such as AND, OR and NOT according to a predetermined coding rule of 2 bits or more. A processor is shown.

[0008]

However, in the prior art as described above, when the main processing is a bit-wise logical operation such as a logical simulation using a logical value coded in 2 bits or more, If the method that refers to the operation table is adopted, the access to the main storage device is usually done in vector element units. Therefore, a parallel method that aims at speeding up by storing multiple data in one vector element and performing operation at once Cannot be used,
Further, since it takes time to refer to the storage device, there is a problem such as an obstacle to speeding up.

Further, in the case of realizing a multivalued logical operation by combining a plurality of instructions, in order to match the bit positions, or to operate one logical value data separately for each of the bits constituting it. The increase in processing time due to the increase in the number of instructions has become a problem.

On the other hand, in the method of adding a dedicated arithmetic unit,
The versatility of the added instruction and the manufacturing cost of the device are problems. In other words, a logic simulator that verifies the design of a logic circuit must start over from the design of a dedicated arithmetic unit if it cannot flexibly respond to changes in the design method, etc., and it retains its superiority in performance over general-purpose computers. Therefore, every time a new high-performance computer emerges, it must be remanufactured by a new technology. Therefore, since the manufacturing cost is not limited to one generation, ease of manufacturing and versatility with respect to the degree of improvement in performance due to addition are important problems.

Further, the above method of providing the arithmetic table in the processor cannot be applied to the parallel system because one address of the table is stored in one vector element, and the encoding of the logical value by a plurality of bits is possible. Whenever the rule of, the addition of a new element, the change of the operation of the element, etc., the definition contents of the operation table in the operation unit of the device must be changed by the initialization route different from the normal use, There is a problem of lack of versatility.

Further, in the case where an arithmetic unit specialized for a predetermined rule of encoding a logical value or a position within a vector element is added, there is a problem that the versatility is insufficient for the manufacturing cost. ..

Therefore, an object of the present invention is to allow a single instruction to execute the operation of the logical operation of an element in a multi-valued logic simulation coded to 2 bits or more, and further to register the register described in the operand of the program. By storing the truth table of the operation in, it has a highly versatile instruction that can be set freely in normal use except for the bit number of the logical value code and the position in the vector element. An object of the present invention is to provide a vector processing device capable of performing high-speed logic simulation without lowering accuracy.

Another object of the present invention is to deny by adopting a specific coding rule in the three-valued logic simulation of "0", "1" and "X" which has been widely used in the past. An object of the present invention is to provide a vector processing device capable of executing the basic logical operations AND, OR, and negation with one instruction at low cost simply by adding logical operation instructions.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0016]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the vector processing device of the present invention is
Each vector element in each vector data held in the first and second vector registers is divided into a plurality of data storage areas, and each divided area is represented by a code consisting of a certain number of bits. Operates according to the truth table stored in the third vector register, which stores the logical value data and stores the two logical value data at the corresponding positions between the two vector data, which is described as the operand code in the program. And the resulting logical value data is stored in the corresponding position of the vector data held in the fourth vector register by a single instruction.

In this case, the truth table stored in the third vector register can be arbitrarily defined.

Further, instead of the third vector register, the truth table is stored in the instruction register holding the operand code described in the program.

Further, another vector processing device of the present invention is
Each vector element in the vector data held in the fifth vector register is divided into 2-bit data storage areas, and logical value data represented by a 2-bit code is stored in each of these divided areas. A vector that stores and logically inverts each bit of the stored logical value data, then switches the values of the upper bit and the lower bit, and holds the resulting logical value data in the sixth vector register. A single instruction executes a process of storing data at a corresponding position.

[0021]

According to the above-described vector processing device, the first, second, third and fourth vector registers are provided, and the processing for storing the result from the operation of the logical value data according to the truth table is performed by a single instruction. It can be used as a simulator of the operation of a logic circuit by being executed by.

For example, in order to realize this vector processing device, a multivalued logical operation function for executing so-called arithmetic processing with a single instruction is provided, and in addition, a main memory device, a vector register and a scalar register, a vector register or Performs vector operation on data received from requester, vector register or scalar register that transfers data between scalar register and main memory,
A vector operation unit that stores the result in a vector register or a scalar register, a scalar operation that transfers data between the scalar register and the main memory and a general-purpose register, and stores the operation result of the data received from the general-purpose register in the general-purpose register. A processing unit and the like are provided.

The vector operation unit corresponds to a truth table from the first and second vector registers that receive the data to be operated from the vector register or the scalar register, which is the main part of the multi-valued logical operation function. Multi-valued logical operation that obtains the operation result by decoding the data in each data storage area of the first and second vector registers and referring to the third vector register A circuit, a fourth vector register that inputs the output of the vector operation unit and sends data to a vector register or a scalar register, and a selector circuit that sends out the fourth vector register when a specific instruction is executed are incorporated. There is.

In this case, the first and second vector registers of the multi-valued logic operation circuit are in a transition state with the times when the contents of the vector or scalar register described in the operands are applied to the input of the operation circuit. It has a function of not passing an uncertain signal, and the fourth vector register of the arithmetic circuit has a function of making the time of copying the operation result in the register uniform and not passing the uncertain operation result in the transition state. further,
The selector circuit has a function of taking out only a result corresponding to a specified instruction code from an arithmetic unit that outputs operation results corresponding to a plurality of types of instructions and sending the result to a vector or a scalar register.

As a result, the multi-valued logic operation circuit takes out a signal from the storage position of the predetermined logic value code consisting of a plurality of bits in the vector data to be operated, and the logic values of the positions where the operations are performed mutually. The data is decoded together, the truth table data on the register read from the scalar register is referenced to perform the operation, and the result of this operation is stored in the predetermined storage position of the vector or scalar register via the fourth vector register. Can be output.

According to the other vector processing device described above,
Uses as a simulator of the operation of a logic circuit by providing a fifth and a sixth vector register, and performing the process of exchanging the upper and lower bit values from the logical inversion of logical value data with a single instruction. You can

That is, a multi-valued logical operation function for executing arithmetic processing with a single instruction is provided, and a fifth vector register which receives data from a vector register or a scalar register, which is the main part thereof, and an output of this register are input. And a single-stage multi-valued logic operation circuit consisting only of an inverter that inverts a logic signal, a sixth vector register that outputs data to a vector register or a scalar register using the output of this operation circuit as an input, and the execution of a specific instruction Sometimes it incorporates a selector that sends out the sixth vector register.

As a result, the multi-valued logical operation circuit takes out a signal from the storage position of the predetermined logic value code of 2 bits in the vector data held in the fifth vector register and inverts the signal. The upper bit and the lower bit are exchanged, for example, logically "0" is two bits of 00, "1" is 11, and uncertain "X".
By expressing 10 as a logical negation operation can be performed by this operation.

[0029]

First Embodiment FIG. 1 is a schematic block diagram showing a vector processing device according to an embodiment of the present invention, and FIG. 2 is a general-purpose 4 which is a characteristic arithmetic circuit portion in the vector processing device according to the present embodiment.
FIG. 3 is a logical configuration diagram showing a value logic operation circuit, FIG. 3 is an explanatory diagram showing an example of a rule of logic value coding in a four value logic operation in the present embodiment, and FIG. 4 is a four value AND logic operation according to the rule of FIG. FIG. 5 is an explanatory diagram showing a truth table, and FIG. 5 is an explanatory diagram showing a storage sequence in the arithmetic circuit of FIG. 2 of the truth table of FIG.

First, the configuration of the vector processing apparatus of this embodiment will be described with reference to FIG.

The vector processing device of this embodiment represents a 4-valued logical value coded into 3 values or more, for example, 2 bits by a code of a plurality of bits, and defines a logical operation between these multivalued logical values. That is, it can be considered as a vector processing device to which a special function for this multi-valued logical operation is added, and is composed of a main memory device 1101, a scalar processing unit 1102 and a vector processing unit 1103.

The operation code and operand code of the scalar processing instruction stored in the main storage device 1101 are stored in the buffer storage device 1104 of the scalar processing unit 1102.
Is input to the operation control unit 1105 having an instruction buffer and an instruction decoder.

Scalar data stored in the main memory 1101 similarly passes through the buffer memory 1104,
In accordance with the instruction decoded by the arithmetic control unit 1105, it is input to the scalar arithmetic processing unit 1106 and loaded into the general-purpose register unit 1107 including a plurality of registers.

From the general-purpose register unit 1107, a plurality of scalar registers 1113 and a plurality of vector registers 1114 are provided.
When there is a data transfer instruction to the vector register section 1110 consisting of and the instruction is executed by the arithmetic control section 1105, the arithmetic control section 1109 of the vector processing section 1103.
A control signal is transmitted to the input side selector circuit 1112 of the vector register section 1110 to transfer data from the general-purpose register selected according to each register number described in the operand code of this instruction to the scalar register 1113.

Further, there is a data transfer instruction from the general-purpose register unit 1107 to the memory requester 1108, and when the instruction is executed by the arithmetic control unit 1105, a control signal is transmitted to the arithmetic control unit 1109 and the memory requester 110.
The address data is transferred from the general-purpose register of the designated number to the address register according to the number described in the operand code of this instruction in the address register unit 1124 composed of the plurality of internal address registers 1125.

The operation code and operand code of the vector processing instruction stored in the main storage device 1101 are input to the operation control unit 1109 via the buffer storage device 1104, similarly to the scalar processing instruction.
The main memory 1101 and the scalar register 1113 or the vector register 111 in the vector register unit 1110
There is a data transfer instruction to and from the communication terminal 4.

When these instructions are executed by the operation control unit 1109, in the case of a load instruction to a register, the selector circuit 1112 selects the scalar register 1113 of the corresponding number according to the description of the operand code of this instruction. , The address register 1125 of the corresponding number is selected by the control signal line 1126, and the main memory device 11
The scalar register 11 selected from the corresponding position of 01 via the memory requester 1108 and the signal line 1131
13 or the vector data is transferred to the vector register 1114.

In the case of a store instruction to the main memory 1101, the selector circuit 1115 selects the scalar register 1113 or the vector register 1114 of the corresponding number according to the description of the operand code of this instruction, and the address register of the corresponding number. 1125 is selected, and data is stored from the scalar register 1113 or the vector register 1114 to the main memory 1101 via the signal line 1132 and the memory requester 1108.

When executing an arithmetic instruction that is not a multi-valued logical operation for the vector data loaded in the vector register section 1110, the output data of the selected operated register is output by the selector circuit 1115 to the signal line 1128.
And is transferred to the vector calculator 1111 through the. The control circuit 11 receives the control signal via the control signal line 1127.
16 stores the data of the signal line 1128 in the register 1117 at an appropriate time, and the arithmetic circuit 1118 calculates the
The result is held in the register 1119 at an appropriate time, selected by the selector circuit 1123, and transferred to the vector register unit 1110 again by the signal line 1130. Further, the selector circuit 1112 selects the designated scalar register 1113 or vector register 1114 and stores the data from the signal line 1130.

When performing a multi-valued logical operation, the data from the vector register section 1110 passes through the signal line 1129, and the control circuit 1116 registers the register 1 at an appropriate time.
The data is held in 120 and operated in the multivalued logic operation circuit 1121, and the resulting data is held in the register 1122 at an appropriate time, selected by the selector circuit 1123, and transferred again to the vector register unit 1110.

As described above, the vector processing device of this embodiment has a configuration in which an arithmetic circuit having a novel multivalued logical operation function is added to the conventional vector processing device, and the vector operation is 32 bits. Assuming as an example a device that is executed in a unit pipeline processing, the register 112
3 of the first and second vector registers corresponding to 0 and the fourth vector register corresponding to the register 1122.
The book shows an example of 32 bits each. Hereinafter, the multi-valued logical operation circuit 1121 will be described in detail with reference to FIG.

The multivalued logic operation circuit 1121 is the control circuit 1
Four registers (first vector register) 1, a register (second vector register) 2, and a register (third vector register) 3 which hold data according to three control signal lines 981, 982 and 983 coming from 116. And register 4 (fourth vector register), 64 input signal lines 21 to 116 corresponding to signal lines from the output of the register 1120, 32 output signal lines 949 to 980 to the register 1122, and 4 bits. Input the binary signal of and select any one of 16 outputs 1
6 decoders 5-20 and these decoders 5-20
Output signal lines 149 to 404 and output signal lines 117 to 148 of the register 3, 512 AND gates 405 to 916, and outputs of the AND gates 405 to 916 corresponding to each bit of the register 4. It is composed of 32 OR gates 917 to 948.

Next, the operation of this embodiment will be described.

In this embodiment, the multivalued logic operation circuit 11
For the sake of convenience, the instruction using 21 is hereinafter referred to as a VX1 instruction (single instruction).

That is, since one vector element of the vector data is 32 bits, one element of the vector data designated by the second and third operands of the VX1 instruction is held in the registers 1 and 2 as it is. In this case, consider an example in which 32 bits of each element are divided into 16 pieces so that adjacent 2 bits form one data storage area.

For example, in FIG. 2, the position of the pair of signal lines (21, 22) of the register 1 is one area (51, 5).
There are 16 areas up to the group of 2). The same applies to the registers 2 and 4, from the position of the pair of signal lines of (53, 54) and (949, 950) to (83, 84), (979, 980).
Is divided into 16 areas each up to the position of the group.

Then, the VX1 instruction is executed in, for example, the signal line (2
1, 22) and (53, 54) are subjected to an arbitrary logical operation, and the resulting 2-bit data is converted into corresponding 2-bit data areas of the register 4, for example, signal lines (949, 95).
0) to store the calculation.

Therefore, the 16 decoders 5 to 20 correspond to the smaller order of the sign of the input signal line in the 16 data storage areas of the registers 1 and 2, and the data 2 bits of the register 1 are the upper 2 bits. The input destination of each decoder is determined so that the data 2 bits of the register 2 are the lower 2 bits.

On the other hand, when the scalar register storing the truth table is selected by the first operand code of the VX1 instruction, the truth table data defined for these multivalued logical values is stored in the register 3. It For example, in FIG. 2, each element of the truth table is 2 bits, and (1
(17,118) to (147,148),
Two adjacent bits represent one calculation result and are divided into 16 areas.

The 16 output signal lines of each decoder are connected to the register 3 in the order from the smallest code to the largest code.
16 sets of output signal lines are also corresponded in order from the smallest code to the largest code. For example, the signal line 149,
Signal lines 165 and 389 correspond to the signal lines (117 and 118), and signal lines 150, 166 and 390 correspond to the signal lines (119 and 120).

Between these signal lines, if the signal line on the decoder side, for example, 149 is logically 1, the value of the corresponding signal line on the register 3 side, for example (117, 118), is set to correspond to the register 4. Area, for example, the signal line 94
AND gates, for example 405 and 406, are connected to transfer to positions 9 and 950.

As a result, the operation result can be obtained by decoding the logical value combination of any data storage area and selecting the truth table of the register 3.

In this case, if the rule shown in FIG. 3 is used as the rule for encoding the logic value, the AND logic operation, which is a basic logic operation, becomes as shown in FIG.
Here, the 2 bits of the input 1 are set to the upper 2 bits, and the input 2
When the bit data of FIG. 4 are arranged in the order of 0 to 15 of the numerical value represented by 4 bits obtained by converting the 2 bits of 2 to the lower 2 bits, it becomes as shown in FIG.

When the AND operation is performed by the VX1 instruction under the above conditions, the data shown in FIG. 5 is stored in the register 3 through the signal lines 85 to 116 in the order of the bit positions. If the signal lines 21 and 22 are 0 and 0, 53 and 54
Are 0 and 1, the signal line 150 of the decoder 5 is
Becomes 1. Then, the AND gates 407 and 408 change the logical values of the signal lines 119 and 120 to the OR gate 917.
And 918 to be output to the signal lines 949 and 950 of the register 4. This is an operation in which the AND of "0" and "Z" becomes "0".

Therefore, according to the vector processing device of the present embodiment, the multi-valued logic operation circuit 1 capable of four-valued logic operation is provided.
By providing four registers 1 to 4, 16 decoders 5 to 20, 512 AND gates 405 to 916 and 32 OR gates 917 to 948 as 121, vector data to be operated from the registers 1 and 2 is provided. Of the predetermined logic value code consisting of 2 bits in each of the above, and the decoders 5 to 20 collectively decode the logic value data of the positions to be mutually operated, and refer to the truth table data on the register 3 Then, a single VX1 instruction can be used to perform the operation and output the operation result via the register 4.

[0056]

[Embodiment 2] FIG. 6 is a logical configuration diagram showing a three-valued logical NOT operation circuit which is a characteristic operation circuit portion in a vector processing apparatus which is another embodiment of the present invention, and FIG. FIG. 8 is an explanatory diagram showing an example of a rule for encoding a logical value of a value logical operation, and FIG. 8 is an explanatory diagram showing a truth table of three-valued AND, OR, and negative basic logical operations according to the rule of FIG.

The vector processing device of this embodiment has a multi-valued logical operation circuit 1121 added with a special function applied to an operation on a ternary logical value coded into, for example, 2 bits.
a, the circuit configuration is as shown in FIG. 6, two control signal lines 1002, 1 coming from the control circuit 1116 of FIG.
Two register (fifth vector register) 1000, a register (sixth vector register) 1001, and 32 input signal lines 100 corresponding to the signal lines from the output of the register 1120 according to 003.
4 to 1035, 32 output signal lines 1036 to 1067 to the register 1122, and 32 inverters 1068 to 1099 that invert each bit of the register 1000.

That is, the multivalued logic operation circuit 1 of this embodiment
121a is applied to an operation on a ternary logical value coded into 2 bits, and vector operation is performed by pipeline processing in units of 32 bits. As an example, two registers 1000 and 1001 are used. Shows an example of 32 bits each. An example of this encoding is shown in FIG.
FIG. 8 shows a truth table of the basic logical operations of AND, OR and negation at this time.

For example, when the operation instruction is applied to the logic simulation, only the combination of the rule that'X 'becomes 01 and the rule that' 0 'becomes 11 can be used as the negative logic operation.

Therefore, by examining the behavior of each bit in the truth table of FIG. 8, an AND operation can be expressed by an instruction that simply ANDs all conventional bits, and an OR operation can be simply expressed by all conventional bits. You can see that it can be expressed by an OR instruction that takes an OR. However, with respect to the negation operation, it is necessary to invert these two bits 0 and 1 and exchange the upper and lower bit positions, and the function of the instruction characterizing this embodiment corresponds to this negation operation.

Next, the operation of this embodiment will be described.

In this embodiment, the multivalued logic operation circuit 1
For the sake of convenience, the instruction using 121a is hereinafter referred to as a VX2 instruction (single instruction).

That is, since one vector element of the vector data is 32 bits, one element of the vector data designated by the second operand of the VX2 instruction is held in the register 1000 as it is.

In this case, the 32 bits of each element are divided into 16 bits, and the upper 16 bits store the upper bits of the 2-bit code, and the lower 16 bits are separated by 16 bits from each bit position to the upper bits. Consider an example of storing lower bit data corresponding to higher bit data at different positions. That is, the data storage area is divided into 16 areas by pairs of bits separated by 16 bits.

All the bits of the register 1000 are inverted by the inverters 1068 to 1099, and the upper and lower sides are switched by the subsequent connection. For example, in the third data'X '(10) from the left of the register 1000, the upper bit data transferred from the signal line 1006 is 1, which is inverted by the inverter 1070 and transferred to the signal line 1054. ..

The lower bit data transferred from the signal line 1022 is 0, which is inverted by the inverter 1086 and transferred to the signal line 1038. As a result, the data in the third storage area from the left of the register 1001 becomes “X” (10), which satisfies the negative operation.

Therefore, according to the vector processing device of the present embodiment, the multi-valued logical operation circuit 1 capable of performing three-valued logical operation.
By providing two registers 1000 and 1001 and 32 inverters 1068 to 1099 as 121a, the AND operation and the OR operation can be expressed by an AND instruction or OR instruction of all bits as in the conventional case, and the negative operation can also be performed. , A signal of a predetermined logical value code consisting of 2 bits each in the vector data held in the register 1000 is taken out, and the inverter 1
A single VX2 instruction can be used to perform the inversion by 068 to 1099, exchange the upper bit and the lower bit, and output the operation result via the register 1001.

Although the invention made by the present inventor has been specifically described based on the first and second embodiments, the present invention is not limited to the above-described embodiments and various modifications are possible without departing from the scope of the invention. Needless to say, it can be changed.

For example, regarding the multi-valued logical operation circuit 1121 in the vector processing device of the first embodiment, when the logical value is represented by 2 bits and it becomes a 4-valued logical value, the vector operation is performed in 32-bit pipelines. The case where each of the three registers 1, 2 and 4 has 32 bits has been described on the assumption that the device is used in the processing, but the present invention is not limited to the above-mentioned embodiment, and the truth table is used. It can be widely applied to the case of arbitrarily defining or expressing a logical value with n bits.

To represent this logical value by n bits, the bit width of the register 3 is multiplied by (2 2n power) times n, the decoder is 2n bit input and 2 2n power bit output, and the register 3 is Scalar register 111 in FIG.
Data is transferred from 3 and used as a truth table.

For example, the bit width of the scalar register is 3
When n is 2, one scalar register is specified by the operand of the instruction using this operation circuit when n is 2, and when n is 3, the width is 192 bits. Specifies the scalar register of. Further, when the unit of pipeline processing is 32 m bits, the number of decoders, AND gates, OR gates, register 1,
The bit widths of 2 and 4 are m times as large as those in FIG.

Further, the multivalued logic operation circuit 1 of the second embodiment
Regarding 121a, an example in which two registers 1000 and 1001 each have 32 bits is shown assuming a device in which vector operation is performed by pipeline processing in 32 bit units. Is 3
If it is 2m bits, the number of inverters, register 1
The bit widths of 000 and 1001 are m in the case of FIG. 6, respectively.
Need to double.

Further, in the first embodiment, if the instruction word length is sufficiently long, the instruction register holding the operation code described in the program is used for holding the truth table instead of the register 3, and the operation code It is also possible to consider a part as a truth table and perform an operation.

[0074]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1). Operation according to the truth table stored in the third vector register for two pieces of logical value data having a fixed number of bits divided and stored in the first and second vector registers By executing the process of storing the resulting logical value data in the fourth vector register with a single instruction, the core unit of processing, which conventionally required several instructions, is processed with a single instruction. Therefore, the processing time can be reduced as a simulator of the operation of the logic circuit.

(2). Regarding the logical value data of 2 bits divided and stored in the fifth vector register, each bit is logically inverted, and then the value of the upper bit and the value of the lower bit are exchanged. By performing the process of storing the resulting logical value data in the sixth vector register with a single instruction, when handling a large-scale circuit, it becomes possible to perform the process with a simple process. The number of evaluation processing instructions can be reduced.

(3) By the above (1) or (2), the number of coded bits is fixed, but any kind of operation can be freely defined within that range while the user is using it. It is possible to obtain a vector processing device that can easily support special elements and simulation models that have employed complex instruction sequences without interruption.

(4) According to the above (1) or (2), a logic value encoding rule is limited to a part, but a vector processing device capable of reducing the manufacturing cost by a simple arithmetic function configuration is obtained. be able to.

(5) According to the above (1) or (2), it is possible to flexibly deal with various coding rules and operation definitions by arbitrarily defining the truth table, and it is possible to improve versatility. Can be obtained.

(6) Since the number of instructions and the processing time can be reduced by the above (1) or (2), the vector processing is particularly effective when applied to the simulation of a logic circuit. The device can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a vector processing device that is Embodiment 1 of the present invention.

FIG. 2 is a logical configuration diagram showing a general-purpose four-valued logical operation circuit which is a characteristic operation circuit portion in the vector processing device of the first embodiment.

FIG. 3 is an explanatory diagram showing a rule example of logical value encoding in a four-valued logical operation in the first embodiment.

FIG. 4 is an explanatory diagram showing a truth table in a four-valued AND logic operation according to the rule of FIG. 3 in the first embodiment.

5 is an explanatory diagram showing a storage sequence of the truth table of FIG. 4 in the arithmetic circuit of FIG. 2 in Embodiment 1. FIG.

FIG. 6 is a logical configuration diagram showing a ternary logical NOT operation circuit which is a characteristic operation circuit portion in the vector processing device according to the second embodiment of the present invention.

FIG. 7 is an explanatory diagram showing an example of rules for logical value encoding of a three-valued logical operation in the second embodiment.

8 is an explanatory diagram showing a truth table of three-valued AND, OR, and negation basic logical operations according to the rule of FIG. 7 in Example 2; FIG.

[Explanation of symbols]

 1 register (first vector register) 2 register (second vector register) 3 register (third vector register) 4 register (fourth vector register) 5-20 decoder 21-116 input signal line 117-148 output Signal line 149 to 404 Output signal line 405 to 916 AND gate 917 to 948 OR gate 949 to 980 Output signal line 981 to 983 Control signal line 1000 register (fifth vector register) 1001 register (sixth vector register) 1002, 1003 Control signal lines 1004 to 1035 Input signal lines 1036 to 1067 Output signal lines 1068 to 1099 Inverter 1101 Main storage device 1102 Scalar processing unit 1103 Vector processing unit 1104 Buffer storage device 1105 Operation control unit 1106 Color arithmetic processing unit 1107 General-purpose register unit 1108 Memory requester 1109 Operation control unit 1110 Vector register unit 1111 Vector arithmetic unit 1112 Selector circuit 1113 Scalar register 1114 Vector register 1115 Selector circuit 1116 Control circuit 1117 register 1118 Operation circuit 1119 register 1120 register 1121, 1121a Multivalued logic operation circuit 1122 register 1123 selector circuit 1124 address register unit 1125 address register 1126, 1127 control signal line 1128 to 1132 signal line

Claims (4)

[Claims] 1. A vector element in each vector data held in the first and second vector registers is divided into a plurality of data storage areas, and each divided area is coded with a constant number of bits. A truth value that stores the represented logical value data and stores the two logical value data at corresponding positions between the two vector data in a third vector register described as an operand code in the program. A vector processing device, characterized in that a single instruction executes a process of performing an operation according to a table and storing the resulting logical value data in a corresponding position of vector data held in a fourth vector register. 2. The vector processing device according to claim 1, wherein the truth table stored in the third vector register can be arbitrarily defined. 3. Instead of the third vector register,
2. The vector processing device according to claim 1, wherein the truth table is stored in an instruction register that holds an operand code described in the program. 4. Each vector element in the vector data held in the fifth vector register is divided into 2-bit data storage areas, and each divided area is represented by a code of 2 bits. The logical value data is stored, each bit is logically inverted with respect to the stored logical value data, and the value of the high-order bit and the value of the low-order bit are exchanged, and the resulting logical-value data is stored in the sixth vector register. A vector processing device characterized by executing a process of storing in a corresponding position of vector data held by a single instruction.