JPH0628892A - Device for testing semiconductor memory ic - Google Patents

Abstract

PURPOSE:To provide a semiconductor memory IC test device improving selection efficiency more than usual in the case of testing and selecting a memory IC having a lot of I/O terminals. CONSTITUTION:Single data st1-16 are written in a memory IC previously through a data input/output terminal. At the time of reading the data, respective input/ output data st1-16 are inputted to a data succssive output circuit 3, and the serial output SE is inputted from one piece of input/output combination terminal successively. By comparing reference data inputted from a write data generator A with a set of operation result data comparator/detector B, the semiconductor memory IC test device testing many memory ICs having a lot of input/output terminals in parallel is constituted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory IC test apparatus, and more particularly to a connection section between a memory IC under test and a memory IC tester section.

[0002]

2. Description of the Related Art Generally, there are various kinds of test patterns used for judging the quality of memory characteristics of a memory IC under test. The relationship between the test time and the memory capacity N is directly proportional to the memory capacity and the test time. So-called "N
Pattern "and" NN pattern "in which the test time is proportional to the square of the memory capacity.

In order to cope with such an increase in test time, a technical development for increasing the test efficiency of one semiconductor memory IC test device (hereinafter, simply referred to as a memory IC test device), that is, the number of ICs that can be tested simultaneously. However, the conventional memory IC test apparatus is capable of testing up to 64 memory ICs under test having four input / output port I / Os at a time even with the most advanced apparatus.

Next, a block diagram showing an example of a conventional memory IC test apparatus of FIG. 7 will be described.

The conventional memory IC test equipment 7 is provided with 16 input / output ports I / O in order to carry out a pass / fail test of the memory characteristics of the memory cells in the memory IC 1 under test. There are 16 write data generators A1 to A16 for supplying test data S1 to S16 to the output port I / O, and 16 read data comparators B1 to B16 for inputting read data s1 to s16, respectively. is doing.

Write data generators A1 to A1 of the IC tester unit 5
A test program for testing the characteristics of the memory under test IC is preset in A16, the test is started by the timing signal of the test start, and the test data S1 to S16 are used to pass through the I / O port of the IC under test. Is written in the memory cell.

The test data written next is
The read data s1 to s16 are sequentially read from the I / O port to the IC test apparatus 7, and the read data comparators B1 to B16 first read the memory IC under test.
The test data S1 to S16 written to the read data and the read data s1 to s16 are compared to determine whether the data match. If they do not match, the memory cell of the corresponding memory under test IC is defective, so the memory IC is tested by outputting the information to a display device (not shown) or a printing device (not shown). Was there.

[0008]

The above-mentioned conventional semiconductor memory IC test device is normally used to test up to 64 memory ICs under test having four input / output ports at one time. Is. This is because the structure of the operation result data comparison / inspection device inside the memory IC tester for testing the read data from the IC is complicated and the cost is high. This is because the memory IC test device designed to meet the above requirement is used, which substantially limits the number of operation result data comparison / inspection devices.

However, with the recent increase in the memory capacity of memory ICs, the number of input / output ports thereof has also increased, causing a problem of test efficiency. For example, 16 I / O ports
When testing a plurality of memory ICs using the conventional memory IC test apparatus, 16 memory under test I
Since only C can be tested, there is a problem that the test efficiency becomes 1/4 as compared with the case of testing an IC having a small memory capacity and four input / output ports.

The object of the present invention has been made in view of the above-mentioned problems, and by eliminating the drawbacks of the conventional semiconductor memory IC testing apparatus, a memory IC having many input / output terminals is provided.
In selecting non-defective products, a large number of memory ICs can be tested in parallel by converting the read data output in parallel from the memory ICs into serial data and sequentially comparing it with the reference data. It is an object of the present invention to provide a semiconductor memory IC testing device capable of improving the sorting efficiency.

[0011]

SUMMARY OF THE INVENTION A feature of the present invention is a write data generator that generates write data for a single test.
An IC having an operation result data comparison / inspection device that sequentially compares the plurality of read data read from the memory cells of the plurality of memory ICs under test that read the write data for test with the reference data for each predetermined period. The tester part and the write data for the test are input from the input / output switching end and output from the fixed write end, and the plurality of read data read from the memory cells are input from the fixed read end to switch the input / output. An input / output switching circuit that outputs from the end and a single piece of the write data that is input from the write fixed end are branched and supplied to a plurality of input / output ports of the memory IC under test to supply to the memory cell. The write data branch circuit for writing and the plurality of read data read from the memory cells via the plurality of input / output ports are input in synchronization with an external signal and are sequentially converted into data. And conversion is to have a data sequence output circuit for outputting to the read fixed end.

Further, the plurality of read data sequentially output from the data sequential output circuit can be determined only at the output timing of the first read data at an arbitrary time by the external signal, and the second and subsequent read data can be determined. It may be a data sequential output circuit that outputs the first read data.

Furthermore, the plurality of read data sequentially output from the data sequential output circuit may be data sequential output circuits whose output timings can be determined at arbitrary times by the external signals.

[0014]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention,
2 is a specific circuit diagram of the data sequential output comparison circuit 3, and FIG. 3 is an output signal waveform diagram for explaining the operation of the circuit shown in FIG.

The semiconductor memory IC test apparatus includes a write data generator A for supplying a single test write data ST to an input / output contact N and a write data ST inside the memory under test IC1. A timing signal generation circuit 30 that sequentially outputs read data st1 to st16 read from a plurality of read memory cells as a waveform of one shot.
And an IC tester unit 5 having an operation result data comparison / inspection unit B for inputting the output signal SE of the data sequential output circuit 3 composed of the transfer gates 31 to 46 from the input / output contact N and comparing it with the reference comparison data, The input / output switching circuit 4 for inputting the write data ST from the input / output contact N to the input / output terminal C and outputting it from the write fixed end W, and the memory under test for inputting the write data ST from the write fixed end W. Via the write data branch circuit 2 for branching and supplying the same write data ST to the 16 input / output port I / Os of the IC1 and writing to the corresponding memory cell, and the 16 input / output port I / Os. The read data st1 to st16 of a plurality of memory cells, the data sequential output circuit 3 that sequentially outputs the read data st1 to st16 as a waveform of one shot, and the data sequential output circuit 3 are activated. Trigger signal TR is an external signal
It is comprised including the connection part 6 which has IG.

First, when a single test write data ST is written in the memory cell of the memory under test IC1 for the purpose of testing the memory characteristic, the write data generator A of the IC tester section 5 writes the data. The data ST is input to the write data branch circuit 2 via the input / output switching end C of the input / output switching circuit 4 and the write fixed end W. Then, the data ST input to the branch circuit 2 is supplied to the 16 input / output ports I / O of the memory under test IC1 through 16 data lines, and the same test for the corresponding memory cells inside is performed. Write data ST is written. Here, the input / output switching circuit 4 is switched in advance by the external write enable data WE.

Next, the operation of reading the memory data st1 to st16 recorded in the memory cells of the memory IC1 will be described. Read data st1 to s output from the 16 input / output ports I / O of the memory under test IC1
t16 is input to the data sequential output circuit 3.

The data sequential output circuit 3 receives a trigger signal TRI from the outside and delays the signal by inverters 471 to 474, an exclusive OR circuit 475 and an inverter 476.
62, one-shot timing signal φ ₁
φ ₁₆ and inversion φ _{1 to} φ ₁₆ are generated. Memory under test IC
Read data st1 to st16 (FIG. 3s)
t1 to st16) are timing signals φ ₁ to
phi _16, are sequentially sampled by the transfer gate 31 to 46 for each period of the inverted phi ₁ to [phi] _16, the output signal S
It is sent as E to the read fixed end R of the input / output switching circuit 4 (SE in FIG. 3).

Next, the input / output data SE as a waveform of one shot is supplied to the operation result data comparison / inspection unit B of the IC tester unit 5 through the read fixed terminal R and the input / output switching terminal C of the input / output switching circuit 4. To be done.

At this time, the waveform of the output data SE of the data sequence output circuit 3 becomes the waveform shown in FIG. 3 as described above, and the waveforms of st1 to st16 are shown in SE as one-shot waveforms. The output of the first stage of SE, that is, the output start time of st1 is determined by the trigger signal TRIG, and each one-shot signal width and signal interval are predetermined by the timing signal generation circuit 47 of the data sequential output circuit 3 with small fluctuation. The value has been determined.

Therefore, each st1 to s of each SE signal is
It suffices that the operation result data comparison / inspection device B successively compare and inspect the levels in the data-fixed state at t16. The time for this comparative inspection can be set to be much shorter than the time for the memory test.

Further, in this embodiment, since all 16 pieces of read data st1 to st16 are the same, it is only necessary to provide one write data generator A and one operation result data comparison / inspection device B to obtain 16 data pieces. A memory test of the memory write / read characteristics of a plurality of memory cells corresponding to the input / output ports becomes possible.

Next, a second embodiment of the present invention will be described. FIG. 4 is a block diagram of a second embodiment of the present invention,
FIG. 5 is a circuit diagram of the data sequential output circuit 3 in the second embodiment. 6 is a waveform diagram of the output signal of FIG.

The semiconductor memory IC test apparatus 7 includes a write data generator A for supplying a single test write data ST to the input / output node N, and the write data ST inside the memory under test IC1. The read data st1 to st16 read out from the plurality of memory cells that have been read are sequentially output as a waveform of one shot, and the output SE of the shift register as the data sequential output circuit 3 is input from the input / output node N to write the data. An IC tester unit 5 having an operation result data comparison / inspection unit B for comparing with reference comparison data input from the embedded data generator A, and write data ST is input from the input / output node N to the input / output switching end C and written. Input / output switching circuit 4 which outputs from the fixed input terminal W, and 16 input / output ports I / O of the memory under test 1 by inputting write data ST from the fixed write terminal W.
Read data st1 to st16 of a plurality of memory cells via the write data branch circuit 2 for branching and supplying the same write data ST to the corresponding memory cell and writing to the corresponding memory cell and 16 input / output port I / O. And a shift register that is a data sequential output circuit 3 that sequentially outputs each one-shot waveform, and a trigger signal T that is an external signal that activates the shift register and determines the signal width and signal interval of each one shot.
And a connection portion 6 having a RIG and a start signal φ ₀ .

Next, the operation of the block will be described.
The operation of writing the test write data ST into the memory cell in the IC1 is the same as that in the first embodiment.
The operation of reading the aforementioned memory data already written in the memory cell for testing will be described.

The operation of reading the memory data st1 to st16 recorded in the memory cell of the memory IC1 will be described.

Read data st1 to st16 output from the 16 input / output port I / Os of the memory under test IC1.
Is input to the data sequential output circuit 3.

When the external trigger signal TRIG is input, the data sequential output circuit 3 receives the inverters 311 and 3 respectively.
12, 314 and the exclusive logic circuit 313 generate the clock signal C and the inverted C, and the shift register (S) including the latch (LA) 315 and the four latches (LA) is generated.
R) Supply as clock for 316-330.

When the start signal φ ₀ is input to the touch (LA) 315 in the first stage, the timing signal φ ₁ and the inverted φ ₁ are generated, and the timing signal φ ₁ is sent to the shift register (SR) 316 in the next stage. The shift register (SR) 316 is a clock signal C of the timing signal φ _1.
The timing signal φ ₂ and the inversion φ ₂ are generated at the timing of the third clock signal C counted from the above, and similarly the timing signals φ ₂ and φ ₃ are generated by the shift registers (SR) 317 to 330.
_{3 to} φ ₁₆ and inversion φ _{3 to} φ ₁₆ are generated (FIG. 6 TRIG,
C, inversion C, φ ₀ , φ _{1 to} φ ₁₆ ).

The read data st1 to st16 (FIG. 6 st1 to st16) read from the memory IC to be tested are respectively timing signals φ _{1 to} φ ₁₆ , as in the first embodiment.
Transfer gates 31 to 31 for each period of inversion φ _{1 to} φ ₁₆
Sequentially sampled by 46, and sent as an output signal SE to the read fixed terminal R of the input / output switching circuit 4 (FIG. 6).
SE). Next, each output data SE as a waveform of one shot is supplied to the operation result data comparison / inspection unit B of the IC tester unit 5 through the read fixed terminal R and the input / output terminal C of the input / output switching circuit 4.

At this time, the waveform of the output data SE of the data sequential output circuit 3 composed of the shift register becomes the waveform shown in FIG. 6 as described above, and the waveforms of st1 to st16 are shown in SE as one shot waveforms. . Here, the difference from the first embodiment is that the first stage output of the signal SE, that is, the output start time of st1 is the trigger signal TR.
It is determined not only by the IG and the start signal φ ₀ , but also by the trigger signal TRIG in each one-shot signal width and signal interval after the second stage.

Therefore, each st1 to s of each SE signal is
The level in the data-fixed state at t16 may be sequentially inspected by the operation result data comparison / inspection device B at arbitrary timing. The time for this comparative inspection can be set to be much shorter than the time for the memory test.

Further, in the second embodiment, since all 16 pieces of read data st1 to st16 are the same, it is only necessary to provide the write data generator A and the operation result data comparison check B one by one so that 16 pieces of read data are provided. A memory test of the memory write / read characteristics of a plurality of memory cells corresponding to the input / output ports becomes possible.

[0034]

As described above, according to the present invention, a set of write data for generating test data to be written in the memory under test IC is simultaneously written through the input / output switching circuit and the write data branch circuit. The data sequentially read from the plurality of output ports I / O of the memory under test IC are combined into one by the data sequential output circuit and sequentially output in a time division manner,
Since a pair of operation result data comparison / inspection devices sequentially perform comparisons via the input / output switching circuit, a large number of memory under test IC1 having a large number of input / output port I / Os can be tested at the same time, and the test efficiency is improved. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a data sequential output circuit according to a first embodiment.

FIG. 3 is a waveform diagram for explaining the operation of the first embodiment shown in FIGS. 1 and 2.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a data sequential output circuit according to a second embodiment.

FIG. 6 is a waveform diagram for explaining the operation of the second embodiment shown in FIGS. 4 and 5.

FIG. 7 is a block diagram showing an example of a conventional semiconductor memory IC test device.

[Explanation of symbols]

 1 Test Memory IC 2 Write Data Branch Circuit 3 Data Sequential Output Circuit 4 Input / Output Switching Circuit 5 IC Tester Section 6 Connection Section 7 Memory IC Test Device A Write Data Generator B Calculation Result Data Comparison Inspector SE Data Sequential Output Circuit output data ST write data st1 to st16 read data

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 21/66 W 7352-4M

Claims (3)

[Claims] 1. A write data generator which generates write data for a single test, and a plurality of read data from memory cells of a plurality of memory ICs under test which read the write data for the test. An IC having an operation result data comparison / inspection device that sequentially compares read data with reference data for each predetermined period.
The tester part and the write data for the test are input from the input / output switching end and output from the fixed write end, and the plurality of read data read from the memory cells are input from the fixed read end to switch the input / output. An input / output switching circuit that outputs from the end and a single piece of the write data that is input from the write fixed end are branched and supplied to a plurality of input / output ports of the memory IC under test to supply to the memory cell. The write data branch circuit for writing and the plurality of read data read from the memory cells via the plurality of input / output ports are input in synchronization with an external signal and are sequentially converted into data and output to the read fixed terminal. Memory IC testing apparatus having a data sequential output circuit for 2. The plurality of read data sequentially output from the data sequential output circuit can be determined by the external signal only at the output timing of the first read data at any time, and the read data of the second and subsequent read data can be determined. 2. The semiconductor memory IC test device according to claim 1, wherein the semiconductor memory IC test device is a data sequential output circuit that is output following the first read data. 3. The data sequential output circuit, wherein the output timings of the plurality of read data sequentially output from the data sequential output circuit can be determined at arbitrary times by the external signal. The semiconductor memory IC test device according to 1.