JPH06284388A - Synchronization processing circuit for television system converter - Google Patents

Abstract

PURPOSE:To make it possible to surely fetch the timing reference signal prepared by a processing system before a conversion in the processing system after the conversion, in a television system converter. CONSTITUTION:After the timing reference pulse prepared by the timing signal generation circuit 13 of a processing system before a conversion is shaped by a clock frequency-dividing the system clock before a conversion in a first D flip-flop 31, and is further shaped by the clock frequency-dividing the system clock after the conversion in a second D flip-flop 34, the pulse is made of the one cycle width of the system clock after the conversion in a pulse take-out circuit 14 and it is supplied to the timing signal generation circuit 15 of the processing system after the conversion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television system converter used in a MUSE-NTSC converter or the like, for synchronizing processing of the television system converter for synchronizing the two systems before and after conversion. It is about circuits.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a configuration example of a television system converter.

In FIG. 6, a video signal converted by the television system is input from an input terminal 1, and a predetermined video signal processing circuit 3, a time base conversion memory 4 and a second video signal processing circuit 5 are provided. By being processed, it is converted into the target television system and then output from the output terminal 2.

Here, the writing process of the time base conversion memory 4 and the first video signal processing circuit 3 operate with the clock and the timing signal created by the first clock / timing signal creating circuit 6, while the time The reading process of the axis conversion memory 4 and the second video signal processing circuit 5 are
It operates with the clock and timing signal created by the timing signal creation circuit 7.

FIG. 3 is a block circuit diagram showing a synchronization processing circuit of a conventional television system converter, more specifically, a television system converter, for example, a high-definition signal (M).
USE signal) as standard television signal (NTSC signal)
FIG. 6 shows an example of the configuration of a conventional clock / timing signal generation circuit in a MUSE-NTSC converter for converting into a. Further, FIG. 4 is a timing chart for explaining the operation of the synchronization processing circuit of the conventional television system conversion device, and FIG. 5 illustrates an erroneous operation of the synchronization processing circuit of the conventional television system conversion device. 3 is a timing chart for

Note that examples of the configuration of the present television system conversion apparatus are disclosed in Japanese Patent Application Nos. 1-223779, 1-269298, and 3-82458 by the present applicant.

In FIG. 3, the MUSE signal is input from the input terminal 11, and the frame pulse detection circuit 12 and the first
Is supplied to the clock generation circuit 21. The frame pulse detection circuit 12 detects the frame pulse multiplexed in the MUSE signal. The detected frame pulse is input to the first timing signal generation circuit 13 as a timing reference pulse. The first timing signal generation circuit 13 creates control signals for the write processing unit of the time base conversion memory 4 and the first video signal processing circuit 3 in FIG. 6, and also serves as a timing reference for the second timing signal generation circuit 15. A frame pulse FP1 is created as a pulse.

The first clock generation circuit 21 is an MSUE.
The signal resample clock is regenerated, and the frame pulse detection circuit 12, the first timing signal generation circuit 13, the write processing section of the time base conversion memory 4 in FIG. 6 and the system clock of the first video signal processing circuit 3 are reproduced. Supply as CK1.

Further, the clock CK1 output from the first clock generating circuit 21 is frequency-divided by the first frequency dividing circuit 24 and input to the phase comparison circuit 22 as the clock CK3. The clock CK2 output from the second clock generation circuit 23 is frequency-divided by the second frequency division circuit 25 and input to the phase comparison circuit 22 as the clock CK4. The phase comparison circuit 22 compares the phase difference between the clock CK3 and the clock CK4, and controls the second clock generation circuit 23 based on the result. By configuring such a phase locked loop (PLL), the clock CK
2 is synchronized with the clock CK1. The clock CK2 generated by the second clock generation circuit 23 is a pulse extraction circuit 14, a second timing signal generation circuit 15 described below, a read processing unit of the time base conversion memory 4 in FIG. It is supplied as the system clock CK2 of the video signal processing circuit 5.

The frame pulse FP1 generated by the first timing signal generation circuit 13 is a pulse extraction circuit 14
Is shaped into a pulse having a width of one clock of the clock CK2, and is input to the second timing signal generation circuit 15 as a timing reference pulse. The second timing signal generation circuit 15 is the time axis conversion memory 4 in FIG.
And a control signal for the writing processing unit and the first video signal processing circuit 3 are created.

Next, FIG. 4 shows the timing until the frame pulse FP1 is output from the first timing signal generating circuit 13 and taken in by the second timing signal generating circuit 15.

Here, the clock CK1 and the clock CK2
Has the same phase difference for every greatest common divisor of the two clock frequencies. For example, if the frequency of the clock CK1 is 16.2
MHz, clock CK2 frequency is 14.742 MHz
Then, every 162 KHz, that is, 1 of the clock CK1
The phase difference becomes the same every 00 clocks and 91 clocks of the clock CK2.

The frame pulse FP1 is output from the first timing signal generation circuit 13 in synchronization with the clock CK1 and then the pulse extraction circuit 14 outputs the clock CK2.
After being shaped as a pulse FP4 ′ having a 1-clock width in synchronization with, the pulse is supplied as a reference pulse for the second timing signal generation circuit 15.

[0014]

However, in the above structure, as shown in FIG. 5, when the phase difference between the frame pulse FP1 and the clock CK2 is small, that is, the frame pulse input in the pulse extracting circuit 14 is input. FP1
When the setup time and hold time of the clock CK2 are smaller than the required values, the operation of the pulse extraction circuit 14 becomes unstable, and the frame pulse FP4 ′ is randomly output as a pulse shifted by about one clock. As a result, the image displayed on the display randomly shakes left and right.

This is the second clock generation circuit 23.
Although it can be improved by adjusting the phase of the clock CK2, it is necessary to adjust the period of the clock CK2 within 68 ns, and it takes time to adjust the phase, and there is a possibility that the phase shifts due to temperature change, secular change, etc. There is. Therefore, the frame pulse FP1 output from the first timing signal generation circuit 13 is reliably output from the clock extraction circuit 1
It is necessary to take in 4.

Therefore, the present invention has an object to provide a synchronous processing circuit of a television conversion device capable of reliably incorporating a timing reference signal created in a processing system before conversion into the processing system after conversion. To do.

[0017]

A television system converter according to the present invention includes a first timing signal generating circuit for generating a control signal for processing a first video signal,
For the second timing signal generating circuit that generates a control signal for processing the second video signal and the reference pulse output from the first timing signal generating circuit, the first clock is set to m · N1 minutes. A first waveform shaping circuit for shaping with a third clock that has been divided, and a fourth clock obtained by dividing the second clock by m · N2 with respect to the reference pulse shaped by the first waveform shaping circuit. A second waveform shaping circuit for shaping, outputting from the first timing signal generating circuit,
The reference pulse shaped by the first waveform shaping circuit and the second waveform shaping circuit is sequentially input to the second timing signal generating circuit.

[0018]

In the present invention, the first waveform shaping circuit produces the first pulse with respect to the reference pulse output from the first timing signal generating circuit for producing the control signal for processing the first video signal. The clock is shaped by the third clock divided by m · N1 (where m> 1 is an integer), and
For the reference pulse shaped by the first waveform shaping circuit,
Second timing signal generation for shaping the second clock by the fourth clock divided by m · N2 by the second waveform shaping circuit and creating a control signal for processing the second video signal Use as input to the circuit. As a result, the first video signal operating at the first clock is converted into the second video signal operating at the second clock having an integer ratio N1: N2 with the first clock.
Convert to the video signal of.

[0019]

1 is a block circuit diagram showing a synchronization processing circuit of a television system converter according to an embodiment of the present invention.
FIG. 2 is a timing chart for explaining the operation of the synchronization processing circuit of the television system conversion apparatus according to the embodiment of the present invention. In the figure, the same reference numerals and symbols as those of the conventional example indicate the same or corresponding components as those of the conventional example, and therefore, duplicated description is omitted here.

The frame pulse FP1 output from the first timing signal generating circuit 13 is input to the first D flip-flop 31 and is waveform-shaped at the timing of the clock CK3 'created by the procedure described later to produce the frame pulse FP2. Is output as. The frame pulse FP2 is
It is input to the second D flip-flop 34, waveform-shaped at the timing of a clock CK4 ′ created by the procedure described later, and output as a frame pulse FP3. The frame pulse FP3 is shaped by the pulse extraction circuit 14 as a frame pulse FP4 having a one-clock width of the clock CK2, and is input to the second timing signal generation circuit 15 as a reference pulse.

Next, a method of generating a clock CK3 'and a clock CK4', which are drive clocks for the first D flip-flop 31 and the second D flip-flop 34, respectively, will be described.

The clock CK3 'is supplied to the first frequency dividing circuit 24.
Of the clock CK3 output by the third D flip-flop 33.
Created by shaping with 1 '. Here, the clock CK1 ′ is created by inverting the clock CK1 by the first inverter 32.

In the same procedure, the clock CK4 'is the fourth clock of the clock CK4 output by the second frequency divider circuit 25.
It is created by shaping by the D flip-flop 36 of FIG. 1 by the inverted clock CK2 ′ of the clock CK2.
Here, the clock CK2 ′ is created by inverting the clock CK2 by the second inverter 35.

In the MUSE-NTSC converter, the clock CK1 is 16.2 MHz, and the clock CK2 varies depending on the conversion mode, but 14.742 in the wide mode.
MHz. Therefore, since the phase comparison circuit 22 performs phase comparison, the frequency division ratio of the first frequency division circuit 24 and the second frequency division circuit 25 is 100: 91. That is, the frequencies of the clock CK3 and the clock CK4 are such that N is an integer of 1 or more,
It is set to 162 / N (KHz). When the second D flip-flop 34 shapes the frame pulse FP2 synchronized with the clock CK3 'with the clock CK4', there is a setup time and a hold time of the phase difference between the clock CK3 'and the clock CK4'.

In particular, in the conventional example shown in FIGS. 3, 4 and 5, the phase difference between the frame pulse FP1 and the clock CK2 in the pulse extraction circuit 14 is the period 68 of the clock CK2.
Although it was necessary to adjust the time within about ns, in the present embodiment, the clock CK3 ′ and the clock CK4 ′, that is, the clock C.
If the frequencies of K3 and clock CK4 are 162 KHz, one cycle is about 6 μs, and the phase difference between clock CK3 and clock CK4 may be adjusted during this cycle.

As described above, the clock CK3 and the clock CK4 are input to the phase comparison circuit 22 and input to the clock CK.
2 is used in a phase-locked loop (PLL) for synchronizing 2 with the clock CK1, and in the state where the phases are synchronized, the frequency is the same and the phase difference has a constant width. Clock CK3
The phase difference between the clock CK4 and the clock CK4 may be in a range of values that can be compared by the phase comparison circuit 22, but is normally set to a phase difference of about 180 degrees for stable operation of the PLL. Therefore, when the frame pulse shaped by the clock CK3 is shaped again by the clock CK4, there is a sufficient margin in its setup time and hold time, and it is possible to reliably capture it.

The synchronization processing circuit of the television system converter of the present embodiment is arranged such that the first video signal operating at the first clock f1 has the second ratio which is in the relation of the integer ratio N1: N2 with the first clock f1. In a television system converter for converting into a second video signal which operates at the clock f2 of the first video signal, a first timing signal generating circuit 13 for generating a control signal for processing the first video signal, and a second video signal. With respect to the reference pulse output from the second timing signal generating circuit 15 that generates a control signal for processing the signal and the first timing signal generating circuit 13, the first clock f1 is set to m.
A first D flip-flop 31 and a third D 3 which are shaped by a third clock f3 divided by N1 (however, an integer of m> 1)
A second waveform f2 for the first waveform shaping circuit including the D flip-flop 33 and the inverter 32 and the reference pulse shaped by the first waveform shaping circuit.
A second D flip-flop 34 and a fourth D flip-flop 36 which are shaped by the fourth clock f4 divided by N2.
And a second waveform shaping circuit including an inverter 35, and outputs from the first timing signal generating circuit 13,
The reference pulse shaped by the first waveform shaping circuit and the second waveform shaping circuit in turn is input to the second timing signal generating circuit 15.

That is, in the present embodiment, the timing reference pulse generated by the timing signal generating circuit 13 of the processing system before conversion is a clock obtained by dividing the system clock before conversion by the first D flip-flop 31. Shaped with
Further, after the system clock after conversion is shaped by the second D flip-flop 34 with a divided clock, the pulse extraction circuit 14 sets the width of one cycle of the system clock after conversion to the processing system after conversion. Is supplied to the second timing signal generating circuit 15.

Therefore, the timing reference signal created by the processing system before conversion can be reliably taken into the processing system after conversion. Therefore, the operation of the pulse extraction circuit 14 becomes stable, and the image displayed on the display does not shake left and right. Also, the cycle 6 of the clock CK2
There is no need to make adjustments within 8 ns, and it is possible to avoid the trouble of adjusting the phase and the phase being shifted due to temperature change, aging change, and the like.

[0030]

As described above, according to the synchronous processing circuit of the television system converter of the present invention, the first timing signal generating circuit for generating the control signal for processing the first video signal is used. For the output reference pulse,
The first waveform shaping circuit sets the first clock to m · N1 (m>
It is shaped by the third clock divided by 1) and the second clock is changed by the second waveform shaping circuit to m · N2 with respect to the reference pulse shaped by the first waveform shaping circuit. It is shaped by the divided fourth clock and is used as an input of the second timing signal generation circuit for creating a control signal for processing the second video signal, and it is operated by the first clock. The first video signal can be converted into a second video signal operating at a second clock having an integer ratio N1: N2 with the first clock, and further, the first timing signal of the processing system before conversion. The timing reference pulse created by the generation circuit is shaped by dividing the system clock before conversion, and by shaping the converted system clock by dividing the clock. The width of one cycle of Te, from supplied to the second timing signal generating circuit of the processing system after the conversion, the timing reference signal generated by the pre-conversion processing system, it is possible to capture reliably the processing system after the conversion.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a synchronization processing circuit of a television system converter according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the synchronization processing circuit of the television system conversion apparatus according to the embodiment of the present invention.

FIG. 3 is a block circuit diagram showing a synchronization processing circuit of a conventional television system conversion device.

FIG. 4 is a timing chart for explaining the operation of the synchronization processing circuit of the conventional television system conversion device.

FIG. 5 is a timing chart for explaining an erroneous operation of the synchronization processing circuit of the conventional television system conversion device.

FIG. 6 is a block diagram showing a configuration example of a television system conversion device.

[Explanation of symbols]

 12 frame pulse detection circuit 13 first timing signal generation circuit 14 pulse extraction circuit 15 second timing signal generation circuit 21 first clock generation circuit 22 phase comparison circuit 23 second clock generation circuit 24 first frequency division circuit 25 second frequency divider circuit 31 first D flip-flop 34 second D flip-flop

Claims (1)

[Claims] 1. A television for converting a first video signal operating at a first clock into a second video signal operating at a second clock having an integer ratio N1: N2 with the first clock. In the system conversion device, a first timing signal generation circuit for generating a control signal for processing the first video signal and a second timing signal generation for generating a control signal for processing the second video signal The circuit and the reference pulse output from the first timing signal generation circuit are shaped by a third clock obtained by dividing the first clock by m · N1 (where m> 1 is an integer). With respect to the waveform shaping circuit and the reference pulse shaped by the first waveform shaping circuit, the second clock is set to m · N 2
A second waveform shaping circuit for shaping with a divided fourth clock, outputting from the first timing signal generating circuit, and sequentially
Of the waveform shaping circuit, and the reference pulse shaped by the second waveform shaping circuit is used as an input of the second timing signal generating circuit.