JPH06283678A - Mos semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To increase the electrostatic withstanding voltage of a MOS semiconductor device without increasing the drain area of its output section by sharing the same channel to an ordinarily diffused drain MOS transistor and double diffused drain MOD transistor formed in its internal circuit. CONSTITUTION:The title semiconductor device is provided with an internal circuit formed in a semiconductor substrate 1 and an output buffer circuit which is electrically connected to the internal circuit. In the NAND circuit constituting the internal circuit, a double diffused drain is formed by forming Nch and Pch well areas in the substrate 1 surrounded by selectively formed oxide layers 10 and N<+> drain areas 4' and 5' in the Nch well areas. Of course, gates 16 are positioned in the Nch areas between N drains 4 and 5. In the Pch well areas, on the other hand, transistors are formed by providing gates 16 between P<+> areas 14 and 15 and connected to the output buffer circuit of the next stage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor device and a method of manufacturing the same, and more particularly, to an electrostatic withstand voltage (Electro Stability).
Suitable for improving atic discharge (abbreviated as ESD).

[0002]

2. Description of the Related Art Among semiconductor elements, MOS semiconductor devices are becoming finer and the electric field in the vicinity of the drain becomes stronger, which causes problems such as hot electrons. The solution is GDD (Graded Diffused Drain) shown in Fig. 2.
And LDD (Lightly Dopped Drain) 2 which is shown in Fig. 3
A MOS transistor having a heavy diffusion drain structure is used, and its main part will be described below.

That is, the GDD MOS semiconductor device shown in FIG.
A gate oxide film 2 having a double-diffused drain structure and provided so as to cover a surface portion of a P type semiconductor substrate 1 of the first conductivity type.
, A polycrystalline silicon layer 3 functioning as a gate layer is overlaid. Further, by using the gate oxide film 2 and the polycrystalline silicon layer 3 as a mask, N-type impurities are introduced and diffused to form a second conductivity type N-type impurity.
⁺ Form drains 4 ', 5'. Also below this,
The other N ⁻ drains 4 and 5 are installed to form a double diffused drain. The portion of the semiconductor substrate 1 directly below the gate oxide film 2 operates as a so-called channel region. The second
The conductivity type N ⁺ drains 4 ′ and 5 ′ are formed to have a lower concentration than the other drains 4 and 5 formed below.

On the other hand, in the LDD MOS semiconductor device shown in FIG. 3, the formation positions of the other drains 4 and 5 of the second conductivity type are adjacent to the thickness portions of the drains 4'and 5'of the same conductivity type. The point of installation is different from the structure in Fig. 2. The manufacturing process is performed by using the sidewall A of the stacked body of the polycrystalline silicon layer 3 and the gate oxide film 2.
That is, the feature is that the polyside 6 formed in the direction intersecting the longitudinal direction of the semiconductor substrate 1 is used as a mask, and the impurity concentration between them is made different.

The structure of FIG. 3 has a merit that the surge withstand capability is improved because the time until the breakdown (Break Down) caused by the surge is faster than that of the structure of FIG.

FIG. 1 clarifies a cross-sectional view of a so-called normal diffusion drain structure MOS transistor, in which a gate oxide is formed on the surface portion of the P-type semiconductor substrate 1 located between the drains 7 and 8 formed by normal diffusion. The film 2 is provided and the polycrystalline silicon layer 3 is formed on the film 2 in the same manner as in FIGS. In the MOS semiconductor device of FIGS. 1 to 3, the insulating layer 9 is covered to serve as an external protective layer.

Next, an outline of the process of mounting the GDD MOS semiconductor device having the second conductivity type N ⁺ drains 4 ', 5'of FIG. 2 will be described with reference to FIGS. That is, for example, a selective oxide layer 10 having a thickness of about 15,000 angstroms is provided on a silicon semiconductor substrate 1, and a P well region 11 containing B of 10 × ¹⁵ × 10 cm ⁻³ is formed on the semiconductor substrate 1 located between them. Are formed (see FIG. 4). A gate oxide film 2 having a thickness of about 150 Å is provided on the surface of the P-well region 11, a polycrystalline silicon layer 3 is deposited, and then a conventional photolithography (Phto Lithograph) is performed.
Patterning is performed by the step y) to form a film having a thickness of about 4000 angstroms at approximately the center of the gate oxide film 2.

Subsequently, as shown in FIG. 5, after covering the perforated resist pattern 12 functioning as an implantation mask, P ions are implanted and diffused to form N ⁺ drains 4'and 5'as shown in FIG. By doing so, a GDD double diffused drain MOS semiconductor device can be obtained.

[0009]

Double diffused drain MO
In the S semiconductor device, there is a problem that the withstand capability against static electricity applied to the output terminal is reduced. This electrostatic withstand capability has a very large pattern dependency, but if the withstand capability of the output terminal is to be increased, a technique of widening the drain area is adopted. However, the area of the semiconductor chip becomes large, which leads to an increase in cost. Further, a method in which a resistor is attached to the output terminal is conceivable, but it cannot be said to be a practical method because the current driving capability of the semiconductor device is reduced.

On the other hand, as a method for minimizing the chip area of the semiconductor device, only the transistor in the output section is used as a double diffused drain, and the impurity in the low concentration layer is increased by an additional ion implantation process to increase the concentration. Although it can be considered, the cost increase due to the increase in man-hours cannot be denied.

The present invention has been made in view of the above circumstances, and particularly provides a MOS semiconductor device having a large electrostatic resistance and a method of manufacturing the same without increasing the drain area of the output section.

[0012]

A normal diffusion drain M formed in the internal circuit, which includes an internal circuit formed in a semiconductor substrate and an output buffer circuit electrically connected to the internal circuit.
The MOS type semiconductor device according to the present invention is characterized in that the OS transistor and the double diffused drain MOS transistor are shared as the same channel. Further, only a high-concentration ion implantation region for forming a double diffused drain is provided below a contact formed in the double diffused drain MOS type semiconductor device, that is, a normal diffused drain formed in an internal circuit formed on the semiconductor substrate. MOS transistor and 2
A MOS semiconductor device sharing the same diffused drain MOS transistor as the same channel is installed in its input / output circuit section, a double diffused drain MOS transistor connected to the internal circuit and its input section, and an output of the output buffer circuit. Diffusion drain MOS connected to the
It is also characterized in that the gate length of the normal diffusion drain MOS transistor connected to the internal circuit and its input portion is larger than the minimum gate length of the double diffusion drain MOS transistor. Furthermore,
A step of selectively forming an insulator region on the semiconductor substrate; a step of forming a well region of the first conductivity type between the insulator regions; and a step of covering the surface of the well region of the first conductivity type with a gate oxide. A step of depositing a polycrystalline silicon layer on the gate oxide, a step of providing a mask while leaving a well region corresponding to the side wall of the polycrystalline silicon layer, and a step of forming a drain region in the well region. A step of depositing a layer serving as a mask for high-concentration ion implantation on the side wall of the polycrystalline silicon layer, a step of forming another drain region in a well region adjacent to the drain region, In the step of forming an internal circuit in the portion
The method of manufacturing the S-type semiconductor device is characterized.

[0013]

The MOS type semiconductor device according to the present invention comprises an internal circuit and an output buffer circuit which are electrically connected. The structure of the MOS transistor for the internal circuit is Pch.
The normal diffusion MOS transistor Nch should be a combination of LDD or GDD MOS transistor with double diffusion drain structure, or Pch should be LDD MOS transistor Nch to LD
Use a combination of D MOS transistors. On the other hand, in the structure of the output buffer circuit, Pch is a combination of the normal diffusion MOS transistor Nch and the normal diffusion MOS transistor, or the Pch is a combination of the normal diffusion MOS transistor Nch and the LDDMOS transistor (structure of FIG. 3). To

In such a structure, in order to reduce the electrostatic withstand capacity of the output terminal and to eliminate the low-concentration layer of the double diffused drain, the transistor in the output section has a normal diffused drain structure. In order to avoid the deterioration due to the hot electrons, the gate length of the MOS transistor having the normal diffusion drain structure is set to the double diffusion drain M in the MOS semiconductor device.
The method of making it longer than that of the OS transistor was adopted.
If one long gate length is approximately 2.0 μm, the other is 1.
If it is about 5 μm or about 3.0 μm, it is set to about 1.5 μm.

[0015]

Embodiments of the present invention will be described with reference to FIGS. 9 is a circuit diagram showing an AND circuit composed of a NAND circuit forming a part of an integrated circuit element to which the MOS semiconductor device according to the present invention is applied, that is, a buffer section and an internal circuit, and FIG. 10 forms the NAND circuit of FIG. FIG. 11 is a cross-sectional view of the semiconductor substrate, and FIGS. 11 to 15 are views showing the manufacturing process of the output buffer circuit which is made clear in FIG.
16 is a sectional view of a semiconductor substrate forming another output buffer circuit, and FIG. 17 is a sectional view of a semiconductor substrate provided with an output buffer circuit.

The MOS semiconductor device according to the present invention is shown in FIG.
Further, as shown in FIG. 17, it may be applied to a part of an integrated circuit element, and a double diffused drain MOS transistor is used for a NAND part C forming a part of the integrated circuit element shown in FIG. An output buffer circuit D electrically connected thereto is provided. In the figure, both circuits are separated by a dotted line. In the NAND circuit forming the internal circuit, transistors are provided in the Pch region and the Nch region respectively as shown in FIG. 10, and the A terminal and the B terminal in FIG. 9 are connected to both circuits. In the NAND circuit, an Nch well region and a Pch well region are provided in the semiconductor substrate 1 surrounded by the selective oxide layer 10, and N ⁺ drain regions 4 ′ and 5 ′ are formed in the Nch well region to form a double diffused drain. To do.

Of course, the gate 16 is provided in the Nch well region between the N ⁻ drains 4 and 5. In one Pch well region, a gate 16 is provided between the P ⁺ regions 14 and 15 to form a transistor, which is connected to the output buffer circuit of the next stage. The structure of the output buffer circuit D is shown in FIG.
And shown in FIG.

A manufacturing process of the output buffer circuit shown in FIG. 17 will be described with reference to FIGS. For example, a selective oxide layer 10 having a thickness of 15000 angstroms is provided on the silicon semiconductor substrate 1, and the semiconductor substrate 1 located between them is formed.
A P well region 11 containing B of 10 × ¹⁵ cm ⁻³ is formed on the substrate (see FIG. 11). A gate oxide film 2 having a thickness of about 150 Å is provided on the surface of the P well region 11, a polycrystalline silicon layer 3 is deposited, and then patterned by a patterning process by a conventional photolithography process. The gate oxide film 2 is formed to have a thickness of about 4,000 angstroms and is formed substantially in the center of the gate oxide film 2.

Subsequently, as shown in FIG. 12, after covering the perforated resist pattern 12 which functions as an implantation mask, P is implanted and diffused at 35 KeV to form other drains 4 and 5 as shown in FIG. . Due to the heat load in this step, the side walls A of the polycrystalline silicon layer 3 and the gate oxide film 2 are
Is annealed while being oxidized to cover the polycide layer 6 and a patterning process is performed to obtain the sectional structure of FIG. Of course, the perforated resist pattern 12 is ablated. The P dose amount of the drain regions 4 and 5 is 4 × 10 ¹³ cm ⁻³ .

With the side wall thus formed, as shown in FIG. 14 and FIG. 15, As ⁺ is ion-implanted under the condition of 50 KeV dose amount 5 × 10 ¹⁵ cm ⁻³ and N ^+.
Drain regions 4'and 5'are formed. Then, the LDD or other double diffused drain MOS semiconductor device is completed by annealing in a nitrogen atmosphere. Other drains 4, 5
The concentration of the N ⁺ drain regions 4 ', 5'becomes lower than the concentration of, and the resistance becomes high. 16 and 17, the output buffer circuit electrically connected to the internal circuit as shown in FIGS. 9 and 10 is shown in cross section. FIG.
Is the Nch on the semiconductor substrate 1 surrounded by the selective oxide layer 10.
A transistor having a structure in which a well region and a Pch well region are provided, and a normal diffusion N ⁺ region 16 and a P ⁺ region 17 are provided in each well, and gate regions 18 and 19 are provided between the two regions are shown. Connect to _SS and V _DD .
However, this structure requires the gate length to be wider than that of the structure of FIG.

On the other hand, in the output buffer circuit example of FIG. 17, the double diffused drain MOS semiconductor device and the normal diffused drain MOS semiconductor device are formed monolithically. The difference from the output buffer circuit of FIG. 16 is that the N ⁺ drain regions 4 ′ and 5 ′ are provided in the Nch well region, and the structure is the same as that of FIG.
Since it is the same as 6, the description is omitted.

[0022]

As described above, in the MOS semiconductor device of the present invention, since the electrostatic withstand capability is improved, it can be overcome even if the miniaturization advances and the electric field near the drain becomes strong.

[Brief description of drawings]

FIG. 1 Conventional conventional diffusion structure conventional MOS
It is sectional drawing of a transistor.

FIG. 2 is a cross-sectional view of a conventional MOS transistor having a double diffused drain structure.

FIG. 3 is a cross-sectional view of another conventional MOS transistor having a double diffused drain structure.

FIG. 4 is a cross-sectional view showing a manufacturing process of a conventional LDD type MOS transistor.

FIG. 5 is a cross-sectional view showing the manufacturing process of the LDD type MOS transistor subsequent to FIG. 4;

FIG. 6 is a cross-sectional view showing the manufacturing process of the LDD type MOS transistor, following FIG. 5;

FIG. 7 is a cross-sectional view showing the manufacturing process of the LDD type MOS transistor subsequent to FIG. 6;

FIG. 8 is a cross-sectional view showing the manufacturing process of the LDD type MOS transistor, following FIG. 7;

FIG. 9 is a diagram showing a circuit portion of a MOS semiconductor device according to the present invention.

10 is a diagram showing a cross-sectional structure of the internal circuit shown in FIG.

FIG. 11 is a cross-sectional view of the manufacturing process of the buffer circuit shown in FIG.

12 is a sectional view of the manufacturing process for the output buffer circuit, following FIG. 11; FIG.

FIG. 13 is a cross-sectional view of the manufacturing process of the output buffer circuit, following FIG. 12;

FIG. 14 is a cross-sectional view of the manufacturing process of the output buffer circuit, following FIG. 13;

FIG. 15 is a cross-sectional view showing the manufacturing process of the output buffer circuit, following FIG. 14;

16 is a diagram showing a structure of the output buffer circuit shown in FIG. 9. FIG.

17 is a diagram showing another structure of the output buffer circuit shown in FIG. 9. FIG.

[Explanation of symbols]

1: semiconductor substrate, 2: gate oxide film, 3: polycrystal silicon, 4, 5, 4 ′, 5 ′, 7, 8: drain, 6: polycide, 9: insulator layer, 10: selective oxide layer, 11, 15: well region, 12: resist pattern with holes, 13: pad, 14, 15, 17: P ⁺ region, 16: N ⁺ region, 18, 19: gate.

Claims (6)

[Claims] 1. An internal circuit formed on a semiconductor substrate and an output buffer circuit electrically connected to the internal circuit, wherein a normal diffusion drain MOS transistor and a double diffusion drain MOS transistor formed in the internal circuit are provided in the same channel. MOS type semiconductor device characterized by being shared as. 2. The MOS type semiconductor according to claim 1, wherein only a high concentration ion implantation region for forming a double diffused drain is provided below a contact formed in the double diffused drain MOS type semiconductor device. apparatus. 3. A MOS semiconductor device that shares a normal diffusion drain MOS transistor and a double diffusion drain MOS transistor formed in an internal circuit formed on the semiconductor substrate as the same channel is installed in the input / output circuit section. MOS type semiconductor device. 4. A double diffused drain MOS transistor connected to the internal circuit and its input, and a normal diffused drain MO connected to the output of the output buffer circuit.
A MOS semiconductor device comprising an S transistor. 5. A MOS-type semiconductor device, wherein the gate length of a normal diffusion drain MOS transistor connected to the internal circuit and its input portion is made larger than the minimum gate length of a double diffusion drain MOS transistor. 6. A step of selectively forming an insulator region on a semiconductor substrate, a step of forming a well region of a first conductivity type between the insulator regions, and a gate on the surface of the well region of the first conductivity type. A step of covering the oxide, a step of depositing a polycrystalline silicon layer on the gate oxide, a step of placing a mask while leaving a well region corresponding to the side wall of the polycrystalline silicon layer, and a drain in the well region. A step of forming a region,
Depositing a layer to be a mask for high-concentration ion implantation on the side wall of the polycrystalline silicon layer, forming another drain region in a well region adjacent to the drain region, and other part of the semiconductor substrate And a step of forming an internal circuit therein.