KR19990004675A - Manufacturing Method of Semiconductor Device - Google Patents
Manufacturing Method of Semiconductor Device Download PDFInfo
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- KR19990004675A KR19990004675A KR1019970028811A KR19970028811A KR19990004675A KR 19990004675 A KR19990004675 A KR 19990004675A KR 1019970028811 A KR1019970028811 A KR 1019970028811A KR 19970028811 A KR19970028811 A KR 19970028811A KR 19990004675 A KR19990004675 A KR 19990004675A
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- region
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- mask pattern
- high concentration
- film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 238000000034 method Methods 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 238000002955 isolation Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 229920005591 polysilicon Polymers 0.000 claims abstract description 14
- 238000005468 ion implantation Methods 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims abstract description 4
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 239000002904 solvent Substances 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 239000010408 film Substances 0.000 description 22
- 230000010354 integration Effects 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 접합 영역과 소자 분리막에 걸친 반도체 소자의 접촉창의 형성 방법에 관한 것으로, 상기 목적을 달성하기 위하여 반도체 기판에 트렌치 구조의 소자 분리막과 활성 영역을 형성하는 단계; 상기 소자 분리막의 소정 영역과 그와 인접한 예정된 고농도 이온 주입 영역이 개구되도록, 상기 반도체 기판 상에 마스크 패턴을 형성하는 단계; 전체 구조 상에 고농도 이온 주입 공정을 실시하여 고농도 접합 영역을 형성하는 단계; 상기 마스크 패턴을 제거하고, 상기 고농도 접합 영역 사이의 소정의 활성 영역 상에 게이트 산화막과 게이트 전극층을 차례로 증착하여 게이트 전극을 형성하는 단계; 전체 구조 상에 저농도 이온 주입 공정을 실시하여 상기 게이트 전극과 인접한 하부 활성 영역 및 그와 인접한 상기 고농도 접합 영역에 저농도 LDD 영역을 형성하는 단계; 전체 구조 상에 상기 마스크 패턴을 형성하여 개구된 영역 상의 상기 게이트 산화막 및 불순물을 제거하고, 폴리실리콘막과 금속막을 차례로 증착한 후 급속 고온 열공정을 실시하여 금속 실리사이드층을 형성하는 단계; 및 상기 마스크 패턴을 제거하되 상기 마스크 패턴 상의 상기 폴리실리콘막 및 금속막이 물리적으로 제거되도록 하여, 상기 접합 영역과 상기 소자 분리막의 소정 영역 상에 상기 폴리실리콘막과 금속망으로 이뤄진 접촉창을 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention relates to a method of forming a contact window of a semiconductor device over a junction region and a device isolation film, the method comprising: forming a device isolation film and an active region of a trench structure in a semiconductor substrate to achieve the above object; Forming a mask pattern on the semiconductor substrate to open a predetermined region of the device isolation layer and a predetermined high concentration ion implantation region adjacent thereto; Performing a high concentration ion implantation process on the entire structure to form a high concentration junction region; Removing the mask pattern and sequentially depositing a gate oxide film and a gate electrode layer on a predetermined active region between the high concentration junction regions to form a gate electrode; Performing a low concentration ion implantation process over the entire structure to form a low concentration LDD region in the lower active region adjacent to the gate electrode and the high concentration junction region adjacent thereto; Forming the mask pattern on the entire structure to remove the gate oxide film and impurities on the opened region, depositing a polysilicon film and a metal film in sequence, and then performing a rapid high temperature thermal process to form a metal silicide layer; And removing the mask pattern to physically remove the polysilicon layer and the metal layer on the mask pattern, thereby forming a contact window formed of the polysilicon layer and the metal net on the junction region and a predetermined region of the device isolation layer. Characterized in that it comprises a step.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 반도체 소자의 고집적화를 위하여 금속 배선을 위한 콘택홀의 접촉창의 소정 부분을 소자 분리막 상에 형성시키는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a predetermined portion of a contact window of a contact hole for metal wiring is formed on a device isolation film for high integration of the semiconductor device.
최근 반도체 산업 전반에 걸쳐 서브-마이크론급 소자의 제조 등 반도체 소자의 고집적화가 요구됨에 따라, 각 소자의 패턴들이 보다 미세화되고 있다. 이에 따라, 패턴을 미세화하기 위하여 반도체 소자의 체널과 접합 영역을 포함한 활성 영역 및 소자 분리 영역을 축소시켜 왔다.Recently, as high integration of semiconductor devices is required, such as the manufacture of sub-micron devices throughout the semiconductor industry, patterns of each device are becoming finer. Accordingly, in order to refine the pattern, active regions including channel and junction regions of semiconductor devices and device isolation regions have been reduced.
그러나, 소자 분리 영역의 경우 인접한 소자간의 기생 회로에 의한 열화를 방지하기 위해서는 어느 정도 그 폭을 확보해 주어야 하고, 활성 영역 또한 반도체 소자의 양호한 동작 특성을 위해서는 그 길이 및 폭을 감소시키는데 한계가 있다.However, in the case of device isolation regions, the width must be secured to some extent in order to prevent deterioration due to parasitic circuits between adjacent devices, and the active region also has a limitation in reducing its length and width for good operating characteristics of semiconductor devices. .
특히 종래에는 통상의 방법에 따라 소오스/드레인 접합 영역 상에 금속 배선의 접촉창과 콘택홀을 형성하였기 때문에 접합 영역의 폭을 줄이는데 어려움이 있다.In particular, since the contact window and the contact hole of the metal wiring are formed on the source / drain junction region according to the conventional method, it is difficult to reduce the width of the junction region.
도 1은 종래 기술에 의한 LDD(Lightly Doped Drain) 구조를 갖는 반도체 소자의 단면도로, 간략하게 설명하면 반도체 기판(10)의 소자 분리막(11) 사이에 트랜지스터가 형성되어 있다. 상기 트랜지스터는 반도체 기판(10) 상에 형성된 게이트 산화막(12)과 게이트 전극(15), 상기 게이트 전극의 측면에 형성된 사이드월 스페이서(14) 및 상기 사이드월 스페이서 하부의 반도체 기판에 형성된 저농도 LDD 접합 영역(13b)과 고농도 접합 영역(13a)을 포함한 소오스/드레인으로 이루어져 있다.FIG. 1 is a cross-sectional view of a semiconductor device having a lightly doped drain (LDD) structure according to the related art. In brief, transistors are formed between device isolation layers 11 of a semiconductor substrate 10. The transistor includes a gate oxide film 12 and a gate electrode 15 formed on a semiconductor substrate 10, sidewall spacers 14 formed on side surfaces of the gate electrode, and a low concentration LDD junction formed on a semiconductor substrate under the sidewall spacers. It consists of a source / drain including a region 13b and a high concentration junction region 13a.
그리고, 각 접합 영역 상에 금속 배선을 위하여 금속 실리사이드막으로 형성된 접촉창(17)이 형성되어 있고, 그 상부에 콘택홀(19a)을 통해 금속 배선(19b)이 형성되어 있다. 상기 접촉창은 접합 영역의 금속 배선을 위한 콘택홀 형성시 충분한 공정 마진을 주기 위하여 접합 영역 상에 형성한다.A contact window 17 formed of a metal silicide film is formed on each junction region for the metal wiring, and the metal wiring 19b is formed on the upper portion of the contact window 19a through the contact hole 19a. The contact window is formed on the junction region in order to give sufficient process margin in forming a contact hole for the metallization of the junction region.
그러나, 도 1에 도시된 바와 같이 종래에는 접합 영역의 금속 배선을 위한 접촉창을 접합 영역 상에 형성하기 때문에 접합 영역이 차지하는 활성 영역을 줄이는데 한계가 있다.However, as shown in FIG. 1, since the contact window for the metal wiring of the junction area is conventionally formed on the junction area, there is a limit in reducing the active area occupied by the junction area.
따라서, 본 발명은 반도체 소자의 접합 영역(소오스/드레인) 및 그와 인접한 소자 분리막의 소정 영역 상에 접촉창을 형성함으로써, 접합 영역 상에 형성되는 콘택홀의 공정 마진을 확보함과 동시에 접합 영역이 차지하는 면적도 줄여 고집적화를 이룰 수 있는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention forms a contact window on a junction region (source / drain) of a semiconductor device and a predetermined region of a device isolation film adjacent thereto, thereby ensuring a process margin of a contact hole formed on the junction region and simultaneously forming a junction region. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of achieving high integration by reducing the area to be occupied.
도 1은 종래 기술에 따른 LDD 구조를 갖는 일전도형 트랜지스터를 나타내는 단면도.1 is a cross-sectional view showing a monoconductive transistor having an LDD structure according to the prior art.
도 2A 내지 도 2E는 본 발명의 실시예에 따른 LDD 구조를 갖는 일전도형 트랜지스터의 제조 공정을 나타내는 공정 단면도.2A to 2E are process cross-sectional views illustrating a manufacturing process of a monoconductive transistor having an LDD structure according to an embodiment of the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
10, 20:반도체 기판11, 21:소자 분리막10, 20: semiconductor substrate 11, 21: device isolation membrane
22:마스크 패턴13a, 13b, 23a, 23b:접합 영역22: mask pattern 13a, 13b, 23a, 23b: junction region
12, 14:게이트 산화막15, 25:게이트 전극12, 14: gate oxide film 15, 25: gate electrode
26:폴리실리콘막27:금속막26: polysilicon film 27: metal film
18, 28:절연막19a, 29a:콘택홀18, 28: insulating film 19a, 29a: contact hole
19b, 29b:금속 배선14:사이드월19b, 29b: metal wiring 14: sidewall
17, W:접촉창17, W: contact window
상기 목적을 달성하기 위하여, 본 발명에 따른 반도체 소자의 제조 방법으로, 반도체 기판에 트렌치 구조의 소자 분리막과 활성 영역을 형성하는 단계; 상기 소자 분리막의 소정 영역과 그와 인접한 예정된 고농도 이온 주입 영역이 개구되도록, 상기 반도체 기판 상에 마스크 패턴을 형성하는 단계; 전체 구조 상에 고농도 이온 주입 공정을 실시하여 고농도 접합 영역을 형성하는 단계; 상기 마스크 패턴을 제거하고, 상기 고농도 접합 영역 사이의 소정의 활성 영역 상에 게이트 산화막과 게이트 전극층을 차례로 증착하여 게이트 전극을 형성하는 단계; 전체 구조 상에 저농도 이온 주입 공정을 실시하여 상기 게이트 전극과 인접한 하부 활성 영역 및 그와 인접한 상기 고농도 접합 영역에 저농도 LDD 영역을 형성하는 단계; 전체 구조 상에 상기 마스크 패턴을 형성하여 개구된 영역 상의 상기 게이트 산화막 및 불순물을 제거하고, 폴리실리콘막과 금속막을 차례로 증착한 후 급속 고온 열공정을 실시하여 금속 실리사이드층을 형성하는 단계; 및 상기 마스크 패턴을 제거하되 상기 마스크 패턴 상의 상기 폴리실리콘막 및 금속막이 물리적으로 제거되도록 하여, 상기 접합 영역과 상기 소자 분리막의 소정 영역 상에 상기 폴리실리콘막과 금속막으로 이뤄진 접촉창을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention, comprising: forming a device isolation layer and an active region of a trench structure in a semiconductor substrate; Forming a mask pattern on the semiconductor substrate to open a predetermined region of the device isolation layer and a predetermined high concentration ion implantation region adjacent thereto; Performing a high concentration ion implantation process on the entire structure to form a high concentration junction region; Removing the mask pattern and sequentially depositing a gate oxide film and a gate electrode layer on a predetermined active region between the high concentration junction regions to form a gate electrode; Performing a low concentration ion implantation process over the entire structure to form a low concentration LDD region in the lower active region adjacent to the gate electrode and the high concentration junction region adjacent thereto; Forming the mask pattern on the entire structure to remove the gate oxide film and impurities on the opened region, depositing a polysilicon film and a metal film in sequence, and then performing a rapid high temperature thermal process to form a metal silicide layer; And removing the mask pattern to physically remove the polysilicon layer and the metal layer on the mask pattern, thereby forming a contact window formed of the polysilicon layer and the metal layer on the junction region and the predetermined region of the device isolation layer. Characterized in that it comprises a step.
[실시예]EXAMPLE
이하, 첨부된 도면을 참조로하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 2A에서 2E는 본 발명의 일실시예에 따른 반도체 소자의 제조 방법을 나타낸 공정 단면도로, 여기서는 LDD 구조를 갖는 N형 모스 트랜지스터에 대해서만 간략하게 도시하여 설명하기로 한다.2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. Here, only an N-type MOS transistor having an LDD structure will be briefly described.
먼저, 도 2A에 도시된 바와 같이 P-웰(도시하지 않음)이 형성된 반도체 기판(20)에 트렌치 분리 공정을 이용하여 두꺼운 산화막을 형성한 후 이를 화학적·기계적 연마(CMP)로 평탄화하여 소자 분리막(21)을 형성한다.First, as shown in FIG. 2A, a thick oxide film is formed on a semiconductor substrate 20 having a P-well (not shown) by using a trench isolation process, and then planarized by chemical and mechanical polishing (CMP) to form a device isolation film. 21 is formed.
그 다음, 반도체 기판 상에 후 소오스/드레인 마스크 패턴(22)을 형성하되, 노광 후 형성된 상기 마스크 패턴을 크기는 후속 공정에서 형성될 게이트 전극과 LDD 이온 주입 영역을 합한 크기로, 소정의 접합 영역과 소자 분리막이 노출되도록하여 이온 주입함으로써 반도체 기판(20) 상에 고농도 접합 영역(23a)을 형성한다.Next, a post source / drain mask pattern 22 is formed on the semiconductor substrate, and the size of the mask pattern formed after exposure is the sum of the gate electrode and the LDD ion implantation region to be formed in a subsequent process. And a high concentration junction region 23a is formed on the semiconductor substrate 20 by ion implantation by exposing the device isolation film to be exposed.
여기서, 통상적인 트랜지스터 제조 공정과는 달리 고농도 접합 영역(23a)을 게이트 전극보다 먼저 형성하는 것은, 고농도 접합 영역 형성시 필요한 고온 열처리 공정을 게이트 형성 전에 진행함으로써 저항이 낮은 폴리사이드막을 게이트 전극에 사용할 수 있기 때문이다.Here, unlike the conventional transistor fabrication process, forming the high-concentration junction region 23a before the gate electrode is performed by using a high-temperature heat treatment process necessary for forming the high-concentration junction region before the gate formation to use a low-resistance polyside film for the gate electrode. Because it can.
그 다음, 상기 소오스/드레인 마스크 패턴(22)을 제거하고, 도 2B에서와 같이 반도체 기판 상에 게이트 산화막(24)과 폴리실리콘막 및 폴리사이드막을 형성한 후 사진 식각 공정을 통하여 게이트 전극(25)을 형성하고, 이어서 이온 주입 공정을 통하여 저농도 LDD 접합 영역(23b)을 형성하여 LDD 구조를 만든다.Next, the source / drain mask pattern 22 is removed, the gate oxide layer 24, the polysilicon layer, and the polyside layer are formed on the semiconductor substrate as shown in FIG. 2B, and then the gate electrode 25 is formed through a photolithography process. ), And then a low concentration LDD junction region 23b is formed through an ion implantation process to form an LDD structure.
그리고, 전체 구조 상에 감광막을 도포한 후, 도 2C에서와 같이 상기 소오스/드레인 마스크 패턴(22)을 형성하여 접합 영역(23a) 상에 존재하는 게이트 산화막 및 불순물을 제거한다.After the photoresist is applied over the entire structure, the source / drain mask pattern 22 is formed as shown in FIG. 2C to remove the gate oxide film and the impurities present on the junction region 23a.
계속해서, 저온 스퍼터링법을 사용하여 전체 구조 상에 저온 스퍼터링 방법을 이용하여 폴리실리콘막(26) 및 티타늄과 같은 금속막(27)을 차례로 증착한 후 급속 고온 열처리 공정을 통하여 금속 실리사이드층을 형성한다.Subsequently, the polysilicon film 26 and the metal film 27 such as titanium are sequentially deposited using the low temperature sputtering method over the entire structure using the low temperature sputtering method, and then a metal silicide layer is formed through a rapid high temperature heat treatment process. do.
이어서, 리프트 오프(Lift-Off) 박막 제조 기술을 이용하여 아세톤 등의 감광막 용매로 소오스/드레인 마스크 패턴(22)과 상기 마스크 패턴을 둘러싼 폴리실리콘막(26)과 금속막(27)을 제거하면, 도 2D에 도시된 바와 같이 접합 영역과 일부 소자 분리막 상에 금속 실리사이드층이 있는 접촉창(W)이 형성된다.Subsequently, the source / drain mask pattern 22 and the polysilicon layer 26 and the metal layer 27 surrounding the mask pattern are removed using a photoresist solvent such as acetone using a lift-off thin film manufacturing technology. As shown in FIG. 2D, a contact window W having a metal silicide layer is formed on the junction region and some device isolation layers.
그 다음, 전체 구조 상부에 절연막(28)을 증착하여 화학적·기계적 연마를 통해 평탄화하고, 통상의 공정을 진행하여 콘택홀(29a)을 통하여 금속 배선(29b)을 형성한 것이 도 2E에 도시되어 있다.Next, an insulating film 28 is deposited on top of the entire structure to be planarized by chemical and mechanical polishing, and the metal wire 29b is formed through the contact hole 29a by a normal process. have.
따라서, 상기와 같이 소자 분리막 상의 소정 영역에 접촉창을 형성함으로써 접합 영역이 차지하는 면적을 줄여 고집적화를 이룰 수 있으며, 또한 콘택홀을 형성하는데 종래와 같이 충분한 공정 마진을 확보할 수 있다.Therefore, by forming a contact window in a predetermined region on the device isolation layer as described above, it is possible to achieve a high integration by reducing the area occupied by the junction region, and to secure a sufficient process margin as in the prior art to form a contact hole.
그리고, 상기 공정 진행 과정에서 고농도 접합 영역을 게이트 전극 형성 전에 형성함으로써 게이트 전극에 면저항이 낮은 금속막을 사용할 수 있다.In addition, a metal film having a low sheet resistance may be used for the gate electrode by forming a high concentration junction region before the gate electrode is formed in the process.
이상에서 설명한 바와 같이, 접합 영역과 소자 분리막의 소정 영역에 금속 배선을 위한 접촉창을 형성함으로써 콘택홀을 형성하는데 충분한 공정 마진을 확보할 수 있다. 또한, 반도체 기판에 접합 영역이 차지하는 면적도 줄일 수 있어 반도체 소자의 고집적화를 이룰 수 있다.As described above, by forming a contact window for the metal wiring in the junction region and the predetermined region of the device isolation film, a sufficient process margin for forming the contact hole can be ensured. In addition, the area occupied by the junction region in the semiconductor substrate can also be reduced, resulting in high integration of the semiconductor device.
그리고, 게이트 형성 전에 고농도 접합 영역을 형성시킴으로써 게이트 전극으로 사용되는 금속의 선택폭을 넓힐 수 있다.By forming a high concentration junction region before the gate is formed, the selection range of the metal used as the gate electrode can be widened.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.
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