JPH0628305A - Data transfer controller for multiprocessor system - Google Patents

Abstract

PURPOSE:To prevent the deterioration of the data transfer efficiency of an entire system by optimizing the access operation of a CPU regardless of the open or non-open state of a multibus when accessing to the multibus. CONSTITUTION:The data received from a main storage 11 are transferred to a data transmit stack memory 16a regardless of the state of a multibus 14 and then transferred to the bus 14 via a stack memory control circuit 25 regardless of the state of a CPU 12 when the multibus 14 is opened. Meanwhile the data received from the multibus 14 are transferred to a data receiving stack memory 16b under the control of the circuit 25 regardless of the states of a local bus 13 and the CPU 12. Then, the data received by the memory 16b are written into the storage 11 via the bus 13 after the processing executed by the CPU 12 has completed. Thus, the data can be received with no interruption of the processing under execution of the CPU 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control device of a multiprocessor system for controlling data transfer between a plurality of single processor modules connected by a multibus and having independent functions.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a data transfer control device of a conventional multiprocessor system disclosed in, for example, Japanese Patent Laid-Open No. 1-276355. In the figure,
Reference numeral 11 is a main storage device for storing various data and programs processed by a central processing device, which will be described later, and 12 is the central processing device for sequentially executing the programs stored in the main storage device 11. Reference numeral 13 denotes a local bus that connects the main storage device 11 and the central processing unit 12, and the main storage device 1
An address bus 13a for supplying an address to 1 and a data bus 13b used for data transfer are formed. Further, 14 is a multi-bus capable of indirectly accessing the main memory 11, and a multi-address bus 14a used for transferring an address for accessing a buffer memory which will be described later and a multi-address bus used for data transfer. It is formed by the multi-data bus 14b.

Reference numeral 15 is a main storage device 11 connected to the multi-bus 14 for transferring data to another single processor module and an input / output device (both not shown).
It is a data register for temporarily holding the data read from the device via the local bus 13. Reference numeral 16 sequentially stores the data held in the data register 15 in response to a load timing signal 17 from the central processing unit 12, and stores the stored data in a storage order in accordance with a read timing signal 18 from the central processing unit 12. 14 and also outputs a memory full signal 19 to the central processing unit 12 when the data storage capacity becomes full.
FO) type stack memory.

Reference numeral 20 is for absorbing a difference in transfer rate, event occurrence time, etc. existing between each other at the time of data transfer with a device such as another single processor module or an input / output device connected to the multi-bus 14. And 21 is a multi-bus address register for holding the address of the buffer storage device 20 designated by the central processing unit 12.

Next, the operation will be described. When a request is issued from the central processing unit 12 to the main storage device 11 to transfer data to a device such as another single processor module or an input / output device connected to the multibus 14,
First, the storage address in the main memory 11 of the data to be transferred is output from the central processing unit 12 to the address bus 13a of the local bus 13. The main memory device 11 outputs the data designated by this address to the data bus 13b. The data on the data bus 13b is transferred to the data register 15 and held in the data register 15 by a latch timing signal from the central processing unit 12, for example. At this time, the central processing unit 12 uses the stack memory 1
If the active memory full signal 19 is not output from 6, the load timing signal 17 is output to the stack memory 16, and the data held in the data register 15 is stacked in the stack memory 16.

The central processing unit 12 repeats the above operation for the required data transfer while sequentially switching the addresses, and then starts the next program processing if the multi-bus 14 is not opened. Here, if stack memory 1
The data storage capacity of 6 is smaller than the required data transfer capacity, the stack memory 16 becomes full during a series of data read from the main storage device 11, and the memory full signal 19 is output from the stack memory 16. In this case, the central processing unit 12 immediately stops the series of data read operations, and the memory full signal 19 output by the stack memory 16
Will be in a waiting state until becomes unwilling.

The above is the case where there is a data transfer request while the multibus 14 is not released. The multibus 14 is released and the central processing unit 12 is executing the program processing or an arbitrary instruction in the processing. Is terminated, or when the multibus 14 is released during the above waiting state, the central processing unit 12 causes the buffer storage unit 20 to
The multi-bus address for designating the address is set in the multi-address register 21, and the read timing signal 18 is output to the stack memory 16. The stack memory 16 receiving this read timing signal 18 outputs the oldest valid data at that time in synchronization with the read timing signal 18 and sends it to the multi-data bus 14b of the multi-bus 14. At that time, the multi-bus address set in the multi-bus address register 21 is also simultaneously transferred to the multi-address bus 14a.
Sent to. As a result, the data transmitted onto the multi-data bus 14b is written in the area of the buffer storage device 20 designated by the multi-bus address on the multi-address bus 14a.

[0008]

Since the data transfer control device of the conventional multiprocessor system is constructed as described above, the main memory device 11 is opened every time the multibus 14 is released and the data transfer is completed once. The multibus address must be set in the multibus address register 21, and the sending of the address to the multibus 14 for data is inefficient, and another single processor connected to the multibus 14 When the data is sent from the module, the central processing unit 12 has to temporarily stop the program being executed and read the data on the multi-bus 14 into the main storage device 11. Not only decreases, but when data is transferred to another single processor module connected to the multi-bus 14, For storing data in the buffer storage device 20 connected on the scan 14, a multi-bus 14 2
There is a problem that it is necessary to make heavy access, the operating rate of the multibus 14 is reduced, and the efficiency of the entire multiprocessor system is reduced.

The present invention has been made to solve the above problems, and when accessing a multibus, the access operation of the central processing unit is optimized regardless of whether the multibus is open or not open. It is an object of the present invention to provide a data transfer control device for a multi-bus system that prevents a decrease in the data transfer efficiency of the entire multi-processor system mainly composed of the multi-bus.

[0010]

In a data transfer control device of a multiprocessor system according to a first aspect of the present invention, data output from a main storage device is stored between a local bus and a multibus. A data transmission stack memory, an address stack memory in which address information of a single processor module is stored, a data reception stack memory in which reception data from the single processor module is stored, a stack memory control circuit for controlling reading / writing of these, And a multi-bus interface section for controlling the interface between each of the stack memories and the multi-bus.

The data transfer control device of the multiprocessor system according to the second aspect of the present invention directly transfers data between the main storage device and each stack memory without the intervention of the central processing unit. is there.

[0012]

In the data transfer control device of the multiprocessor system according to the first aspect of the present invention, the data from the main storage device is transferred to the data transmission stack memory regardless of the state of the multibus, and the data is transferred to the multibus. When the memory is released, the stack memory control circuit transfers the data to the multi-bus regardless of the central processing unit, and the data from the multi-bus is controlled by the stack memory control circuit regardless of the state of the local bus or the central processing unit. Data is transferred to the data reception stack memory, and after the processing being executed by the central processing unit is completed, the data reception stack memory is written to the main storage device via the local bus, thereby causing the central processing unit to interrupt the processing being executed. Data can be received without any regard, regardless of the data transfer direction or the operating status of the transfer target. You can exchange chromatography data, allowing the construction of utilization and high multibus data transfer efficiency of a multiprocessor system of the central processing unit.

In the data transfer control device of the multiprocessor system according to the second aspect of the present invention, the data transfer between the main memory device and each stack memory is directly performed without the intervention of the central processing unit. To realize a data transfer control device of a multiprocessor system capable of further reducing the processing load of the central processing unit.

[0014]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the invention described in claim 1. In the figure, 11 is a main memory, and 12
2 is a central processing unit, 13 is a local bus, 13a is its address bus, 13b is also a data bus, 14 is a multi-bus, 14a is its multi-address bus, and 14b is also a multi-data bus. Since these are the same as or equivalent to those of the conventional ones, detailed description thereof will be omitted.

Reference numeral 16a denotes a data transmission stack memory for holding the data to be transmitted to the multi-bus 14 output from the main memory device 11 or the central processing unit 12 in the FIFO system, 1
6b receives the data sent from the multi-bus 14 into the FIF
It is a data reception stack memory that is held in the O system.
Reference numeral 2 is an address stack memory for holding a multi-bus address indicating a transfer destination of the data held in the data transmission stack memory 16a by the FIFO method. Reference numeral 19a is a memory full signal output from the address stack memory 22 when the data storage capacity of the address stack memory 22 is full, and 19b is the data when the data storage capacity of the data transmission stack memory 16a is full. 19c is a data reception stack memory 1 which is a memory full signal output from the transmission stack memory 16a.
6b is a memory full signal output from the data receiving stack memory 16b when the data storage capacity of 6b is full. Further, 23a is the address stack memory 22.
Address stack memory control signal for invoking the read operation and load operation of the data transmission stack memory 1
6a is a data transmission stack memory control signal for invoking a read operation and a load operation, and 23c is a data reception stack memory control signal for invoking a read operation and a load operation for the data reception stack memory 16b.

Reference numeral 25 is a stack memory control circuit for controlling the data transmission stack memory 16a, the data reception stack memory 16b, and the address stack memory 22 in accordance with the settings and commands of the central processing unit 11, and 26 is each of these data transmission stack memories. 16 a, data reception stack memory 16 b, address stack memory 22, and a multi-bus interface unit that controls the timing of the multi-bus 14. Reference numeral 24 is a control signal transmitted and received between the stack memory control circuit 25 and the multi-bus interface unit 26 for control.

Reference numerals 10a, 10b and 10c each have an independent function, and the main storage device 11 and the central processing unit 1 are provided.
2, local bus 13, data transmission stack memory 16
a, a data reception stack memory 16b, an address stack memory 22, a stack memory control circuit 25, a multi-bus interface unit 26, and the like, which are connected to each other by a multi-bus 14.

Next, the operation will be described. Now, it is assumed that the central processing unit 12 in the single processor module 10a issues a request to the main storage device 11 to transfer data to the other single processor modules 10b and 10c connected to the multibus 14. . In that case, the central processing unit 12 first sets the storage address of the data to be transferred in the main storage device 11 to the address bus 13 of the local bus 13.
Output to a. The main memory device 11 uses this address bus 13
The data designated by the address on a is output to the data bus 13b. The data on the data bus 13b is transferred to the data transmission stack memory 16a, and the data transmission stack memory control signal 23b output from the stack memory control circuit 25 causes the data transmission stack memory 1 to operate.
6a. Further, the central processing unit 12 outputs multibus address information indicating the transmission destination of the data held in the data transmission stack memory 16a from the main storage device 11 to the address stack memory 22, and the multibus address information is stored in the stack memory control circuit. It is held in the address stack memory 22 by the address stack memory control signal 23 a output by 25.

The above operation is continued until the predetermined data size or the memory full signals 19a and 19b output from the data transmission stack memory 16a or the address stack memory 22 become significant. When the memory full signal 19a or 19b becomes significant, the central processing unit 12 temporarily suspends the series of processes and executes other program processes. This memory full signal 19
If a and 19b become unwilling, the above-mentioned processing which has been temporarily suspended is continued.

Next, the multi-bus interface section 26
Confirms that the multibus 14 has been released,
The stack memory control circuit 2 is controlled by the control signal 24.
Notify 5. As a result, the stack memory control circuit 25
Outputs the address stack memory control signal 23a and the data transmission stack memory control signal 23b, and outputs the address stack memory 22 and the data transmission stack memory 16a.
Outputs the held multi-bus address information and data to the multi-bus interface unit 26. The multibus interface unit 26 receives the multibus address information received from the address stack memory 22 in accordance with the timing of the multibus 14
4a, the data received from the data transmission stack memory 16a is output to the multi-data bus 14b. As a result, a series of data transmission / transfer processing is completed.

When data is sent from the other single processor modules 10b and 10c connected to the multi-bus 14, first, the multi-bus interface unit 26 is the access target of its own single processor module 10a. Recognize this, and inform the stack memory control circuit 25 of this. The stack memory control circuit 25 outputs the data reception stack memory control signal 23c to the data reception stack memory 16b, and the data reception stack memory 16b which receives the data reception stack memory control signal 23c receives the data on the multi-data bus 14b via the multi-bus interface unit 26. . After that, when the stack memory control circuit 25 confirms that the data reception stack memory 16b has received the data to some extent, it notifies the central processing unit 12 that the data has been received. The central processing unit 12 recognizes that data has been received from the multi-bus 14, reads the data from the data reception stack memory 16b via the local bus 13, and transfers this data to a predetermined area of the main storage device 11. Store. As a result, a series of data reception transfer processing is completed.

Example 2. In the above embodiment, the storage and reading of data in the data transmission stack memory 16a, the data reception stack memory 16b, and the address stack memory 22 are performed by the stack memory control that operates according to the settings and instructions of the central processing unit 12. Although the case where the circuit 25 executes is shown, these data transfers may be realized by using direct memory access (DMA), and the same effect as that of the above-described embodiment is obtained.

[0023]

As described above, according to the first aspect of the present invention, data from the main storage device to the data transmission stack memory is transferred to the data transmission stack memory regardless of the state of the multibus. Under the control of the stack memory control circuit, the multi-bus is sent to the multi-bus independently of the central processing unit when the multi-bus is released.
The data from the multi-bus is transferred to the data receiving stack memory under the control of the stack memory control circuit regardless of the status of the local bus and the central processing unit, and when the central processing unit finishes the processing being executed. Since it is configured to write to the main storage device via the local bus, the central processing unit can execute the data transmission processing regardless of the state of the multibus, and output the data from the data transmission stack memory to the multibus. The central processing unit can execute other program processing even during the operation to increase the utilization efficiency, and the data transmitted from the multi-bus can be received by the stack memory control circuit. Since it is stored in, the central processing unit does not need to intervene in the handshake with the multi-bus, Since the execution program of the central processing unit is not interrupted in response to an access request from the bus, it is possible not only to eliminate the overhead required up to now, but also another single processor module connected to the multibus. By performing the timing control with and by the multiprocessor provided in its own single processor module, it is possible to eliminate the buffer device on the multibus that has been used conventionally, and the double access of the multibus is also unnecessary. The data transfer efficiency of the multi-bus itself can be increased, and thus the operating rate of the entire multi-processor system can be increased.

According to the second aspect of the invention, since the data transfer is directly performed between the main memory device and each stack memory, the processing load of the central processing unit can be further reduced. The data transfer control device of the multiprocessor system can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a data transfer control device of a conventional multiprocessor system.

[Explanation of symbols]

 10a to 10c Single processor module 11 Main storage device 12 Central processing unit 13 Local bus 14 Multibus 16a Data transmission stack memory 16b Data reception stack memory 22 Address stack memory 25 Stack memory control circuit 26 Multibus interface unit

Claims (2)

[Claims] 1. A multiprocessor capable of transferring data between a plurality of single processor modules each having a central processing unit and a main memory unit, each of which is connected to a local bus, and having independent functions. In a multiprocessor system connected by a bus, the data in the main storage device is transmitted to another single processor module connected to the multibus, and the data from the other single processor module is transmitted. In a data transfer control device of a multiprocessor system for receiving and storing in the main memory device, a data transmission stack memory for temporarily storing data output from the main memory device in order in accordance with a request from the central processing unit. And temporarily store address information of the single processor module connected to the multi-bus. Controls read / write of the address stack memory to be stored, the data reception stack memory that temporarily stores the reception data from the other single processor module, and the data transmission stack memory, the address stack memory, and the data reception stack memory. A data transfer control of a multiprocessor system comprising a stack memory control circuit, a data transmission stack memory, an address stack memory, and a data reception stack memory and a multibus interface unit that controls the interface with the multibus. apparatus. 2. The data transfer between the main memory and the data transmission stack memory, the address stack memory, and the data reception stack memory is performed directly without the intervention of the central processing unit. Item 2. A data transfer control device for a multiprocessor system according to Item 1.