JPH06276063A - Latch circuit - Google Patents

Abstract

PURPOSE:To obtain the latch circuit with low power consumption which suppresses unnecessary power consumption due to the operation of the logic circuit in an input stage when the operation frequency of an input signal is lower than the operation frequency of an enable signal. CONSTITUTION:An exclusive OR gate 10 which compares the state of the input signal to a data input terminal 1 with the state of the output signal from an output terminal 3 is added and when the enable signal 2a varies, the output of the exclusive OR gate 10 is connected to the input terminals of three-input NAND gates 6a and 7a so that neither of the three-input NAND gates 6a and 7a operates on condition that the input signal 1a is in the same state as that before the enable signal 2a varies.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a latch circuit, and more particularly to a latch circuit capable of reducing power consumption.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing an example of a conventional latch circuit. In the figure, 40 is an RS flip-flop section and 41 is a data input section. Further, 1 is a data input terminal, 2 is an enable signal input terminal, 3 is an output terminal, 4 is an inverting output terminal, 5 is an inverter gate, and 1
a to 4a are signal names of the respective terminals. 6-9 is 2
The two-input NAND gates 8 and 9 are input NAND gates.
The flip-flop unit 40 is configured to include the 2-input NAND 6,
7 has one input connected to the enable signal input terminal 2 and the other input connected to the data input terminal 1 respectively.
Is connected to the data input terminal 1 via the inverter 5. FIG. 6 is a timing chart showing the operation of the latch circuit of FIG.

Next, the operation will be described. In FIG. 5, while the input signal 2a (E) is at "H level", this latch circuit is in the through state, and the input signal 1a (D) input from the data input terminal 1 is output from the output terminal 3 to the output signal 3a (Q ), And from the output terminal 4, data obtained by inverting the signal D input from the data input terminal 1 by the inverter 5 is output as the output signal 4a (QC).

On the other hand, while the input signal E of the input signal 2a is at "L level", this latch circuit is in the holding state, and the output terminal 3 outputs the signal regardless of the state (level) of the input signal D of the input terminal 1. Output signal 3a
It continues to output as (Q), and continues to output the data held until then as the output signal 4a (QC) from the inverting output terminal 4. This series of operations can be summarized as shown in the timing chart of FIG.

As described above, the latch circuit temporarily stores 1-bit information, but in the above configuration, since the reset input of the flip-flop section 40 is created from the input signal D via the inverter 5, it is set. The signal and the reset signal do not become "L level" at the same time, and the output does not become unstable.

[0006]

Since the conventional latch circuit is configured as described above, the frequency of the input signal D input to the input terminal 1 is low and the level of the constant state is maintained during the period. Although the signal appearing at the output terminal does not change regardless of the state of the enable signal, and therefore the change of the enable signal during this period is not necessary, as shown in FIG. 7, the input signal E of the enable signal input terminal 2 is changed. Changes, either of the two-input NAND gates 6 or 7 operates, and there is a problem in that unnecessary power is consumed.

The present invention has been made to solve the above problems, and is a two-input NAND which constitutes a data input section during a period in which the input signal D maintains a constant state.
An object is to obtain a latch circuit that can suppress unnecessary power consumption due to the operation of the circuit.

[0008]

In a latch circuit according to the present invention, a data input section receives input data and a control signal as a first signal.
And a 3-input NAND gate serving as a second input, and comparing the data output from the data holding unit with the input data.
A data comparison control means for outputting a predetermined comparison result signal to the third input of the input NAND gate to stop the operation of the gate is provided.

[0009]

According to the present invention, the states of the input signal and the output signal are compared by the data comparison control means, and when these states are the same, the 3-input NAN forming the data input section.
Since the D gate is configured not to operate, it is possible to prevent the logic circuit forming the data input unit from operating unless the input data changes from the state before the enable signal changes.

[0010]

EXAMPLES Example 1. The latch circuit according to the first embodiment of the present invention will be described below with reference to the drawings. In FIG.
10 indicates the state of the input signal D of the input terminal 1 and the output terminal 3
The exclusive OR gates (exclusive OR circuits) 6a and 7a for comparing the output signal Q of the enable signal input terminal 2 with the state of the output signal Q of
When the input signal D of the data input terminal 1 matches the state before the change of the input signal E, the 3-input N provided in place of the conventional 2-input NAND gates 6 and 7 does not operate.
It is an AND gate, and the output of the exclusive OR gate 10 is connected to its 1 input terminal.

Next, the operation will be described. In FIG. 1, while the input signal E of the enable signal input terminal 2 is "H level", this latch circuit is in the through state, the input signal D input from the data input terminal 1 is output from the output terminal 3, and the output terminal 3 is output. The data output from 4 is the inverted data of the input signal D. On the other hand, enable signal input terminal 2
While the input signal E of is at "L level", this latch circuit is in the holding state, and the output signal Q is held from the output terminal 3 and is output regardless of the state of the input signal D of the data input terminal 1. Output signal QC from the inverting output terminal 4.
Hold and continue to output this. This series of operations can be summarized as shown in the timing chart of FIG. 2, which is functionally the same as the conventional latch circuit.

By the way, as shown in FIG. 3, when there is a period in which the frequency of the input signal D is low and the level of the enable signal E is changed but the level of the data input signal D is not changed, for example, Output signal D of output terminal 3
Enable signal E during the period when is at "L level"
When the exclusive OR gate 10 detects that there is no change in the input signal D input to the data input terminal 1 even when the level of is changed from "H level" to "L level", the 3-input NAND "L level" is output to the gates 6a and 7a, and as a result, the 3-input NAND gate 6
The outputs of a and 7a remain at "H level" and do not change,
Unnecessary power consumption can be suppressed.

As described above, according to this embodiment, the input terminal 1
An exclusive OR gate (exclusive OR circuit) 10 is added to compare the state of the input signal D of the input signal D with the state of the output signal Q of the output terminal 3. 2-input NAND to prevent the circuit from operating
Since three-input NAND gates 6a and 7a are used instead of the gates and the output of the exclusive OR gate 10 is connected as one of these inputs, the input signal D of the data signal input terminal 1 and the output of the output terminal 3 are output. Even if the state of the signal Q is the same, unless the input signal D and the output signal Q do not match, the logic circuit of the data input section does not operate, and the power consumption can be reduced.

Example 2. Next, a latch circuit according to a second embodiment of the present invention will be described with reference to the drawings. In the above embodiment, the exclusive OR gate 10 is used as a means for comparing the levels of the input signal D and the output signal Q, but in this embodiment, as shown in FIG. 4, the exclusive OR gate is replaced with an exclusive OR gate. This is a configuration in which the crucible NOR gate 11 is used.

In this case, the input signal to the exclusive NOR gate 11 is the input signal D and the output signal QC, and by doing so, the same effect as that of the first embodiment can be obtained.

In the above embodiment, an example of the NAND type latch circuit is shown, but the same effect can be obtained with the same configuration even with the NOR type latch circuit.

Further, although the example of the latch circuit is shown in the above-mentioned embodiment, the same effect can be obtained with a similar configuration even with a flip-flop.

[0018]

As described above, according to the latch circuit of the present invention, the states of the input signal and the output signal are compared by the data comparison control means, and when these states are the same,
Since the 3-input NAND gate forming the data input section is configured not to operate, it is possible to suppress unnecessary power consumption when the operating frequency of the input signal is lower than the operating frequency of the enable signal. Therefore, there is an effect that a latch circuit with low power consumption can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a latch circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the latch circuit.

FIG. 3 is a timing diagram showing an operation of an internal signal of the latch circuit.

FIG. 4 is a circuit diagram showing a configuration of a latch circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a conventional latch circuit.

FIG. 6 is a timing diagram showing an operation of a conventional latch circuit.

FIG. 7 is a timing diagram showing an operation of an internal signal of a conventional latch circuit.

[Explanation of symbols]

 1 Data Input Terminal 2 Enable Signal Input Terminal 3 Output Terminal 4 Inverted Output Terminal 5 Inverter 6a 3 Input NAND Gate 7a 3 Input NAND Gate 8 2 Input NAND Gate 9 2 Input NAND Gate 10 Exclusive OR Gate 11 Exclusive NOR Gate

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[Procedure amendment]

[Submission date] August 17, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction content]

[0006]

Since the conventional latch circuit is configured as described above, the frequency of the input signal D input to the input terminal 1 is low and the level of the constant state is maintained during the period. The signal appearing at the output terminal does not change regardless of the state of the enable signal, and as shown in FIG. 7, when the input signal E of the enable signal input terminal 2 changes, either the 2-input NAND gate 6 or 7 operates. However, there is a problem in that unnecessary power is consumed.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

As described above, according to this embodiment, the input terminal 1
An exclusive OR gate (exclusive OR circuit) 10 is added to compare the state of the input signal D of FIG. 1 with the state of the output signal Q of the output terminal 3, and when the logic of the data input section is unnecessary. 2-input NAND to prevent the circuit from operating
Using 3-input NAND gates 6a and 7a in place of the gate, from the output of the exclusive OR gate 10 so as to connect as these 1 input, enable signals
As long as the input signal D and the output signal Q do not match even if E changes, the logic circuit of the data input section does not operate and power consumption can be reduced.

Claims (3)

[Claims] 1. A latch circuit comprising a data input section for controlling the output of input data based on a control signal, and a data holding section for holding the data output from the data input section. The data input unit is configured by using a 3-input NAND gate having the input data and the control signal as the first and second inputs, and the data output from the data holding unit is compared with the input data. A latch circuit comprising data comparison control means for outputting a predetermined comparison result signal to the third input of the 3-input NAND gate to stop the operation of the gate when these data match. 2. The latch circuit according to claim 1, wherein an exclusive OR gate is used as the data comparison control means. 3. The latch circuit according to claim 1, wherein an exclusive NOR gate is used as the data comparison control means.