JPH10290143A - Low power consumption type storage circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the storage circuit for a flip-flop or the like in a semiconductor integrated circuit where the operation of a clock generating gate in the flip-flop is suppressed when a storage content and data to be entered newly are identical so as to reduce dynamic power consumption. SOLUTION: The circuit is provided with an EOR gate 4 that compares an output of a flip-flop circuit 1 with new data input and with an AND gate 5 that controls whether or not a clock signal is given to the flip-flop circuit 1 based on an output of the EOR gate 4, and only when the content already stored and data to be entered newly are identical, the clock input is invalidated and only when both the data are dissident, the clock input is validated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage circuit in a semiconductor integrated circuit, and more particularly to a circuit such as a flip-flop for storing data to be stored one by one with a clock signal, in which the stored content and the newly stored data are stored. The present invention relates to a storage circuit in a semiconductor integrated circuit which suppresses the operation of a circuit portion operated by a clock signal in the storage circuit when the contents are the same data, and reduces power consumption in the storage circuit.

[0002]

2. Description of the Related Art As an example of a memory circuit in a conventional semiconductor integrated circuit, see page 19 of "Principles of CMOS VLSI Design" published by Maruzen Co., Ltd. on August 30, 1988.
A circuit example of a CMOS flip-flop is shown.

The present flip-flop will be described with reference to FIG. 3, Table 2, and FIG. 3 shows a circuit diagram of the flip-flop, Table 2 shows a truth table of the present flip-flop, and FIG. 4 shows an operation time chart.

In FIG. 3, the present flip-flop circuit 1
Is roughly composed of three parts. The first is a portion for generating a positive signal and a negative signal of a clock signal composed of the inverters 11 and 12. The second is a part for controlling whether or not the input data signal is transferred to the storage unit by the inverter 21 and the complementary switch circuit 22 including the PMOS transistor and the NMOS transistor. Third, a storage unit in which a loop circuit is formed by the inverters 31 and 32 and the complementary switch circuit 33.

[0005]

[Table 2]

As is clear from Table 2 and FIG. 4, when the clock signal is in an off state (Low state), a loop circuit of the storage unit is formed and held, and the clock signal is turned on. At the time of (High state), the input data signal is transferred to the storage unit, and when the clock signal is turned off, a loop of the storage unit is formed and the input data is held.

Therefore, in this circuit, the inverter 11,
The circuits 12 and 12 are circuits that constantly operate every clock input irrespective of the value of the held data and input data.

[0008]

In the above prior art, the clock signal generator in the storage circuit always operates every time the clock signal changes, and the power consumption of the clock signal generator is reduced. There was no regard for what to do.

According to the present invention, when a very simple circuit is added to a memory circuit, and the content currently held by the memory circuit is the same as data to be fetched next, a clock signal in the memory circuit is used. It is an object of the present invention to provide a storage circuit that suppresses the operation of the creation unit and reduces power consumed by the clock creation unit.

[0010]

In order to achieve the above object, according to the method of the present invention, there is provided a circuit for comparing the currently stored contents with the contents of input data to be newly acquired. Further, control data for determining whether or not the clock signal is propagated to the storage circuit is provided according to the comparison result. If the storage content currently held is different from the content of the input data to be newly acquired (a mismatch Only when the clock signal generation circuit operates.

[0011] The comparison circuit comprises:
This is a circuit for comparing data to be newly taken in and can be generally realized by an exclusive OR gate (EOR). The output of this comparison circuit outputs a logical value "1" when the data does not match.

On the other hand, the clock input signal is controlled by the output result of the comparison circuit, and works so as to validate the clock input to the storage circuit only when the comparison result is a logical value "1". Generally, this control circuit is achieved by an AND gate.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. 1, Table 1 and FIG.

FIG. 1 is a circuit diagram of an embodiment of the present invention.
It comprises a flip-flop circuit 1, an exclusive OR gate (hereinafter abbreviated as EOR) 4, and an AND gate (hereinafter abbreviated as AND) 5.

The flip-flop circuit 1 is the same as that shown in FIG. The EOR gate 4 receives the currently held data 'Q' and the data 'D' to be newly acquired, and outputs a comparison result (DEOR) of the two data. The output of the EOR gate 4 is the clock input (C
K) is ANDed with the AND gate 5, and becomes the clock input (CKA) of the flip-flop circuit 1.

The operation of this circuit will be described with reference to Table 1 and FIG. Note that the operation in the flip-flop 1 has been described in the section of the prior art and will not be described here.

[0017]

[Table 1]

The information (Qn- ₁ ) currently held is Lo.
w, and the data “D” to be newly acquired is also Lo.
At the time of w, the output (DEOR) of the EOR gate 4 becomes a logical value “0”. At this time, the clock (CK) has the logical value “1”.
(High), the AND gate 5 does not hold and the AN
The output (CKA) of the D gate 5 remains at the logical value “0”, the inverters 11 and 12 of the clock generation unit in the flip-flop circuit 1 do not operate, and the flip-flop circuit 1
Is kept Low.

Next, from the above-mentioned state, the data input D becomes High.
At time h, the output (DEOR) of the EOR gate 4 becomes a logical value “1” (High), and when the clock (CK) becomes a logical value “1”, the AND gate 5 is established, and the output (CKA) of the AND gate 5 is established. (CK) propagates through the clock.
As a result, the flip-flop circuit 1 takes in the High level of the data input 'D' and propagates it to Q. Thereafter, the falling of the clock (CK) stores and holds the High level of the data input 'D'.

Next, from the above state, the data input 'D' becomes H
Even if the clock (CK) becomes the logical value “1” while the signal remains at the high level, the content currently held and the content of the data input “D” are the same, and the output of the EOR gate 4 becomes the logical value “0”. '
And the output (CKA) of the AND gate 5 does not propagate the clock input (CK), so that the inverters 11 and 12 do not operate, and the flip-flop circuit 1
The High level is maintained.

Next, from the above-mentioned state, the data input 'D' becomes L
When it becomes ow, the output (DEOR) of the EOR gate 4 becomes a logical value “1”, and when the clock (CK) becomes a logical value “1”, the AND gate 5 is established, and the clock (CKA) is output to the output (CKA) of the AND gate 5 CK) propagates. As a result, the flip-flop circuit 1 outputs the low level of the data input 'D'.
Capture level and propagate to Q. After that, the low level of the data input 'D' is stored and held by the falling edge of the clock (CK).

As described above, in the storage circuit of the present invention, the clock generation inverter gates 11 and 12 are used only when the content currently held is different from new input data.
Operates, and when the content currently held and the new input data are the same, even if the clock (CK) changes, the change is not propagated to the inverter gates 11 and 12.

In this embodiment, the circuit in which the AND gate 5 for controlling the input of the clock is provided separately from the flip-flop circuit 1 is shown. However, the clock generation inverter gate 11 in the flip-flop circuit 1 is replaced by a NAND gate. Thus, it is possible to provide a circuit that reduces the amount of delay of a clock signal and also reduces the number of transistors used. This embodiment is shown in FIG. It is clear to those skilled in the art that the circuit shown in FIG. 5 has the same function as the circuit shown in FIG. still,
The data input 'D' in FIG. 5 is first received by an inverter gate, and then connected to an ENOR gate and a complementary switch circuit. The circuit is connected to the source gate (not shown) of the data input 'D' This is to reduce the amount of delay between storage circuits.

[0024]

According to the present invention, the operation of the clock signal generation unit in the storage circuit (flip-flop) can be determined by simply adding a simple circuit to the data currently held and the data to be newly captured. Is operated only when the data is different, and when the data currently held and the data to be newly acquired are the same (new and old data are the same, the acquisition operation is unnecessary), the operation is suppressed. This has the effect of reducing dynamic power consumption in the clock signal generator in the storage circuit.

In general, a clock signal operates steadily every cycle. However, since the change of the data signal is small, the effect of reducing the power consumption in the clock signal generation unit is large.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a time chart showing an operation in the circuit of FIG. 1 which is one embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of the related art.

FIG. 4 is a time chart illustrating an operation in a circuit of the related art.

FIG. 5 is a circuit diagram showing another embodiment of the present invention.

[Explanation of symbols]

1 ... Flip-flop circuit, 11, 12, 21, 31,
32 ... Inverter gate, 22, 23 ... Complementary switch circuit, 4 ... Exclusive OR gate, 5 ... AND gate

Claims (1)

[Claims] 1. A storage circuit in a semiconductor integrated circuit for taking in and holding data in response to a clock signal, a comparison circuit of currently held data and data to be newly taken in, and a clock signal based on the comparison result. A storage circuit comprising a circuit for controlling validity and invalidity of a clock signal, wherein when the comparison result matches, the clock signal is invalidated, and only when the comparison result does not match, the clock signal is validated. .