JPH0793281A - Key-on wakeup mode setting circuit - Google Patents

Abstract

PURPOSE:To automatically validize key-on wakeup by writing a clock signal and data for stopping an oscilator into a register for clock signal control when validizing interruption. CONSTITUTION:By writing '1' in a register 20 for automatic key-on wakeup setting, a pull-up transistor 11 is turned on and at the same time, '0' is written in a direction register 5. Therefore, a P channel transistor 12 is turned on, and pull-up is turned to a valid state. On the other hand, when the clock signal and the data for stopping the osicllator are written in a register 22 for clock signal control, the osicllator is stopped and the clock signal is stopped. Further, when an 'L' level to hit an 'H' level outputted from the pull-up transistor 11 is inputted to an external input/output terminal 3 by a key input for validizing the interruption, the 'L' of an interrupt signal 19 as a key-on wakeup interrupting input is outputted through a Schmift circuit 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a key-on wake-up mode setting circuit for restarting the operation of a one-chip microcomputer or the like from a stop state or a wait state by interruption by a key input.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a conventional key-on wakeup function circuit. In the figure, 1 is a power supply (hereinafter referred to as Vcc) of a semiconductor integrated circuit, 2 is a ground,
Reference numeral 3 is an external input / output terminal, 4 is a data bus, and 5 is a register (hereinafter referred to as a direction register) that determines the input / output of the I / O port.

Further, 6 is a register for storing data to be output to the I / O port (hereinafter referred to as port latch), 7
Is a register (hereinafter referred to as a pull register) that determines whether to enable or disable the pull-up transistor.

Reference numeral 8 indicates the contents of the port latch 6 on the data bus 4
To output data to the data bus 4 when the I / O port is in an input state, 10 is a Schmitt circuit for key-on wakeup, 11 is a P-channel transistor for pullup (hereinafter , Called a pull-up transistor).

Further, 12 is a P-channel transistor controlled so that pull-up is effective only when the I / O port is set to input, and 13 is for outputting data to the external input / output terminal 3. P-channel transistor,
Reference numeral 14 is an N-channel transistor for outputting data to the external input / output terminal 3, and 15 is a NAND gate for controlling external output.

Further, 16 is a NOR gate for controlling an external output, 17 is an inverter for controlling the external output, 18 is an inverter for controlling the pull-up transistor 18, and 19 is a key-on wake-up interrupt input. There is.

The pull-up transistor 11 has an ON resistance of several tens of kΩ and the P-channel transistor 12 has an ON resistance sufficiently smaller than that of the pull-up transistor 11. When the interrupt is enabled in the one-chip microcomputer, it is assumed that the interrupt signal by the key input is valid.

Next, the operation will be described. Here, a one-chip microcomputer (hereinafter referred to as one-chip microcomputer) will be described as an example. Generally, a one-chip microcomputer synchronizes with another one-chip microcomputer using a clock signal.

The clock signal is supplied to another semiconductor integrated circuit by connecting an oscillator to the one-chip microcomputer to generate a clock signal inside the one-chip microcomputer.

It is possible to stop the oscillator and hold the one-chip microcomputer in a state before stopping the oscillator (hereinafter, this state is called a stop state). The one-chip microcomputer does not operate during the stop state because the oscillator stops and the internal clock cannot be generated.

Further, it is possible to stop only the internal clock of the one-chip microcomputer without stopping the oscillator, and hold the one-chip microcomputer in the state before the stop of the internal clock (hereinafter, this state is referred to as a wait state). ).

In order to operate the one-chip microcomputer from the stop state and the wait state, it is possible to carry out restoration by interrupt or initialization of the one-chip microcomputer by reset input.

Of these, a key-on wakeup is an example of the above-mentioned interrupt. This key-on wakeup is an I / O port that has a key-on wakeup function of a one-chip microcomputer, and generates an interrupt signal when an "L" level is input to an I / O port set to the input state. It has a function to do.

That is, by inputting the "L" level to this I / O port, it is possible to return from the stop state or the wait state to the operating state, and to the I / O port by key input such as ten keys. If a circuit to which the “L” level is applied is connected to the semiconductor integrated circuit,
Since an interrupt can be generated by key input, various things can be done with the key input as a trigger.

The I / O port has an input state and an output state, and the input / output is determined by the direction register 5.
When the direction register 5 is "1", the I / O port is set to the output state, while when it is "0", it is set to the input state.

Direction register 5 is "1", port latch 6
When the data inside is "0", "H" is output from the NAND gate 15 and the NOR gate 16, the P-channel transistor 13 is in the OFF state, and the N-channel transistor 14 is in the OFF state.
Is turned on, and “L” is output to the external input / output terminal 3.

When the direction register is "1" and the data in the port latch 6 is "1", "L" is output from the NAND gate 15 and the NOR gate 16, the N-channel transistor 14 is in the off state, and the P-channel transistor 13 is in the off state. Is turned on, and "H" is output to the external input / output terminal 3.

Next, the interrupt is disabled and the direction register is set to "
When 0 ”and the pull register are“ 0 ”, the output of the buffer 9 is valid, the external input / output terminal 3 is in the input state, and the input signal is output from the buffer 9 to the data bus 4.

Interrupt disabled, direction register "0",
When the pull register is "1", the pull-up transistor 11 and the P-channel transistor 12 are on, the output of the buffer 9 is valid, and the external input / output terminal 3 is "1".
Is output.

At this time, since the ON resistance of the pull-up transistor 11 is several tens of kΩ, when the "L" level that overcomes the "H" level output by the pull-up transistor 11 is input to the external input / output terminal 3, the buffer 9 is input. To "L" are output to the data bus 4.

When an "L" level input below the "L" level or an "H" level is input, the buffer 9 outputs "
H "is output to the data bus. Also, the port latch 6
The data stored in the buffer is output from the buffer 8 to the data bus when the direction register is "1".

Interrupt is valid, direction register is "0",
When the pull register is "0", the output of the buffer 9 is valid,
The external input / output terminal 3 becomes the input state, and the external input / output terminal 3
When the "L" level that overcomes the "H" level output by the pull-up transistor 11 is input to the, the interrupt signal "L" is output via the Schmitt circuit 10. At this time, an interrupt occurs and the output signal to the data bus becomes invalid.

FIG. 7 shows a key-on wake-up function circuit for performing an interrupt by any one of the plurality of ports assigned to key input, and in the figure, 24 is the I / O shown in FIG. A port 1-bit key-on wake-up circuit, and 25 a key switch.

Generally, since a large number of key inputs are required, the I / O port having the key-on wakeup function is not composed of 1 bit, but is composed of a plurality of bits as shown in FIG. ing. In the case of an I / O port having a multi-bit key-on wakeup function, the logical product of the interrupt signals of each bit is NOR gate 26.
Then, this is used as an interrupt signal by key input. In addition, as a related technical document of these conventional technologies, "Mitsubishi Electric Corporation, Delivery Standard Kitanoki-M38200MX"
-XXXP-00-A P15, P19 1993 1
There is a monthly issue.

[0025]

Since the conventional key-on wakeup function circuit is configured as described above,
In order to enable the key-on wake-up, it is necessary to set the I / O port having the key-on wake-up function to the input state, enable the pull-up transistors 11 and 12, and then set the stop state or the wait state. Therefore, the program has a problem that a large amount of memory is required for the program for enabling the key-on wakeup in order to execute the above three things.

The invention of claim 1 has been made to solve the above-mentioned problems, and each port assigned to key-on wake-up is automatically set to key-on wake-up interrupt acceptance setting for each port assigned to key-on wake-up. An object of the present invention is to obtain a key-on wake-up mode setting circuit that can be easily set to various types simply by writing data in the register for use.

It is an object of the present invention to provide a key-on wakeup mode setting circuit capable of effectively setting the key-on wakeup in the wait state.

According to a third aspect of the present invention, a key-on wake-up mode setting circuit capable of accepting a key-on wake-up interrupt by a specific port can be obtained by writing data to a specific bit of the key-on wake-up automatic setting register. To aim.

According to a fourth aspect of the present invention, the key-on wakeup mode can be enabled, the stop state can be set, and the wait state can be set by writing to the key-on wakeup automatic setting register of each byte. The purpose is to obtain a setting circuit.

According to the fifth aspect of the present invention, even when there are a plurality of ports assigned to the key-on wakeup, the bit of each port used for the key-on wakeup can be easily specified by the data written to the key-on wakeup automatic setting register. The purpose is to obtain a key-on wake-up mode setting circuit.

[0031]

According to a first aspect of the present invention, there is provided a key-on wake-up mode setting circuit, which is provided with a key-on wake-up automatic setting register for enabling pull-up by writing data and enabling an interrupt. When the above interrupt is enabled, the clock signal and the data for stopping the oscillator are written in the clock signal control register.

In the key-on wake-up mode setting circuit according to the invention of claim 2, in the oscillation control, the oscillator stopped and the internal clock written in the clock signal control register are controlled by the data to be written in the key-on wake-up automatic setting register. The current stop and oscillation control are selectable.

The key-on wakeup mode setting circuit according to the invention of claim 3 has a port having an input function corresponding to each bit of the key-on wakeup automatic setting register, and the bit of the key-on wakeup automatic setting register is By writing the data to the port, the port is set to the input state to accept the interrupt by the key input, and the pull-up enable setting is enabled only to the port corresponding to the bit in which the data is written. .

A key-on wake-up mode setting circuit according to a fourth aspect of the present invention is a port having an input function of grouping several bits corresponding to each bit of the key-on wake-up automatic setting register as one group or one bit as a group. When the data is written to the bit of the key-on wakeup automatic setting register, the port is set to the input state to accept the interrupt by the key input, and the pull-up enable setting is written. This is possible only for a group of ports corresponding to bits.

In the key-on wakeup mode setting circuit according to the fifth aspect of the present invention, there are a plurality of port groups to which the ports are functionally assigned, and a plurality of ports in one group must be set to the same port group. With the data written to the key-on wakeup automatic setting register, the port is set to the input state in order to accept the interrupt by key input to the above group, and the pullup enable setting corresponds to the bit in which the above data is written. This is possible only for a group of ports.

[0036]

The key-on wake-up mode setting circuit according to the first aspect of the present invention automatically enables the key-on wake-up by writing the data for enabling the interrupt of the key-on wake-up automatic setting register.

In the key-on wakeup mode setting circuit according to the second aspect of the present invention, by writing "1" in the first bit of the key-on wakeup automatic setting register, "0" is written in the direction register to enable the interrupt. Further, data in which the oscillator is stopped and data in which the clock is stopped are written in the clock signal control register to enable the key-on wakeup to be enabled in the wait state.

In the key-on wakeup mode setting circuit according to the third aspect of the present invention, by writing "1" to the specific bit of the key-on wakeup automatic setting register, the specific port can accept the interrupt due to the key-on wakeup. .

In the key-on wakeup mode setting circuit according to the invention of claim 4, the first byte, the second byte, and the third byte
By writing each key-on wakeup automatic setting register at the byte, the key-on wakeup is enabled, the stop state is set, and the wait state can be set.

According to the fifth aspect of the present invention, the key-on wake-up mode setting circuit uses the data written in the key-on wake-up automatic setting register even when there are a plurality of ports assigned to the key-on wake-up.
Allows you to specify the bit for each port used for key-on wakeup.

[0041]

【Example】

Example 1. An embodiment of the invention of claim 1 will be described below with reference to FIG. In the figure, 1 is Vc of the semiconductor integrated circuit
c, 2 is ground, 3 is an external input / output terminal, 4 is a data bus,
Reference numeral 5 is a direction register that determines the input / output of the I / O port.

Further, 6 is a port latch for storing the data to be output to the I / O port, and 7 is a pull register for deciding whether to enable or disable the pull-up transistor.

Reference numeral 8 indicates the contents of the port latch 6 on the data bus 4
A buffer for outputting input data to the data bus 4 when the I / O port is in an input state, 10 a Schmitt circuit for key-on wakeup, and 11 a pull-up transistor.

Further, 12 is a P-channel transistor which is controlled so that pull-up becomes effective only when the I / O port is set to input, and 13 is for outputting data to the external input / output terminal 3. P-channel transistor,
Reference numeral 14 is an N-channel transistor for outputting data to the external input / output terminal 3, and 15 is a NAND gate for controlling external output.

Further, 16 is a NOR gate for controlling external output, 17 is an inverter for controlling external output, and 19 is a key-on wakeup interrupt input.

The P-channel transistor 13,
The N-channel transistor 14, the NAND gate 15 and the NOR gate 16 form a switching circuit X that switches an output signal to the external input / output terminal 3.

Reference numeral 20 is a key-on wakeup automatic setting register, 21 is a NOR gate for controlling the pull-up transistor 11, 22 is a clock signal control register, and 23 is the inversion of the contents of the key-on wakeup automatic setting register 20. It is an inverter that outputs a signal.

The pull-up transistor 11 has an ON resistance of several tens of kΩ, and the P-channel transistor 12 has an ON resistance sufficiently smaller than that of the pull-up transistor 11. When the interrupt is enabled in the one-chip microcomputer, it is assumed that the interrupt signal by the key input is valid.

Here, when "1" is written in the key-on wakeup automatic setting register 20, "0" is written in the direction register 5, and the clock signal and the oscillator are stopped in the clock signal control register 22. It is assumed that such data is written and the interrupt is set to be valid.

Next, the operation will be described. The operation other than the operation different from the above-mentioned conventional example is the same as that of the conventional example, and thus the duplicate description thereof will be omitted.

In this embodiment, by writing "1" in the key-on wakeup automatic setting register 20,
At the same time that the pull-up transistor 11 is turned on, "0" is written in the direction register 5, so that P
The channel transistor 12 is turned on and the pull-up is enabled.

Further, by writing the clock signal and the data for stopping the oscillator to the clock signal control register 22, the oscillator is stopped and the clock signal is stopped.
Furthermore, in order to enable the interrupt, by key input,
When the "L" level that overcomes the "H" level output by the pull-up transistor 11 is input to the external input / output terminal 3, the "L" level of the interrupt signal 19 as the key-on wakeup interrupt input is input via the Schmitt circuit (10). ”
Is output.

At this time, an interrupt occurs and the output signal to the data bus becomes invalid. Further, when the interrupt processing is completed, "0" is automatically written in the key-on wakeup automatic setting register 20. In this embodiment, when data is written to the key-on wakeup automatic setting register 20 after the direction register 5 and pull register 7 are set and interrupts are enabled, the stop state is automatically set.

Although the port having the direction register 5 is shown in this embodiment, the same effect can be obtained even in the case of an input-only port having no direction register although the effect is small. Further, the same effect can be obtained with respect to the input-only terminals excluding the direction register 5, the port latch 6, and the switching circuit X, which are circuits for controlling the output from the above circuit.

Example 2. FIG. 2 shows the contents of the key-on wakeup automatic setting register 20. here,
The key-on wakeup automatic setting register 20A corresponds to the key-on wakeup automatic setting register 20 in FIG. In this key-on wakeup automatic setting register 20A, "1" is set at the 0th bit.
Is written in the direction register 5 in FIG.
0 "is written to enable the interrupt, and data for stopping the oscillator and data for stopping the clock signal are written to the clock signal control register 22 in FIG. 1. As a result, the key-on wake By writing to the 0th bit of the automatic up setting register 20A, the same effect as that of the embodiment 1 is obtained, and when the interrupt processing is completed, the 0th bit of the automatic key-on wakeup automatic setting register 20A is automatically obtained. Is written with 0. That is, whether the oscillation control is to be in the wait state, the stop state, or the current state is determined by the data written in the key-on wakeup automatic setting register.

By writing "1" in the first bit of the key-on wakeup automatic setting register 20, "0" is written in the direction register 5 in FIG. 1 to enable the interrupt, and The data in which the oscillator oscillates and the data for stopping the clock signal are written in the clock signal control register 22 in 1.

As a result, it is possible to provide a setting for enabling the key-on wakeup in the wait state. Further, when the interrupt processing is completed, the first bit of the key-on wakeup automatic setting register 20 is automatically set to "
It is assumed that 0 "is written.

Further, by writing "1" in the second bit of the key-on wakeup automatic setting register, "0" is written in the direction register 5 in FIG. 1 to enable the interrupt, and Data is not written in the clock signal control register 22 in FIG.

As a result, the present invention can be applied to a program in which data processing is started by interruption by key input. When the interrupt processing is completed, "0" is automatically written in the second bit of the key-on wakeup automatic setting register 20.

Example 3. FIG. 3 shows another embodiment of the key-on wakeup automatic setting register. The key-on wakeup automatic setting register 20B corresponds to the key-on wakeup automatic setting register 20 in FIG.

In this embodiment, 8-bit I / O
Is assigned to the key-on wakeup port.

By writing "1" to the 0th bit of the key-on wakeup automatic setting register 20B,
"0" is written to all the 8-bit direction registers of the key-on wakeup port (1 bit each corresponds to the direction register 5 in FIG. 1), and the interrupt is set to be valid.

When the interrupt process is completed, "0" is automatically written to the 0th bit of the key-on wakeup automatic setting register 20B.

Further, by writing "1" to the first bit of the key-on wakeup automatic setting register 20B, a specific 4-bit direction register (each 1-bit is 1 bit) of the 8 bits of the key-on wakeup port. "0" is written in (corresponding to the direction register 5 in FIG. 1) to set the interrupt to be valid.

In this case, the remaining 4 bits for which "0" is not written in the direction register are not affected. Further, when the interrupt processing is completed, "0" is automatically written in the first bit of the key-on wakeup automatic setting register 20B.

Further, by writing "1" to the second bit of the key-on wakeup automatic setting register 20B, a specific 2-bit direction register (each 1-bit is 1 bit) among the 8 bits of the key-on wakeup port. "0" in (corresponding to the direction register 5 in FIG. 1)
And set to enable interrupts.

In this case, the remaining 6 bits in which "0" is not written in the direction register are not affected. When the interrupt process is completed, "0" is automatically written in the second bit of the key-on wakeup automatic setting register 20B.

As described above, by writing "1" to a specific bit of the key-on wakeup automatic setting register 20B, the specified plural bits of the key-on wakeup port or the direction register of the specified bit. It is possible to write "0" only in that and enable the interrupt.

In this case, the remaining bits for which "0" is not written in the direction register are not affected at all.

Further, a bit for writing "0" only in the direction register of the specified plural bits or the specified bit of the key-on wakeup port to enable the interrupt and the operation other than the above operation are shown. 1, the oscillator signal is sent to the clock signal control register 22 in FIG. 1 in addition to the above-described operation, and bits for writing data for stopping the oscillator in the clock signal control register 22. The effect of the second embodiment can be obtained by providing a bit for writing such data and data for stopping the clock signal.

When the interrupt processing is completed, "0" is automatically written in the bit used in the key-on wakeup automatic setting register 20B. By thus writing the specific bit "1" of the key-on wakeup automatic setting register 20B, the specific port can be made ready to accept the interrupt due to the key-on wakeup.

Example 4. FIG. 4 shows another embodiment of the key-on wakeup automatic setting register. Here, FIG.
The three key-on wakeup automatic setting registers 20C shown in (a) to (c) correspond to the respective key-on wakeup automatic setting registers 20 in FIG.

In this embodiment, 8-bit I / O
Is assigned to the key-on wakeup port.

Each bit of each key-on wakeup automatic setting register 20C corresponds to each bit of each key-on wakeup port, and the interrupt is enabled by writing the data to the keyon wakeup automatic setting register 20C. Shall be

Further, when the interrupt processing is completed, the key-on wakeup automatic setting register 20C is automatically set.
"0" is written in all the bits of.

Then, the key-on wakeup automatic setting register 20C for 3 bytes is provided, and the key-on wakeup becomes effective if the first byte register is written. If the second byte register is written, the key-on wakeup is enabled and set to the stop state, and the third byte register is written, the key-on wakeup is enabled and set to the wait state. The same effect as can be obtained.

Example 5. FIG. 5 shows another embodiment of the key-on wakeup automatic setting register. The key-on wakeup automatic setting register 20D corresponds to the key-on wakeup automatic setting register 20 in FIG.

In this embodiment, 8-bit I / O
Is assigned to two groups (port 1 and port 2 respectively) for key-on wakeup.

By writing data "1 (hexadecimal data)" to the key-on wakeup automatic setting register 20D, the lower 4 bits of the port 1 are set to be able to accept the interrupt due to the key-on wakeup. At this time, ports other than the lower 4 bits of port 1 are not affected.

Further, by writing the data "2 (hexadecimal data)" to the key-on wakeup automatic setting register 20D, all the bits of port 1 are set to accept the interrupt due to the key-on wakeup. At this time, the port 2 is not affected.

By writing "3 (hexadecimal data)" data in the key-on wakeup automatic setting register 20D, all the bits of port 1 and the lower 2 bits of port 2 are set to be able to accept the interrupt due to the key-on wakeup. To be done. At this time, 3 bits to 8 bits of the port 2 are not affected.

Furthermore, by writing data "4 (hexadecimal data)" to the key-on wakeup automatic setting register 20D, all bits of port 1 and lower 4 bits of port 2 can accept interrupts due to key-on wakeup. Is set to. At this time, the upper 4 bits of port 2 are not affected.

By writing "5 (hexadecimal data)" to the key-on wakeup automatic setting register 20D, all bits of port 1 and the lower 6 bits of port 2 are set to accept interrupts by key-on wakeup. To be done. At this time, the upper 2 bits of port 2 are not affected.

By writing data "6 (hexadecimal data)" to the key-on wakeup automatic setting register 20D, all the bits of port 1 and port 2 are set to be able to accept the interrupt due to the key-on wakeup.

Further, it is assumed that the interrupt becomes valid by writing data in the key-on wakeup automatic setting register 20D. Furthermore, it is assumed that when the interrupt processing is completed, "0 (hexadecimal data)" is automatically written in the key-on wakeup automatic setting register 20D.

Even when there are a plurality of ports assigned to the key-on wakeup in this way, the bit of each port used for the key-on wakeup can be easily specified by the data written in the key-on wakeup automatic setting register 20D. is there.

[0087]

As described above, according to the invention of claim 1, the key-on wakeup automatic setting register for enabling the pull-up by writing the data and enabling the interrupt is provided, and the interrupt is enabled. When doing
Since the clock signal and the data for stopping the oscillator are written to the clock signal control register, not only the program until the key-on wakeup is enabled can be facilitated, but also the key-on wakeup is assigned. Each port can be easily set to various types simply by writing data to the key-on wakeup automatic setting register for setting the key-on wakeup interrupt acceptance.

According to the invention of claim 2, by the data written in the key-on wakeup automatic setting register,
In the oscillation control, the oscillator written in the clock signal control register, the internal clock only, and the oscillation control are configured so that the current state can be selected.
There is an effect that a key on wakeup can be effectively set in a wait state with a small program capacity.

According to the invention of claim 3, there is a port having an input function corresponding to each bit of the key-on wakeup automatic setting register, and data is written to the bit of the key-on wakeup automatic setting register. In this way, the port is set to the input state so that the interrupt by key input can be accepted, and the pull-up enable setting can be executed only to the port corresponding to the bit written with the above data. By writing data to a specific bit of the setting register, there is an effect that a specific port can receive an interrupt due to a key-on wakeup with a small program capacity.

According to the invention of claim 4, there is a port having an input function of grouping several bits corresponding to each bit of the key-on wakeup automatic setting register, or a group having 1 bit, and the key-on wakeup is provided. When data is written to the bits of the automatic setup register, the port is set to the input state in order to accept the interrupt due to key input, and the pull-up enable setting is made for the port corresponding to the bit to which the data is written. Since it is configured so that it can be executed only for the group, by writing to the key-on wakeup automatic setting register of each byte individually, the key-on wakeup can be enabled, the stop state can be set, and the wait state can be set with a small program capacity. There is an effect that something that can set is obtained.

According to the fifth aspect of the present invention, there are a plurality of port groups to which ports are functionally assigned, and a plurality of ports within one group must be set to the same port group for the above key-on wakeup automatic setting. According to the data written to the register, the port is set to the input state so that the interrupt by key input can be accepted for the above group, and the pull-up enable setting is performed only for the group of ports corresponding to the bit to which the above data is written. Even if there are multiple ports assigned for key-on wakeup, the data written to the key-on wakeup automatic setting register can be used with a small program capacity and the bits of each port used for key-on wakeup can be easily configured. The effect that can be specified is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a key-on wakeup mode setting circuit according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an embodiment of a key-on wakeup automatic setting register in FIG.

FIG. 3 is an explanatory diagram showing another embodiment of the key-on wakeup automatic setting register in FIG.

FIG. 4 is an explanatory diagram showing another embodiment of the key-on wakeup automatic setting register in FIG.

5 is an explanatory diagram showing another embodiment of the key-on wakeup automatic setting register in FIG. 1. FIG.

FIG. 6 is a block diagram showing a conventional key-on wakeup function circuit.

FIG. 7 is a block diagram showing a key-on wakeup function circuit for performing an interrupt by any one of a plurality of key inputs.

[Explanation of symbols]

 3 External Input / Output Terminal 4 Data Bus 5 Register (Direction Register) 6 Register (Port Latch) 7 Register (Pull Register) 8 Buffer (First Buffer) 9 Buffer (Second Buffer) 10 Schmitt Circuit 11 Pull-up Transistor 12 Transistor 20 Key-on wakeup automatic setting register 22 Clock signal control register X switching circuit

[Procedure amendment]

[Submission date] March 23, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0025

[Correction method] Change

[Correction content]

[0025]

Since the conventional key-on wakeup function circuit is configured as described above,
In order to enable the key-on wake-up, the I / O port having the key-on wake-up function is set to the input state, the pull-up transistor 11 and the P-channel transistor are connected.
Since it is necessary to set the stop state or the wait state after enabling the register 12, the program needs a large amount of memory for enabling the key-on wakeup in order to execute the above three things. There was a problem such as doing.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0049

[Correction method] Change

[Correction content]

Here, when "1" is written in the key-on wakeup automatic setting register 20, "0" is written in the direction register 5, and the clock signal and the oscillator are stopped in the clock signal control register 22. It is assumed that such data is written and the interrupt is set to be valid. Also, stop the clock signal and oscillator.
When stopped, the one-chip microcomputer is interrupted or reset.
The operation of the one-chip microcomputer is stopped until
Of the above series of operations, the clock signal
Data is written last to stop the
Shall be.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0056

[Correction method] Change

[Correction content]

Further , as in the first embodiment, the wait state and
Key on to write data to get to the top state
At the end of the series of operations until wakeup is enabled
Shall be performed. Further, by writing "1" to the first bit of the key-on wakeup automatic setting register 20, "1" is written in the direction register 5 in FIG.
"0" is written to enable the interrupt, and the clock signal control register 22 shown in FIG. 1 is written with data in which the oscillator oscillates and data with which the clock signal is stopped.

Claims (5)

[Claims] 1. A direction register or an input-only port for setting an input / output state of an external input / output terminal, a pull-up transistor for pulling up the external input / output terminal, and a pull register for controlling the pull-up transistor. To the external input / output terminal depending on the state of the transistor that enables the pull-up when inputting the write output terminal and the direction register and the port latch that stores the data.
A switching circuit that outputs an L "or" H "level signal;
A first buffer that outputs the contents of the port latch to the data bus; and a second buffer that outputs the input data from the external input / output terminal to the data bus when in the input state,
When an interrupt is enabled, an interrupt input that disables output of input data from the input / output terminal to the data bus when a signal of a level that overcomes the output of the pull-up transistor is input to the external input / output terminal A Schmitt circuit that occurs, a register for key-on wakeup automatic setting that enables the pull-up by writing data and enables the interrupt, and a clock signal and data for stopping the oscillator when enabling the interrupt. A key-on wake-up mode setting circuit having a clock signal control register for writing. 2. With the data written in the key-on wakeup automatic setting register, in the oscillation control, the stop of the oscillator written in the clock signal control register, the stop of only the internal clock, and the oscillation control can be selected to maintain the current state. The key-on wakeup mode setting circuit according to claim 1. 3. A port having an input function corresponding to each bit of the key-on wakeup automatic setting register is provided, and an interrupt due to a key input is accepted by writing data in the bit of the key-on wakeup automatic setting register. 2. The key-on wake-up mode setting circuit according to claim 1, wherein the port is set to an input state to enable the pull-up enable only for the port corresponding to the written bit of the data. 4. A key-on wakeup automatic setting register has a port having an input function of grouping several bits corresponding to each bit of the key-on wakeup automatic setting register, or 1 bit as a group. The port is set to an input state so that an interrupt due to a key input can be accepted by writing data to the port, and pull-up enable setting can be performed only to a group of ports corresponding to the bit in which the data is written. Key-on wake-up mode setting circuit described. 5. A plurality of port groups to which ports are functionally allocated are provided, and a plurality of ports in one group are set to the same port group without fail, and the data is written to the key-on wakeup automatic setting register for the group. 2. The key-on wake-up mode according to claim 1, wherein a port is set to an input state so that an interrupt due to a key input can be accepted, and pull-up enable setting is possible only for a group of ports corresponding to the bit in which the data is written. Setting circuit.