JPH1070456A - Digital pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the phase adjustment capability of the digital PLL circuit from being deteriorated attended with low power consumption. SOLUTION: A REF signal is a clock signal and a C signal is a data signal. Register circuits 11, 12 receive two signals being the C signal and a C' signal delaying the C signal by a delay gate 14 by using the REF signal as a timing signal. A matching discrimination circuit 13 discriminates the matching between the C and C' signals received by the register circuits 11, 12. Gating circuits 15, 16 gate respectively the REF signal and the C signal given to a phase comparator 1 based on an output signal from the matching discrimination circuit. That is, when the output signal indicates coincidence, the input of the REF signal and the C signal to the phase comparator is inhibited and when the output signal indicates dissidence, the input of the REF signal and the C signal to the phase comparator is authorized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital PLL.
The present invention relates to a circuit, and more particularly, to a digital PLL circuit that prevents a decrease in phase adjustment capability due to a reduction in power consumption.

[0002]

2. Description of the Related Art In order to reduce the power consumption of a conventional PLL circuit, as disclosed in Japanese Patent Application Laid-Open No. 58-066422, the operating conditions (ambient temperature in the embodiment) of the PLL circuit are monitored. There is an operation condition monitoring method for performing a lock operation for a predetermined time when a change is detected in the operation condition. Further, as introduced in Japanese Patent Application Laid-Open No. 2-311020, there is a low-speed operation method in which the digital PLL circuit itself operates at a lower speed than the input signal.

[0003]

SUMMARY OF THE INVENTION The above-mentioned conventional PLL
The method of reducing power consumption in a circuit is that, in the operating condition monitoring method, the condition for causing the PLL circuit to perform the phase adjustment operation is a specific operating condition that is only indirectly related to the phase shift between two signals such as the ambient temperature. Because of the limitation, even if a phase difference occurs due to other conditions, the PLL circuit does not operate, and there is a leak in the condition of low power consumption, and there is a disadvantage that the phase adjustment capability is reduced.

In the low-speed operation method, since the PLL circuit is operated at a lower speed than the input signal at a constant speed, the PLL circuit operates at a lower speed.
The operation of adjusting the phase between the signals is delayed irrespective of the phase shift between the two signals, and there is a disadvantage that the serviceability of the phase adjustment of the PLL circuit is reduced.

An object of the present invention is to provide a circuit for detecting that the phases of two signals coincide with each other, and stop the phase adjustment operation while the phases of the two signals coincide with each other. An object of the present invention is to provide a low-power-consumption digital PLL circuit that does not cause the above-described reduction in phase adjustment capability due to power consumption.

[0006]

According to a first aspect of the present invention, there is provided a circuit for detecting that the phases of two signals match, and the phase adjusting operation is stopped while the phases of the two signals match. It is characterized by.

The second invention is a clock RE
A register circuit 11 and a register for taking in two signals, an F signal and a C signal indicating data, a delay gate, the C signal and the C 'signal obtained by delaying the C signal by the delay gate with the REF signal as a timing. A circuit 12;
A match judging circuit for judging a match between the C signal and the C 'signal taken into the register circuits 11 and 12, a REF signal and the C signal input to a phase comparator based on an output signal from the match judging circuit; , And a gating circuit 15 and a gating circuit 16 for respectively gating the gates.

In a third aspect of the present invention, the gating circuits 15 and 16 according to the second aspect of the present invention are arranged such that when the output signal from the match determination circuit indicates a match, the gating circuits 15 and 16 output the REF signal and the C signal.
The input of the signal to the phase comparator is inhibited, and the input of the REF signal and the C signal to the phase comparator is permitted when the output signal from the match determination circuit indicates a mismatch.

Further, a fourth aspect of the present invention relates to a clock R
A register circuit 11 and a register which take in two signals, an EF signal and a C signal indicating data, a delay gate, the REF signal and the REF 'signal obtained by delaying the REF signal by the delay gate, with the C signal as a timing. A circuit 12, a match judging circuit for judging a match between the REF signal and the REF 'signal taken into the register circuits 11, 12, and the REF signal inputted to a phase comparator based on an output signal from the match judging circuit. And a gating circuit 15 and a gating circuit 16 for respectively gating the C signal.

A fifth invention is characterized in that the amount of delay by the delay gate in the second and fourth inventions can be set arbitrarily.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.
FIG. 2 is a time chart illustrating the operation of the present embodiment.

Referring to FIG. 1, in the present embodiment, it is determined whether or not the phases of a REF signal as a clock and a C signal indicating data coincide with the phases of two signals, a REF signal to be phase-adjusted and a C signal. A delay gate 14 for determining the accuracy, and a C signal and a C 'having a slight phase difference by the delay gate 14.
Register circuits 11 and 12 for taking in two of the signals at the timing of the other signal REF signal;
The circuit comprises a coincidence determination circuit 13 for determining the coincidence of the signal levels taken into the register circuits 11 and 12, and gating circuits 15 and 16 for controlling a signal input to the phase comparator 1 of the digital PLL circuit.

In FIG. 1, two signals REF and C for adjusting the phase are ANDed before being input to the phase comparator 1.
The signals are input to the circuits 15 and 16, and the propagation to the phase comparator 1 is controlled by the output S of the ENOR circuit 13. Also, the signal RE
F is input to the clock terminals of the two D-type flip-flop circuits 11 and 12, the signal C is input to the data input terminal of the D-type flip-flop circuit 12 and the delay gate 14, and the output C 'of the delay gate 14 is output. Is input to the data input terminal of the D-type flip-flop circuit 11. The outputs Q1 and Q2 of the D-type flip-flop circuits 11 and 12 are connected to the aforementioned E
Input to NOR circuit 13.

The delay value of the delay gate 14 can be set arbitrarily.

A digital PL including a phase comparator 1
The L circuit adjusts the phase of the two signals to be compared only when the determination result in the match determination circuit 13 does not match. When the determination result in the match determination circuit 13 matches, the L circuit turns off the power supply and performs the phase adjustment operation. It shall be configured to stop. As described above, since the configuration for turning off the power of the digital PLL circuit by itself when a certain condition is not satisfied is a known technique (for example, see Japanese Patent Application Laid-Open No. 58-066422), its details are not shown here.

Next, the operation of this embodiment will be described in detail with reference to FIGS.

The phase difference between the two signals REF and C is C and C
Is larger than the phase difference of C 'delayed by the delay gate 14, as shown in FIG. 2, the REF signal is clocked, and the C and C' signals are used as data, and the D flip-flops 11, 1 are used.
When 2 operates, as a result, the outputs Q1 and Q2 output the same value. Therefore, the output S of the ENOR circuit 13 which receives Q1 and Q2 as inputs becomes H level, and the AND circuits 15 and 16
Are transmitted to the next-stage phase comparator 1 to perform a phase comparison adjustment operation.

On the other hand, when the phase difference between the two signals REF and C is within the range of the propagation delay of the delay gate 14, the outputs Q1 and Q2 of the two D-type flip-flop circuits 11 and 12 are, as shown in FIG. Output different values. Therefore, the output S of the ENOR circuit 13 having Q1 and Q2 as inputs is at L level, and the signals REF and C input to the AND circuits 15 and 16 do not propagate to the next-stage phase comparator 1, and the phase adjustment operation is not performed. Stop.

FIG. 3 is a block diagram showing another embodiment of the present invention. In the first embodiment, the delay gate 14 for determining the accuracy of determining whether or not the phases of the two signals for adjusting the phase match is provided on the data side of the register circuits 11 and 12. As shown in FIG. 3, it is placed on the timing signal side for taking in data.

[0021]

As described above, the digital PLL circuit of the present invention determines whether the phases of two signals match or not, and if they match, turns off the power until the phases are out of phase again. By doing so, there is an effect of preventing a decrease in the phase adjustment capability of the digital PLL circuit due to the omission of the condition for low power consumption and a decrease in the serviceability of the digital PLL circuit due to a low operation speed due to low power consumption.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a digital PLL circuit of the present invention.

FIG. 2 is a time chart showing the operation of the embodiment of FIG.

FIG. 3 is a configuration diagram showing another embodiment of the digital PLL circuit of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 phase comparator 11, 12 register (D-type flip-flop circuit) 13 match determination circuit (ENOR circuit) 14 delay gate 15, 16 gating circuit (AND circuit)

Claims (5)

[Claims] 1. A digital PLL circuit comprising a circuit for detecting that the phases of two signals match, and stopping the phase adjustment operation while the phases of the two signals match. 2. A REF signal which is a clock, a C signal indicating data, a delay gate, and two signals of the C signal and the C 'signal obtained by delaying the C signal by the delay gate are used for timing the REF signal. Register circuit 11 and register circuit 12, and register circuit 11,
A match determination circuit for determining a match between the C signal and the C 'signal captured by the C.12; and a gate for respectively gating the REF signal and the C signal input to a phase comparator based on an output signal from the match determination circuit. A digital PLL circuit comprising a gating circuit 15 and a gating circuit 16. 3. The gating circuits 15, 16 inhibit the input of the REF signal and the C signal to the phase comparator when the output signal from the match determination circuit indicates a match, and When the output signal indicates a mismatch, the R
3. The digital PL according to claim 2, wherein input of the EF signal and the C signal to the phase comparator is permitted.
L circuit. 4. A REF signal as a clock and a C signal indicating data, a delay gate, the REF signal and the REF signal.
A register circuit 11 and a register circuit 12 which take in two signals of the REF 'signal whose signals are delayed by the delay gate at the timing of the C signal, and the REF signal and the RE which are taken in the register circuits 11 and 12, respectively.
A match determining circuit for determining a match of the F 'signal; and a gating circuit 15 and a gating circuit 16 for respectively gating the REF signal and the C signal input to a phase comparator based on an output signal from the match determining circuit. A digital PLL circuit characterized by the above-mentioned. 5. The digital PLL circuit according to claim 2, wherein the amount of delay by said delay gate can be set arbitrarily.