JPS6365974B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device that can reduce power consumption in a computer with a clock or the like.

Conventionally, the system block of an integrated circuit device (hereinafter referred to as LSi) for a computer with a clock, for example, has generally been configured as shown in FIG. OR gate of output of frequency divider (DV) 2 of clock device
The operation is started by the OR output S, and the operation is controlled by instructions from the read-only memory (ROM) 3. In addition, random access memory (RAM) 4 is an arithmetic register,
It is used as a clock register and flag, and a display device (DISPLAY) 5 displays the contents of the RAM 4 in accordance with instructions from the CPU 1. The CPU 1 starts its operation in response to the above S (key input or second signal) signal, and when the calculation and time processing are completed within the CPU, it enters a halt (temporary stop) state, and system clock pulses other than the clock pulses necessary for display, etc. and enters low power operation. CPU1
maintains the halt state until the next key input or an S signal consisting of a 1 second signal arrives. But the key is ON
The drawback was that the CPU could not enter low-power operation if it remained in this state.

Therefore, in conventional clock mode, etc., signal input based on unnecessary key operations is prohibited (LOCK).
In order to do this, design was performed using software processing.

That is, as shown in Figure 2, the Key input signal or 1
When any signal S of the second clock signal arrives, it is determined whether the mode is in clock mode, and if it is not in clock mode, it executes arithmetic processing and displays the processing result. On the other hand, if it is in clock mode, it is in the LOCK state. (For example, this can be determined by checking that the mode switch is set to watch mode.)

However, such software design had the disadvantage that the program was actually being executed even on the LOCKed keys, consuming power in the same way as during calculation.

On the other hand, in the key input circuit device configured in the LSi system, as shown in Figure 3, a key strobe signal is introduced to the input terminal of each key ki via the terminal Oi, and a pull-down signal is input to the input terminal Ki of each key. (pull-
For example, when key _k2 is operated, pull-down current Ip flows through k ₂ → K ₂ → R ₂ → −V as shown in the figure, and this flowing current causes The drawback is that it consumes a lot of electricity. That is, in the watch mode, unnecessary key operations cause the same program to be executed during calculation, and a pull-down current flows, resulting in power consumption.

The present invention has been made in order to eliminate the drawbacks of the integrated circuit devices in the conventional clock-equipped computers and the like.

That is, the present invention introduces a mode terminal that can set first and second different mode states (e.g., computer mode and watch mode, which can be set by a mode changeover switch) and signals related to a plurality of key operations. Connect a series circuit (for example, a series circuit of a pull-down resistor and a MOS transistor) containing an impedance element and a switch element (for example, a series circuit of a pull-down resistor and a MOS transistor) to which a predetermined potential is applied to the output terminal of each key and the output terminal of each key. The logic gate circuit means (for example, a combination of NAND gates) changes the logic level (for example, High level or "1", Low level or "0") and outputs a mode setting signal based on the key input signal and the logic level. , the first mode (e.g. computer mode)
In the second mode (e.g., clock mode), the switching element (e.g., MOS transistor) is turned OFF and the gate circuit outputs a high level signal. By prohibiting (LOCK), the power consumption of the LSi system is reduced.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIGS. 4a and 4b are system block diagrams of an example of LSi according to the present invention, in particular, a specific circuit configuration diagram of a key input circuit device.

In the figure, figure a is used to explain the operation in the computer mode, and figure b is used to explain the operation in the watch mode, which puts the key input signal in the LOCK state. Identical parts are denoted by the same reference numerals. It will be done.

In the figure, K ₀ is the mode terminal, for example,
Connect the K ₀ terminal to a slide switch (not shown) that selects the calculator and clock modes, and when the slide switch is in the “LOCK” mode position, a “High” level signal is applied to the K ₀ terminal, and the
A “Low” level signal is applied at the “LOCK” mode position. This mode terminal K ₀ is applied to one input of the NAND gates NA ₁ , NA ₂ , … through the inverter I ₀ . _{K 1} , K ₂ … are This is an input terminal for a key signal, and a series circuit of current control pull-down resistors R ₁ , R ₂ . . . and N-channel MOS transistors T ₁ , T ₂ . _{1 ,} T _{2 .} Its ON or OFF is determined by _the logic level applied to the key input terminals K _{1 ,} K ₂ . _{1 ,} NA _{2 .} Added as a start signal.

Next, the operation will be explained.

(i) Computer mode (see Figure 4a) This mode is the so-called non-LOCK state mode.
A “Low” level signal is applied to the mode terminal K ₀ , the output of the inverter I ₀ becomes “High” level, and the outputs of the NAND gates NA ₁ , NA ₂ . . . receive key input signals K ₁ , K ₂ . determined by the level of Now the output of inverter I ₀ is “High”
Since _the N-channel type MOS transistors T ₁ , _{T 2 .} In other words, when there is a key operation, one of the NAND gates NA ₁ , NA ₂ , etc. goes to "Low" level, and furthermore, the output S of NAND gate NA ₁₀ goes to "High" level,
This S signal is sent to the central processing unit (CPU) via the data line and starts the operation of the CPU. In the above, if any key is operated, for example
When the _K1 key is pressed, a pull-down current flows as shown. Therefore, in the computer mode, key input is effectively determined.

(ii) Clock mode (see Figure 4b) This mode is the so-called LOCK state mode.
Unlike the computer mode, this clock mode does not require key input, and it is necessary to eliminate unnecessary power consumption based on key input. In this case, a "High" level signal is applied to the mode terminal _K0 . Therefore, logic levels change due to differences in mode settings. Therefore, the output of the inverter I ₀ becomes "Low" level, and the MOS transistors T ₁ , T ₂ . . . corresponding to each key are rendered non-conductive (OFF), eliminating unnecessary power consumption due to key operations.

In other words, in the clock mode, the key input is set to a high impedance circuit and is logically controlled to a locked state. Since the output of the inverter _I0 is at "Low" level, regardless of the input level of the key inputs _K1 , _K2 ...
Its output becomes "High" level. that way,
Since all inputs to the NAND gate NA ₁₀ are at the "High" level, its output signal S is at the "Low" level, so the CPU does not start any operation based on this S signal. In other words, it is prohibited (LOCK).

Therefore, in the clock mode, no pull-down current flows and the CPU does not start operating, so power consumption due to these is completely eliminated.

Although the mode of a computer and a clock has been described in the embodiment, the present invention is not limited to these devices, and can of course be applied to various types of devices. Also, similar parts can be selected for the key on a switch.

As explained above, according to the integrated circuit device of the present invention, by changing the logic level of the mode terminal input, there is a mode in which key input is processed as a normal input, and a mode in which key input is logically locked. It has the advantage that it can be set at any time to a mode that reduces the power consumption of the LSi system by making the current control resistor such as a pull-down resistor non-conductive and putting it in a high impedance state.

[Brief explanation of drawings]

Fig. 1 is a system block diagram for explaining the LSi system, Fig. 2 is a conventional system flowchart, Fig. 3 is a circuit configuration diagram of a conventional key input circuit device, and Figs. 4 a and b are according to the present invention. A circuit configuration diagram of such an integrated circuit device is shown, in which a shows a computer mode;
Figure b shows the clock mode. In the diagram, 1: CPU, 2: Divider, 3:
ROM, 4: _{RAM, 5: Display, K0: Mode terminal, K1 to Kn : Key} signal input terminal, I: Inverter, NA: NAND gate, S: Key input or second signal.

Claims (1)

[Claims] 1. A mode terminal for setting first and second different mode states, each terminal for introducing signals related to the operation of a plurality of keys, and a predetermined potential at the output terminal of each of the keys. means for connecting a series circuit including an impedance element and a switching element that are given an impedance element, a means for changing the logic level applied to the mode terminal, and a signal based on each of the above key operations as one input, respectively, and the above mode setting. and a logic gate circuit means for inputting signals based on the switching element as other inputs, the logic gate circuit outputs the switching element in a first mode state based on the one logic level and makes the switching element conductive based on the key operation. and means for rendering the switching element non-conductive in a second mode state based on the other logic level and inhibiting the output of the logic gate circuit based on the key operation. An integrated circuit device characterized by: