JPH06266342A - Character display device - Google Patents

Abstract

PURPOSE:To prevent an access time from becoming long by storing contents generated by connecting a discrimination code and a character code or an attribute code in each address of a video RAM. CONSTITUTION:The discrimination code is stored in a latch circuit 11, and then the discrimination code held in the latch circuit 11 and the character code or attribute code outputted by a CPU 2 are connected and written in each address of the video RAM 1. Therefore, the 9-bit contents of the connected discrimination code and character code or attribute code can easily be read only by accessing the video RAM 1 only once by using an 8-bit video RAM 1. Consequently, when the kinds of display characters are increased, the number of bits of the character code and attribute code stored in the video RAM 1 can be increased, namely, the display information can be increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a character display device for displaying characters on a television screen or the like, and more particularly to a character display device suitable for preventing an increase in writing time due to an increase in storage capacity of a video RAM. .

[0002]

2. Description of the Related Art Recently, many TV receivers and VTRs are equipped with a so-called on-screen function for displaying various information such as channel and volume on the screen according to the viewer's intention. The on-screen function includes a video RAM and a character RO.
It is realized by including M. The video RAM stores a character code indicating a display character at an address corresponding to a display portion of a television screen, stores an attribute code indicating a modification such as a color or shape of the display character at an immediately preceding address, and stores the character code of the television signal. Access is made according to horizontal scanning and vertical scanning. In particular, in the case where a part or all of the displayed characters are continuously displayed in the screen display in the same modified state, the video RAM is arranged immediately before the address storing the character code of the first character whose modified state is changed. All that is required is to store the attribute code in the address. The character ROM stores all the character data that can be displayed on the television screen in a dot pattern of a specific character font, and is accessed by the character code read from the video RAM. On-screen display is realized by performing signal processing for display on the attribute code read from the video RAM and held therein and the character data read from the character ROM.

Here, the most significant bit of the storage code of the video RAM is assigned to a code which determines whether the storage code is a character code or an attribute code. That is, the storage code of the video RAM is
When the most significant bit is "0" or "1", it can be distinguished from the character code and the attribute code. For example, when one address of the video RAM is 8 bits,
Character codes and attribute codes can be set for each of 128 types using 7 bits, that is, 128 types of character data having 128 types of character modifications can be displayed.

By the way, when it is desired to increase the types of characters to be displayed, the storage capacity of the character ROM is increased.
It is also necessary to increase the kinds of character codes that the video RAM can store. As a concrete measure, the video RA
A method of storing a character code over two addresses of M is usually used.

[0005]

However, although the number of character codes that can be stored in the video RAM increases, one character code cannot be read unless the video RAM is accessed twice, so that access to the video RAM is possible. There was a problem that the time was long. Therefore, the present invention is
An object of the present invention is to provide a character display device capable of preventing the access time of the video RAM from becoming long even if the types of display characters are increased.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and is characterized in that a character in which a plurality of character data having a specific character font is stored. ROM and the character ROM
A video code in which a character code for accessing is stored in an address corresponding to the display portion on the display panel, and an attribute code for modifying the character data read from the character ROM according to the character code is stored in the immediately preceding address. In a character display device having a RAM and performing character display with character modification on the display panel, the character code, the attribute code, and a discrimination code for discriminating the character code and the attribute code A first means for generating and a second means for holding and outputting the discrimination code, wherein the discrimination code and the character code are connected to each address of the video RAM, and the discrimination code and the The point is that the contents of connecting the attribute code are stored.

[0007]

According to the present invention, the discrimination code held in the second means after being obtained from the first means, and the contents obtained by connecting the character code or the attribute code obtained from the first means are stored in the video RAM. Since it is stored at each address, even if the number of display characters is increased, the video RAM
Access time can be prevented from increasing.

[0008]

The details of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing a character display device of the present invention. still,
The character display device is built in the microcomputer, and the output information of the character display device is sent to the television screen.

In FIG. 1, (1) is a video RAM, a character code indicating a display character is stored in an address corresponding to a display portion of a television screen, and an attribute code indicating modification information such as color and shape of the display character. Is stored at the immediately preceding address. Particularly, when a part or all of the displayed characters are continuously displayed in the same modified state on the TV screen, the video RAM (1) is an address where the character code of the first character whose modified state is changed is stored. Only the attribute code is stored at the address immediately before. Further, in this embodiment, the video RAM
Each address in (1) shall consist of 9 bits,
The most significant bit is allocated for determining the character code and the attribute code, and the remaining 8 bits are allocated for storing the character code or the attribute code. For example, if it is arranged such that the most significant bit of "0" means the discrimination of the character code and the most significant bit of "1" means the discrimination of the attribute code, "00"
0 to 0FF "H (H is hexadecimal) 256 types of character codes are stored in the video RAM (1),
~ 1FF "H, 256 kinds of attribute codes are stored in the remaining addresses of the video RAM (1). Then, the stored code is read from the video RAM (1) and at the same time, the most significant bit is decoded to determine what the code is.

Now, one of the above-mentioned microcomputers
The machine cycle is the video RAM (1) regardless of the CPU timing for performing the read / write operation of the video RAM (1) based on the decoding result of the program and the operation of the CPU.
OSD (On Screen Displa) that performs the reading operation of (1)
y) consists of timing. Specifically, one machine cycle consists of three periods of CPU timing and three periods of OSD.
It consists of 6 states that repeat the timing alternately. Video RAM (1) has CPU timing and OS
Since it is accessed independently at D timing, a single port with a simple configuration will suffice. This technique has already been described in Japanese Patent Application No. 4-106608 filed by the present applicant.

(2) is the above-mentioned CPU (first means) for performing, for example, 8-bit arithmetic processing, which performs logical operation according to the decoding result of the program data and video RAM (1)
Address data, character code,
The attribute code or the like is transferred via the data bus (3), or the code is fetched via the data bus (3) for the purpose of confirming the contents already written in the video RAM (1). A row address register (4) is used to set row address data of the video RAM (1) from the CPU (2) through the data bus (3). Similarly, (5) is a column address register, and column address data of the video RAM (1) is set from the CPU (2) via the data bus (3).

(6) is a character ROM in which dot patterns of all characters to be displayed on the television screen are stored in advance. For example, when each display character that the viewer sees on the television screen is formed with a specific character font (vertical m dots × horizontal n dots), the character ROM (6) is developed with the character font at each address. The dot pattern will be stored.
The character ROM (6) is accessed by a character code read from the video RAM (1), and reads data of horizontal n dots m times in the vertical direction according to horizontal scanning.

(7) is a vertical position detection circuit for detecting the vertical start position of the displayed character. The vertical position detection circuit (7) uses the vertical sync signal Vsync present in the television signal.
The first counter function that counts the rising of the horizontal synchronizing signal Hsync in binary after being reset at the rising edge of, and the number of the horizontal synchronizing signals Hsync when the horizontal scanning is performed up to the vertical start position of the display character It has a first register function that is set in binary. The vertical position detection circuit (7) increments the row address every time the rising edge of the m horizontal sync signals Hsync is applied from the time when the first counter function counts the value of the first register function. Generate data. The vertical position detection circuit (7) derives a binary count value of the rising edges of the m horizontal sync signals Hsync to the character ROM (6) every time the row address data is incremented.
Therefore, the character ROM (6) is a video RAM.
It is accessed by the character code of (1) and further horizontal sync signal H
By loading sync, the horizontal n dot data of each display character can be read m times in the vertical direction. (8)
Is a horizontal position detection circuit for detecting the horizontal start position of the displayed character. The horizontal position detection circuit (8) has a second counter function of counting the rising edge of the dot clock DCK in binary after being reset at the rising edge of the horizontal synchronizing signal Hsync, and the horizontal scanning is performed up to the horizontal start position of the display character. It has a second register function in which the number of dot clocks DCK when it is broken is preset in binary. still,
The dot clock DCK repeats each cycle every time the horizontal scanning line passes through each dot in the horizontal direction of the display character. The horizontal position detection circuit (7) increments the column address data that is incremented every time the rising edge of the n dot clocks DCK is applied from the time when the second counter function counts the value of the second register function. To occur.

An address switching circuit (9) switches and outputs the data held in the row address register (4) or the vertical position detection circuit (7) in accordance with the timing switching signal C / O. Here, the timing switching signal C / O is a signal that goes high at CPU timing and goes low at OSD timing. That is, the address switching circuit (9) derives the data held in the low address register (4) to the video RAM (1) when the timing switching signal C / O is at high level, and the timing switching signal C
When / O is at the low level, the data held in the vertical position detection circuit (7) is derived to the video RAM (1). Similarly, (10) is also an address switching circuit, and when the timing switching signal C / O is at high level, the data held in the column address register (5) is derived to the video RAM (1), and the timing switching signal C / O is output. The data held by the horizontal position detection circuit (8) when in the low level is stored in the video RAM (1).
Is derived. Therefore, video RAM (1)
Is a low address register (4) at CPU timing
And the combined data of the column address register (5), and at the OSD timing, the combined data of the vertical position detection circuit (7) and the horizontal position detection circuit (8) are accessed.

Reference numeral (11) is a latch circuit (second means), which is a discrimination code for discriminating the character code and the attribute code, that is, "0" when discriminating the character code and "1" when discriminating the attribute code. The discrimination code is transferred and set from the CPU (2) via the data bus (3). The latch circuit (11)
The content of the latch circuit (11) is taken into the CPU (2) through the data bus (3) for the purpose of confirming the content of the latch circuit (11). (12) is a data switching circuit,
Video RAM according to the timing switching signal C / O
In (1), the character code including the discrimination code and the attribute code are written and read.
That is, the video RA in the writing state at the CPU timing
When the address corresponding to both data of the row address register (4) and the column address register (5) is accessed by M (1) and the CPU (2) generates a character code or an attribute code after the discrimination code, the video RA
A 9-bit character code including a discrimination code or an attribute code is stored in the address of M (1). Similarly, the video RA in the read state is read at the CPU timing.
When M (1) is accessed to an address corresponding to both data of the row address register (4) and the column address register (5), a character code or an attribute code including a discrimination code from the address of the video RAM (1). Is read out, the discrimination code is once set in the latch circuit (13) and taken into the CPU (2) through the data bus (3), and the character code and the attribute code are directly stored in the CPU (through the data bus (3) ( Incorporated in 2). On the other hand, at the OSD timing, when the video RAM (1) in the read state is accessed to the address corresponding to both data of the vertical position detection circuit (7) and the horizontal position detection circuit (8), the video RAM (1) of the video RAM (1) is read. The character code including the discrimination code or the attribute code is read from the address, the character code including the discrimination code is loaded into the character ROM (6), and the attribute code including the discrimination code is loaded into the attribute control circuit described later. (14) is the above-mentioned attribute control circuit, which takes in an attribute code when the timing switching signal C / O rises from a low level to a high level, decodes it, and outputs attribute control data for character modification for each display character. It occurs. (15) is an output processing circuit, which is a dot pattern data and attribute control circuit (1
The attribute control data output from 4) is subjected to signal processing to generate an RGB signal that can be displayed on the screen.

As described above, in the present embodiment, the latch circuit (1
The discrimination code is stored in 1), and then the latch circuit (1
The discrimination code held in 1) and the character code or attribute code output from the CPU (2) are connected and written in each address of the video RAM (1). Therefore, using the 8-bit CPU (2), the video R
By accessing AM (1) only once, the 9-bit contents obtained by connecting the discrimination code and the character code or the attribute code can be easily read. As a result, when the types of display characters are increased, the number of bits of the character code and the attribute code stored in the video RAM (1) can be increased, that is, the display information can be increased, and the video RAM (1) can be further increased. Access time can be shortened.

[0017]

According to the present invention, when the types of displayed characters are increased, the number of bits of the character code and the attribute code stored in the video RAM can be increased,
That is, it is possible to increase the display information, and further, it is possible to obtain an advantage that the access time of the video RAM can be shortened.

[Brief description of drawings]

FIG. 1 is a diagram showing a character display device of the present invention.

[Explanation of symbols]

 (1) Video RAM (2) CPU (11) Latch circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masaya Ota 2-18 Keihan Hondori, Moriguchi City, Osaka Prefecture Sanyo Electric Co., Ltd. (72) Inventor Shusaku Terawaki 2-18 Keihan Hondori, Moriguchi City, Osaka Sanyo Denki Within the corporation

Claims (2)

[Claims] 1. A character ROM in which a plurality of character data having a specific character font is stored, and a character code for accessing the character ROM is stored in an address corresponding to a display portion on a display panel, and the character is stored. And a video RAM in which an attribute code for modifying character data read from the character ROM according to the code is stored at the immediately preceding address, and a character display device for performing character display with character modification on the display panel is provided. A first means for generating a discrimination code for discriminating the character code and the attribute code, and a second means for holding and outputting the discrimination code, Connect the discrimination code and the character code to each address of the video RAM. A character display device for storing the continued contents and the contents of connecting the discrimination code and the attribute code. 2. The character display device according to claim 1, wherein the first means generates the character code, the attribute code, and the discrimination code at different timings.