JPH0626212B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JPH0626212B2
JPH0626212B2 JP61235605A JP23560586A JPH0626212B2 JP H0626212 B2 JPH0626212 B2 JP H0626212B2 JP 61235605 A JP61235605 A JP 61235605A JP 23560586 A JP23560586 A JP 23560586A JP H0626212 B2 JPH0626212 B2 JP H0626212B2
Authority
JP
Japan
Prior art keywords
layer
silicide
semiconductor device
atmosphere
unit process
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61235605A
Other languages
Japanese (ja)
Other versions
JPS6390154A (en
Inventor
信恭 北岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP61235605A priority Critical patent/JPH0626212B2/en
Publication of JPS6390154A publication Critical patent/JPS6390154A/en
Publication of JPH0626212B2 publication Critical patent/JPH0626212B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に高融点金属
あるいはその珪化物からなる半導体装置の製造方法に関
する。
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device made of a refractory metal or a silicide thereof.

〔従来の技術〕 従来、高融点金属あるいはその珪化物(以降シリサイド
と称す)を被着する工程とその後の熱処理工程とは独立
に行われていたので、その工程の途中で半導体基板表面
及び高融点金属あるいはそのシリサイドからなる半導体
表面が大気に晒されることがあった。
[Prior Art] Conventionally, the step of depositing a refractory metal or its silicide (hereinafter referred to as silicide) and the subsequent heat treatment step are performed independently of each other. The surface of a semiconductor made of a melting point metal or its silicide may be exposed to the atmosphere.

第3図(a),(b)は従来の半導体装置の製造方法の
一例を説明するための工程順に示した半導体チップの断
面図である。
FIGS. 3A and 3B are cross-sectional views of a semiconductor chip showing the order of steps for explaining an example of a conventional method for manufacturing a semiconductor device.

この従来例では、先ず、第3図(a)に示すように、シ
リコン基板1上に順次形成した酸化膜2及び多結晶シリ
コン膜3の上にチタン層4a′を形成した後、一旦大気
中に晒すことがあるのでチタン層4a′の表面に酸化物
層6が出来る。
In this conventional example, first, as shown in FIG. 3 (a), a titanium layer 4a 'is first formed on an oxide film 2 and a polycrystalline silicon film 3 which are sequentially formed on a silicon substrate 1 and then once in the atmosphere. Therefore, an oxide layer 6 is formed on the surface of the titanium layer 4a '.

次に、第3図(b)に示すように、酸化物層6を付けた
まま、熱処理を行い多結晶シリコン膜3とチタン層4
a′とを反応させてチタンシリサイド層4′を形成す
る。
Next, as shown in FIG. 3 (b), heat treatment is performed with the oxide layer 6 still attached, so that the polycrystalline silicon film 3 and the titanium layer 4 are formed.
The titanium silicide layer 4'is formed by reacting with a '.

この場合、表面の酸化物層6が存在するために、チタン
シリサイド層4′は不均一になりしかも層抵抗が高くな
る。
In this case, because of the presence of the oxide layer 6 on the surface, the titanium silicide layer 4'is non-uniform and the layer resistance is high.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上述した従来の半導体装置の製造方法では、高融点金属
あるいはそのシリサイドを被着する工程とその後の熱処
理工程とを独立に行いしかも途中で半導体基板が大気に
晒されていたので、高融点金属あるいはそのシリサイド
表面上に酸化物層が形成されたり、あるいは不純物が付
着する等して高融点金属あるいはそのシリサイドからな
る導体層が不均一でしかも層抵抗が高くなるという欠点
があった。
In the above-described conventional method for manufacturing a semiconductor device, the step of depositing the refractory metal or its silicide and the subsequent heat treatment step are performed independently, and the semiconductor substrate is exposed to the atmosphere during the process. An oxide layer is formed on the surface of the silicide, or impurities are attached to the surface of the silicide, so that the conductor layer made of the refractory metal or the silicide is nonuniform and the layer resistance is high.

又、導体層表面を熱処理前にフッ酸で処理しようとする
とチタンまで同時に除去されてしまうという問題もあっ
た。
Further, when the surface of the conductor layer is treated with hydrofluoric acid before the heat treatment, titanium is also removed at the same time.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の特徴は、半導体基板の上に高融点金属あるいは
その珪化物を被着した後に真空中又は不活性ガス雰囲気
中でランプアニールによる短時間熱処理を施し導体層を
形成する単位工程を少くとも一回含み、前記単位工程中
及び前記単位工程から前記単位工程までの間、その全期
間に亘って前記半導体基板を大気中に晒すことなく真空
中又は非酸化性ガス雰囲気中に保持する半導体装置の製
造方法にある。
A feature of the present invention is that at least a unit step of forming a conductor layer by depositing a refractory metal or a silicide thereof on a semiconductor substrate and then performing short-time heat treatment by lamp annealing in a vacuum or in an inert gas atmosphere. A semiconductor device that includes once and holds the semiconductor substrate in a vacuum or a non-oxidizing gas atmosphere without exposing the semiconductor substrate to the atmosphere during the unit process and from the unit process to the unit process for the entire period. In the manufacturing method.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明す
る。
Next, embodiments of the present invention will be described with reference to the drawings.

第1図(a)〜(c)は本発明の第1の実施例を説明す
るための工程順に示した半導体チップの断面図である。
1A to 1C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention.

この実施例は、先ず、第1図(a)に示すように、シリ
コン基板1の上に 500Åの酸化膜2及び3000Åの多結晶
シリコン膜3を順次形成する。
In this embodiment, first, as shown in FIG. 1A, a 500 Å oxide film 2 and a 3000 Å polycrystalline silicon film 3 are sequentially formed on a silicon substrate 1.

次に、第1図(b)に示すように、多結晶シリコン膜3
の表面をフッ酸で処理して大気中で出来た酸化膜を除去
した後真空蒸着法により、 500Åのチタン層4aを形成
する。
Next, as shown in FIG. 1B, the polycrystalline silicon film 3
After the surface of the above is treated with hydrofluoric acid to remove the oxide film formed in the atmosphere, a titanium layer 4a of 500 Å is formed by a vacuum evaporation method.

次に、第1図(c)に示すように、大気中に晒さずに連
続して真空中でハロゲンランプアニール法により 800
℃,15秒間加熱し、チタンシリサイド層4を形成する。
Next, as shown in Fig. 1 (c), 800 times was continuously applied in a vacuum by a halogen lamp annealing method without being exposed to the atmosphere.
The titanium silicide layer 4 is formed by heating at ℃ for 15 seconds.

第2図(a),(b)は本発明の第2の実施例を説明す
るための工程順に示した半導体チップの断面図である。
2A and 2B are cross-sectional views of the semiconductor chip shown in the order of steps for explaining the second embodiment of the present invention.

この実施例は、先ず、第2図(a)に示すように、シリ
コン基板1の上に酸化膜2及び多結晶シリコン膜3を順
次形成した後多結晶シリコン膜3の表面をフッ酸処理し
て、スパッタ法によりタングステンとシリコンの組成比
が1:3.5 のWS3.5 からなるタングステンシリサイド層
5aを1000Åの厚さで形成する。続いて、シリコン基板
1を大気中に晒すことなく真空中でハロゲンランプアニ
ール法により1000℃,10秒間加熱する。ここで、シリコ
ンの組成比の多いタングステンシリサイドを、先ず被着
したのは、下層の多結晶シリコン層3との密着性を良く
するためである。
In this embodiment, first, as shown in FIG. 2 (a), an oxide film 2 and a polycrystalline silicon film 3 are sequentially formed on a silicon substrate 1 and then the surface of the polycrystalline silicon film 3 is treated with hydrofluoric acid. Then, a tungsten silicide layer 5a made of WS 3.5 having a composition ratio of tungsten and silicon of 1: 3.5 is formed to a thickness of 1000 Å by a sputtering method. Then, the silicon substrate 1 is heated at 1000 ° C. for 10 seconds by a halogen lamp annealing method in vacuum without exposing it to the atmosphere. Here, the reason why the tungsten silicide having a large silicon composition ratio is first deposited is to improve the adhesion with the lower polycrystalline silicon layer 3.

しかし、このタングステンシリサイド層5aの層抵抗は
高いので、半導体基板1上のタングステンシリサイド層
5aの表面を大気に晒さずに、連続して、第2図(b)
に示すように、タングステンとシリコンの組成比が1:1.
8 とタングステンの組成比が多いWS1.8 からなるタン
グステンシリサイド層5bをスパッタ法により1000Åの
厚さで形成する。更に真空中でハロゲンランプアニール
法により、1000℃、10秒間の加熱をする。
However, since the layer resistance of the tungsten silicide layer 5a is high, the surface of the tungsten silicide layer 5a on the semiconductor substrate 1 is continuously exposed without being exposed to the atmosphere, as shown in FIG.
As shown in, the composition ratio of tungsten and silicon is 1: 1.
A tungsten silicide layer 5b made of WS 1.8 having a large composition ratio of 8 and tungsten is formed to a thickness of 1000 Å by a sputtering method. Further, it is heated in vacuum by a halogen lamp annealing method at 1000 ° C. for 10 seconds.

これにより低抵抗タングステンシリサイド層を形成で
き、シリサイド層の被着と熱処理との一連の工程で半導
体基板は、一度も大気にさらされないため、高純度なタ
ングステンシリサイド層が得られる。
Thus, a low-resistance tungsten silicide layer can be formed, and the semiconductor substrate is never exposed to the atmosphere in the series of steps of depositing the silicide layer and heat treatment, so that a high-purity tungsten silicide layer can be obtained.

なお、この実施例では、各シリサイド層を被着する毎に
ランプアニールを行っているが、勿論、シリサイド層全
部を先に被着した後にランプアニールを行っても良い。
In this embodiment, the lamp annealing is performed every time each silicide layer is deposited, but it goes without saying that the lamp annealing may be performed after depositing the entire silicide layer first.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明では、高融点金属あるいはそ
のシリサイドの被着と熱処理とを一連の真空中で行な
い、工程の途中で半導体基板の表面が大気に晒されない
ため、大気からの汚染を阻止すると共に高融点金属ある
いはそのシリサイドの表面上の酸化物層の形成も防止
し、均一でしかも層抵抗の低い導体層が安定に得られる
という効果がある。
As described above, in the present invention, the deposition of the refractory metal or its silicide and the heat treatment are performed in a series of vacuums, and the surface of the semiconductor substrate is not exposed to the atmosphere during the process, so that the contamination from the atmosphere is prevented. In addition, the formation of an oxide layer on the surface of the refractory metal or its silicide can be prevented, and a uniform conductor layer having a low layer resistance can be stably obtained.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)〜(c)及び第2図(a),(b)はそれ
ぞれ本発明の第1及び第2の実施例を説明するための工
程順に示した半導体チップの断面図、第3図(a),
(b)は従来の半導体装置の製造方法の一例を説明する
ための工程順に示した半導体チップの断面図である。 1……シリコン基板、2……酸化膜、3……多結晶シリ
コン膜、4,4′……チタンシリサイド層、4a,4
a′……チタン層、5a,5b……タングステンシリサ
イド層、6……酸化物層。
FIGS. 1A to 1C and FIGS. 2A and 2B are cross-sectional views of a semiconductor chip showing the order of steps for explaining the first and second embodiments of the present invention, respectively. Figure 3 (a),
(B) is sectional drawing of the semiconductor chip shown in order of process for demonstrating an example of the manufacturing method of the conventional semiconductor device. 1 ... Silicon substrate, 2 ... Oxide film, 3 ... Polycrystalline silicon film, 4, 4 '... Titanium silicide layer, 4a, 4
a '... titanium layer, 5a, 5b ... tungsten silicide layer, 6 ... oxide layer.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体基板の上に高融点金属あるいはその
珪化物を被着した後に真空中又は不活性ガス雰囲気中で
ランプアニールによる短時間熱処理を施し導体層を形成
する単位工程を少くとも一回含み、前記単位工程中及び
前記単位工程から前記単位工程までの間、その全期間に
亘って前記半導体基板を大気中に晒すことなく真空中又
は非酸化性ガス雰囲気中に保持することを特徴とする半
導体装置の製造方法。
1. A unit process of forming a conductor layer by depositing a refractory metal or a silicide thereof on a semiconductor substrate and then performing short-time heat treatment by lamp annealing in a vacuum or in an inert gas atmosphere to form a conductor layer. Including the above, the semiconductor substrate is kept in a vacuum or in a non-oxidizing gas atmosphere without being exposed to the atmosphere during the unit process and from the unit process to the unit process over the entire period. And a method for manufacturing a semiconductor device.
JP61235605A 1986-10-02 1986-10-02 Method for manufacturing semiconductor device Expired - Lifetime JPH0626212B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61235605A JPH0626212B2 (en) 1986-10-02 1986-10-02 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61235605A JPH0626212B2 (en) 1986-10-02 1986-10-02 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS6390154A JPS6390154A (en) 1988-04-21
JPH0626212B2 true JPH0626212B2 (en) 1994-04-06

Family

ID=16988483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61235605A Expired - Lifetime JPH0626212B2 (en) 1986-10-02 1986-10-02 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0626212B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100332127B1 (en) * 1995-06-30 2002-10-25 주식회사 하이닉스반도체 Method for forming conductive layer in semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59231836A (en) * 1983-06-14 1984-12-26 Toshiba Corp Formation of multilayer structural aluminum layer

Also Published As

Publication number Publication date
JPS6390154A (en) 1988-04-21

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