JPS61160952A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPS61160952A
JPS61160952A JP162985A JP162985A JPS61160952A JP S61160952 A JPS61160952 A JP S61160952A JP 162985 A JP162985 A JP 162985A JP 162985 A JP162985 A JP 162985A JP S61160952 A JPS61160952 A JP S61160952A
Authority
JP
Japan
Prior art keywords
melting point
silicide layer
point metal
high melting
polycrystalline silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP162985A
Other languages
Japanese (ja)
Inventor
Nobuyasu Kitaoka
北岡　信▲やす▼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP162985A priority Critical patent/JPS61160952A/en
Publication of JPS61160952A publication Critical patent/JPS61160952A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain the titled device having a uniform, gentle silicide layer, by a method wherein a high melting point metal is made to react with polycrystalline Si by lamp annealing. CONSTITUTION:A gate oxide film 2 is provided on an Si substrate 1, and a polycrystalline Si 3 is provided thereon. Then, the polycrystalline Si is coated with a layer 4 of a high melting point metal such as Ti. Thereafter, As is introduced into the Ti and the polycrystalline Si. Then, the Ti is made to react with the polycrystalline Si by lamp annealing into a uniform, gentle thin silicide layer 101. This silicide layer is coated with a Ti 102, which are then formed into a uniform, gentle silicide layer 103 of desired film thickness by lamp annealing. As the high melting point metal, Mo, Ta, W, or Ti is used.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に高法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a high-speed method.

〔従来の技術〕[Conventional technology]

従来、高融点金属のシリサイド層を有する電極配線は高
融点金属を多結晶シリコン上に薄く被着させイオン注入
法によりイオン種を高融点金属と多結晶シリコン中に導
入し、炉アニールにより高融点金属を多結晶シリコンと
反応させていた。Conventionally, electrode wiring having a silicide layer of a high-melting point metal is made by thinly depositing a high-melting point metal on polycrystalline silicon, introducing ion species into the high-melting point metal and polycrystalline silicon using an ion implantation method, and then increasing the high-melting point by furnace annealing. The metal was reacting with polycrystalline silicon.

第５図から第８図により従来の高融点金属のシリサイド
Ｗ／Ｉを有する電極配線の形成法の一例を示す。5 to 8 show an example of a conventional method of forming an electrode wiring having a silicide W/I of a high melting point metal.

第５図において、ｌはシリコン基板、２はゲート酸化膜
、３は多結晶シリコン、４は被着されたチタンである。In FIG. 5, l is a silicon substrate, 2 is a gate oxide film, 3 is polycrystalline silicon, and 4 is deposited titanium.

これにヒ素をイオン注入法によりチタンと多結晶シリコ
ン中に導入し、その後炉アニールによりチタ／′！ｉＩ
−多結晶シリコンと反応させて薄いシリサイド層１）を
形成する（第６図）。その後シリサイド層ｌｌ上にチタ
ｙｔ　ｚｔ被着しく第７図）、熱処理により望みの膜厚
のシリサイド層１３を形成していた（第８図）。Arsenic was then introduced into the titanium and polycrystalline silicon by ion implantation, and then furnace annealed to titanium/'! iI
- forming a thin silicide layer 1) by reaction with polycrystalline silicon (FIG. 6); Thereafter, titanium was deposited on the silicide layer 11 (FIG. 7), and a silicide layer 13 having a desired thickness was formed by heat treatment (FIG. 8).

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の高融点金属のシリサイド層を有する電極
配線の形成方法は、薄く被着した高融点金属を炉アニー
ル法で熱処理をして高融点金属の７リサイド層を形成し
ていたため、このシリサイド層と多結晶クリコンの界面
及びシリサイド層の表面はなめらかＫなシにくかった。The conventional method for forming electrode wiring having a silicide layer of a high melting point metal described above involves heat treating a thinly deposited high melting point metal using a furnace annealing method to form a 7 silicide layer of a high melting point metal. The interface between the layer and polycrystalline silicon and the surface of the silicide layer were difficult to smooth.

そのため、このなめらかでないシリサイド層の上に高融
点金属を被着し、熱処理により所望の膜厚のシリサイド
層を形成してもなめらかなりリサイド層を得ることが困
難であった。すなわち、はじめに薄くなめらからシリサ
イド層を形成することにょシ、なめらかな所望の膜厚の
シリサイド層を形成しようとする方法が効果的でなかつ
九。Therefore, even if a high melting point metal is deposited on top of this uneven silicide layer and a silicide layer of a desired thickness is formed by heat treatment, it is difficult to obtain a smooth silicide layer. That is, the method of forming a smooth silicide layer of a desired thickness by first forming a thin and smooth silicide layer is not effective.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の目的は高融点金属のシリサイド層を有する電極
配線において均一でなめらかなりリサイド層を形成する
ことができる半導体装置の製造方法を提供するにある。An object of the present invention is to provide a method for manufacturing a semiconductor device that can form a uniform and smooth silicide layer in an electrode wiring having a silicide layer of a refractory metal.

本発明の製造方法は、電極配線に高融点金属の７リサイ
ド層を有する半導体装置の製造方法において、多結晶シ
リコン上に高融点金属を薄く被着する工程と、イオン注
入法によりイオン種を前記高融点金属と多結晶シリコン
中に導入する工程と、前記高融点金属と前記多結晶シリ
コンをうｙグアニール法により反応させ均一でなめらか
な高融点金属のシリサイド層を形成する工程と、その後
シリサイド層上に高融点金属をさらに被着し、ランプア
ニール法または炉アニール法により所望の膜厚のシリサ
イド層を形成することＫある。The manufacturing method of the present invention is a method for manufacturing a semiconductor device having seven recidivated layers of high-melting point metal in electrode wiring, and includes a step of thinly depositing a high-melting point metal on polycrystalline silicon, and an ion implantation method to inject ion species into the semiconductor device. A step of introducing a high melting point metal into polycrystalline silicon, a step of reacting the high melting point metal and the polycrystalline silicon to form a uniform and smooth silicide layer of the high melting point metal, and then forming a silicide layer. A refractory metal may be further deposited thereon, and a silicide layer having a desired thickness may be formed by lamp annealing or furnace annealing.

〔実施例〕〔Example〕

次に本発明の実施例を第１図から第４図により説明する
。Next, embodiments of the present invention will be described with reference to FIGS. 1 to 4.

第１図は本発明の一実施例の工程途中段階の断面図であ
る。すなわちシリコン基板ｌＯ上にゲート酸化膜２ｔ−
設けその上に多結晶クリコン３を設ける。そして多結晶
シリコン上にスバ、タリング法によりチタン層４を２０
０〜４００　Ｘ被着させる。FIG. 1 is a cross-sectional view of an embodiment of the present invention at an intermediate stage in the process. That is, a gate oxide film 2t- is formed on the silicon substrate lO.
A polycrystalline crystal 3 is provided thereon. Then, a titanium layer 4 is deposited on the polycrystalline silicon with a thickness of 20 mm by a rolling method.
Deposit 0-400X.

その後ヒ素ｔ　ｔ　ｏ　ｏ　Ｋｅ　Ｖ　ｔ　ｓ　ｘ　１
０１ｓｃＩＬ−２の条件でイオン注入法によりチタンと
多結晶シリコン中に導入する。その後ランプアニール法
により、チタンと多結晶シリコンを７００℃３０秒で反
応させ均一でなめらかな薄いシリサイド層１０１　を形
成する（第２図）。Then arsenic t t o Ke V t s x 1
It is introduced into titanium and polycrystalline silicon by ion implantation under the conditions of 01scIL-2. Thereafter, by lamp annealing, titanium and polycrystalline silicon are reacted at 700° C. for 30 seconds to form a uniform and smooth thin silicide layer 101 (FIG. 2).

この均一でなめらかなりリサイド層上にチタン１０２　
ｔａｏｏｏｌスバ、クリング法で被着する（第３図）。Titanium 102 is applied on this uniform and smooth reside layer.
Taool Suba is applied using the Kling method (Figure 3).

その後ランプアニール法により７００’Ｃ３０秒の条件
で均一でなめらかな所望の膜厚のシリサイド層１０３　
ｔ−形成する（第４図）。After that, a uniform and smooth silicide layer 103 with a desired thickness is obtained by lamp annealing at 700'C for 30 seconds.
t-form (Figure 4).

〔発明の効果〕〔Effect of the invention〕

従来方法でははじめに薄く被着した高融点金属と多結晶
シリコンとを炉アニール法により反応させていたため均
一でなめらかなシリサイド層を得ることが困難であった
が、本発明によればこの炉アニール法ｔランプアニール
法により行なうので均一でなめらかなりリサイド層を容
易に得ることができ、このため、このシリサイド層上に
高融点金属を被着し熱処理により所望の膜厚のシリサイ
ド層を形成するのに均一でなめらかなシリサイド層を形
成できる効果がある。In the conventional method, it was difficult to obtain a uniform and smooth silicide layer because the thinly deposited high melting point metal and polycrystalline silicon were first reacted by a furnace annealing method, but according to the present invention, this furnace annealing method Since the t-lamp annealing method is used, a uniform and smooth silicide layer can be easily obtained. Therefore, it is possible to deposit a high melting point metal on the silicide layer and form a silicide layer of the desired thickness by heat treatment. It has the effect of forming a uniform and smooth silicide layer.

【図面の簡単な説明】[Brief explanation of drawings]

第１図から第４図は本発明の一実施例の工程途中の断面
図であシ、第５図から第８図はシリサイド層を有する電
櫨配を形成する従来の形成方法の断面図である。 尚、図において、 ｌ・・・・−・シリコン基板、２・・・・・・ゲート鹸
化膜、３・・・・・・多結晶シリコン、４，１２，１０
２・旧・・チタン、１）．１３，１０１，１０３・・・
用チタンシリサイド層である。FIGS. 1 to 4 are cross-sectional views of an embodiment of the present invention during the process, and FIGS. 5 to 8 are cross-sectional views of a conventional method of forming an electric grid having a silicide layer. be. In the figure, 1...--Silicon substrate, 2... Gate saponification film, 3... Polycrystalline silicon, 4, 12, 10
2. Old...Titanium, 1). 13,101,103...
titanium silicide layer.

Claims (2)

【特許請求の範囲】[Claims] （１）電極配線に高融点金属のシリサイド層を有する半
導体装置の製造方法において、多結晶シリコン上に高融
点金属を被着し、イオン注入法によりイオン種を前記高
融点金属と前記多結晶シリコン中に導入し、その後ラン
プアニール法により、高融点金属のシリサイド層を形成
する工程と、該高融点金属のシリサイド層上にさらに高
融点金属を被着させ、ランプアニール法または炉アニー
ル法により高融点金属のシリサイド層を形成する工程を
含むことを特徴とする半導体装置の製造方法。(1) In a method for manufacturing a semiconductor device having a silicide layer of a high-melting point metal in electrode wiring, a high-melting point metal is deposited on polycrystalline silicon, and ion species are introduced into the high-melting point metal and the polycrystalline silicon by an ion implantation method. There is a step of forming a silicide layer of a high melting point metal using a lamp annealing method, and further depositing a high melting point metal on the silicide layer of the high melting point metal, followed by a step of forming a high melting point metal silicide layer using a lamp annealing method or a furnace annealing method. A method for manufacturing a semiconductor device, comprising the step of forming a silicide layer of a melting point metal. （２）高融点金属はモリブデン、タンタル、タングステ
ンもしくはチタンを用いることを特徴とする特許請求の
範囲（１）項記載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim (1), wherein the high melting point metal is molybdenum, tantalum, tungsten, or titanium.
JP162985A 1985-01-09 1985-01-09 Manufacture of semiconductor device Pending JPS61160952A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP162985A JPS61160952A (en) 1985-01-09 1985-01-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP162985A JPS61160952A (en) 1985-01-09 1985-01-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61160952A true JPS61160952A (en) 1986-07-21

Family

ID=11506825

Family Applications (1)

Application Number Title Priority Date Filing Date
JP162985A Pending JPS61160952A (en) 1985-01-09 1985-01-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61160952A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63128732A (en) * 1986-11-19 1988-06-01 Sanyo Electric Co Ltd Formation of metallic silicide film
US5217924A (en) * 1989-05-12 1993-06-08 Texas Instruments Incorporated Method for forming shallow junctions with a low resistivity silicide layer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63128732A (en) * 1986-11-19 1988-06-01 Sanyo Electric Co Ltd Formation of metallic silicide film
JP2522924B2 (en) * 1986-11-19 1996-08-07 三洋電機株式会社 Method for forming metal silicide film
US5217924A (en) * 1989-05-12 1993-06-08 Texas Instruments Incorporated Method for forming shallow junctions with a low resistivity silicide layer

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