JPH06260898A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunction by making a threshold voltage at the time of rising an input signal higher than a supply voltage for the signal input higher than the power supply to increase the difference between the signal input higher than the threshold voltage and the input signal low potential and stopping flowing-in of a steady state current. CONSTITUTION:If the input potential of a terminal 21 exceeds 3.5V at the time of rising input signal, the input end potential of a buffer 3 exceeds threshold voltage 1.5V of an inverter 4, and the output of the inverter 4 goes to 0V, and an NMOS transistor TR 2 is turned off, and it becomes the input potential of the terminal 21. That is, when the input potential is 5V, a current does not flow in from the terminal 21 because the TR 2 is turned off. At the time of falling, the input end potential of the buffer 3 becomes the input potential of the terminal 21 because the TR 2 is turned off at the beginning. When the terminal 21 is <=1.5V, the input end potential of the buffer 3 is lower than threshold value of 1.5V, and the output of the inverter 4 goes to 3V, and the TR 2 is turned on, and it is the same potential as the initial stage of the rising. Thus, the malfunction is prevented without increasing the current consumption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a Schmitt buffer included in a conventional semiconductor integrated circuit, a conventional example is shown in FIGS. 5 and 6 as an example in which an input voltage higher than a power supply voltage is input. FIG. 5 shows the configuration of the Schmitt buffer in the first conventional example, and the power supply voltage is 3V.
Is supplied, an inverter having a high threshold voltage (threshold voltage is 2V) 7, an inverter having a low threshold voltage (threshold voltage is 1V) 8, inverters 9 and 12,
This is an example in which an input signal having a potential of 5V higher than the power supply voltage 3V is directly input to the external input terminal 21 of the Schmitt buffer, which is configured by including the NAND circuits 10 and 11. Corresponding to the voltage level of this input signal,
The voltage level of the signal output from the internal terminal 22 is shown in FIG.
As shown in the input / output characteristics of. That is, when the potential level of the input signal is 0V, the output level of the inverter 9 is 0V, and the potential level of the output signal output from the internal terminal 22 is 0V. Further, when the input potential of the external terminal 21 rises from 0V to the maximum input potential, that is, 5V, if the input potential exceeds the threshold voltage 2V of the high threshold inverter 7, the output potential of the inverter 7 is increased. Is 0V
Therefore, the output potential level of the NAND circuit 10 becomes 3V of the power source potential itself, and the output level of the inverter 9 also becomes 3V.
The output potential of the internal terminal 22 is also 3V.
Becomes When the potential of the input signal of the external terminal 21 further falls from 5V to 0V, if the potential level falls below the threshold voltage of the low threshold voltage inverter 8,
The output level of the inverter 9 becomes 0V, and thus the output potential of the internal terminal 22 also becomes 0V.

The second conventional example shown in FIG. 6 is different from the first conventional example described above in that the Schmitt buffer 1 having the same structure as the Schmitt buffer shown in FIG.
6, the NMOS transistor 13, the PMOS transistor 14 and the NMOS transistor 15 are connected to the input terminal of the Schmitt buffer 16 as shown in FIG. Also in this conventional example, similarly, 3V is supplied as the power supply voltage, and the input signal having the potential of 5V higher than the power supply voltage 3V is supplied to the Schmitt buffer 16 via the NMOS transistor 13, the PMOS transistor 14 and the NMOS transistor 15. Shall be input to the input terminal of. A power supply voltage is supplied from the power supply terminal 23 to the gate of the NMOS transistor 15.

In this conventional example, the relationship of the potential output to the input terminal of the Schmitt buffer 16 in accordance with the voltage level of the input signal at the external terminal 21 is as shown in the input / output characteristics of FIG. . That is, since both the PMOS transistor 13 and the NMOS transistor 15 are in the ON state, when the potential level of the external terminal 21 is equal to or lower than the threshold voltage V _T of the NMOS transistor 13,
The NMOS transistor 13 is turned off and the input terminal potential of the Schmitt buffer 16 becomes 0V. Further, when the input potential of the external terminal 21 is equal to or higher than the threshold voltage V _{T of the} NMOS transistor 13, the potential lower than the input potential of the external terminal 21 by the threshold voltage V _T of the NMOS transistor 13 is the source of the PMOS transistor 14. Is applied to the on-state resistance value of the PMOS transistor 14 and the NM
The potential divided by the ON resistance value of the OS transistor 15 becomes the input end potential to the Schmitt buffer 16. Therefore, as the input / output characteristic of the conventional example, as shown in FIG. 9, the input / output characteristic of the Schmitt buffer 16 is the same as the characteristic shown in FIG.
The input potential of the external terminal 21 rises from 0V to 3V. If the input potential of the external terminal 21 falls below 1.5V at the fall, the input end potential of the Schmitt buffer 16 is 1V.
And the output potential at the internal terminal 22 is from 3V to 0.
It is output after falling to V.

[0005]

In the Schmitt buffer in the conventional semiconductor integrated circuit described above, the structure shown in FIG.
In the case of the first conventional example shown in (1), the threshold voltage at the rising time is the threshold voltage itself of the high threshold inverter 7, and this threshold voltage is higher than the power supply voltage. Since the potential is low, even a noise having a peak value of the input signal of about 2 V cannot be prevented, which causes a malfunction.

Further, in the case of the second conventional example shown in FIG. 6, when the input signal is in the high potential state, N
Since the MOS transistor 13, the PMOS transistor 14, and the NMOS transistor 15 are all turned on, and the current constantly flows in from the external terminal 21, there is a disadvantage that the current consumption increases unnecessarily.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit having a Schmitt buffer to which an input signal having a voltage level higher than a power supply voltage is applied. Of the Schmitt buffer, the other end of which is connected to the input terminal of a buffer included in the Schmitt buffer, first and second inverters which are connected in cascade to form the buffer, and the drain of which is An NMOS transistor connected to an input terminal of the buffer, a source connected to a ground potential, and a gate connected to a connection point between the output terminal of the first inverter and the input terminal of the second inverter; It is characterized in that the output terminal of the buffer is configured as an output terminal.

The semiconductor integrated circuit of the second invention is a semiconductor integrated circuit having a Schmitt buffer to which an input signal having a voltage level higher than the power supply voltage is applied, and the Schmitt buffer has a drain and a gate connected to each other. An NMOS transistor connected to a predetermined external input terminal, having a source connected to an input terminal of a buffer included in the Schmitt buffer and acting as a transfer gate, and connected in cascade to form the buffer.
And a second inverter, a drain is connected to the input end of the buffer, a source is connected to the ground potential, and a gate is a connection point between the output end of the first inverter and the input end of the second inverter. And an NMOS transistor connected to the buffer, and the output terminal of the buffer is configured as an output terminal.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the structure of a Schmitt buffer according to the first embodiment of the present invention. As shown in FIG. 1, the Schmitt buffer has a resistance element 1 corresponding to the external terminal 21 and the output terminal 22.
And an NMOS transistor 2 functioning as a pull-down resistor, and a buffer 3 including inverters 4 and 5. Also in the Schmitt buffer in the case of the present embodiment, 3V is supplied as the power supply voltage, and an input signal of 5V, which is higher than the power supply voltage, is input to the external terminal 21. In this embodiment,
The resistance value of the resistance element 1 is 40 kΩ, and the ON resistance value of the NMOS transistor forming the pull-down resistance is 3
It is 0 kΩ. The threshold voltages of the inverters 4 and 5 forming the buffer 3 are 1.5V, respectively.

In FIG. 1, the input / output relationship between the input potential of the external terminal 21 and the input end potential of the buffer 3 is as shown in FIG. That is, when the input potential of the external terminal 21 is 0 V, the buffer 3 connected via the resistance element 1
The input terminal potential of is also 0V and the output of the inverter 4 is 3V.
Then, the NMOS transistor 2 is turned on. At this time, the NMOS transistor 2 is in the ON state, but since the input potential of the external terminal 21 and the ground potential are at the same potential, the steady current from the external terminal 21 does not flow into the Schmitt buffer. Absent.

Next, when the input signal rises,
The input terminal potential of the buffer 3 is initially a voltage divided by the resistance value of the resistance element 1 of 40 kΩ and the pull-down resistance value of 30 kΩ by the ON resistance of the NMOS transistor 2, and thus is 4/7 times the input potential of the external terminal 21. It becomes the electric potential of. When the input potential of the external terminal 21 exceeds 3.5V, the input terminal potential of the buffer 3 exceeds the threshold voltage 1.5V of the inverter 4, and the output of the inverter 4 becomes 0V.
Since the NMOS transistor 2 is turned off, it reaches the input potential of the external terminal 21. Therefore, the external terminal 21
When the input potential is high, that is, when the input potential is 5 V, the current does not flow from the external terminal 21 because the NMOS transistor 2 is off. Further, at the time of the fall, the input terminal potential of the buffer 3 is initially in the state where the NMOS transistor 2 is off,
It becomes the potential of the input potential itself of the external terminal 21. When the potential of the external terminal 21 falls below 1.5V, the input end potential of the buffer 3 falls below the threshold voltage 1.5V of the inverter 4, the output of the inverter 4 becomes 3V, and the NMOS transistor 2 is turned on. Therefore, the potential is 4/7 times the input potential of the external terminal 21 as in the case of the initial state when rising. Therefore, as shown in FIG. 4, the input / output characteristics of this embodiment are such that when the input potential of the external terminal 21 rises above 3.5V, the 3V output of the inverter 4 falls to the 0V output. The output potential at the internal terminal 22 rises from 0V to 3V.
When the voltage falls below 1.5V at the fall, the inverter 4 rises from 0V output to 3V output, so the internal terminal 2
The output potential of 2 drops from 3V to 0V and is output.

Next, FIG. 2 shows the second embodiment of the present invention.
3 is a circuit diagram showing a configuration of a Schmitt buffer in the embodiment of FIG. As shown in FIG. 2, the structure of the Schmitt buffer corresponding to the external terminal 21 and the output terminal 22 has an on-resistance value of 40 kΩ and a threshold voltage of 0 V.
Transfer gate 6 of NMOS depletion transistor configuration and NM functioning as pull-down resistor
It is configured to include an OS transistor 2 and a buffer 3 including inverters 4 and 5. The difference of this embodiment from the first embodiment is that the transfer gate 6 is connected between the external terminal 21 and the input terminal of the buffer 3 as a substitute for the resistance element. The other circuit configuration is exactly the same as that of the first embodiment.
In the case of this embodiment, the use of the resistance element is unnecessary, and the MO
With the circuit configuration of only the S transistor, it is possible to obtain the same input / output characteristics as in the case of the Schmitt buffer of the first embodiment described above. Further, as in the case of the first embodiment, the steady current does not flow in, and the current consumption is reduced.

[0014]

As described above, the Schmitt buffer according to the present invention makes the threshold voltage at the rising edge of the input signal higher than the power supply voltage in response to the signal input having a voltage level higher than the power supply voltage. By increasing the potential difference between the input signal and the low potential, and configuring the Schmitt buffer so that a steady current does not flow from the external terminal, a high peak value can be applied to the input signal without increasing the current consumption. Even in the state where the noise is generated, it is possible to prevent the malfunction.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram showing input / output characteristics of an external input potential and a buffer input end potential in the above embodiment.

FIG. 4 is a diagram showing input / output characteristics of an external input potential and an internal output potential in the above embodiment.

FIG. 5 is a circuit diagram showing a first conventional example.

FIG. 6 is a circuit diagram showing a second conventional example.

FIG. 7 is a diagram showing input / output characteristics of an external input potential and an internal output potential in the first conventional example.

FIG. 8 is a diagram showing input / output characteristics of an external input potential and a Schmitt buffer input end potential in the second conventional example.

FIG. 9 is a diagram showing input / output characteristics of an external input potential and an internal output potential in the second conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 resistance element 2, 6, 13, 15 NMOS transistor 3 buffer 4, 5, 7, 7-9, 12 inverter 10, 11 NAND circuit 14 PMOS transistor 16 Schmitt buffer

Claims (2)

[Claims] 1. A semiconductor integrated circuit having a Schmitt buffer to which an input signal having a voltage level higher than a power supply voltage is applied, wherein the Schmitt buffer has one end connected to a predetermined external input terminal and the other end connected to the Schmitt buffer. A resistor element connected to the input terminal of the buffer, first and second inverters connected in series to form the buffer, a drain connected to the input terminal of the buffer, and a source connected to the ground potential. And an NMOS transistor having a gate connected to a connection point between the output terminal of the first inverter and the input terminal of the second inverter, and the output terminal of the buffer is configured as an output terminal. A characteristic semiconductor integrated circuit. 2. In a semiconductor integrated circuit having a Schmitt buffer to which an input signal having a voltage level higher than a power supply voltage is applied, the Schmitt buffer is connected to a predetermined external input terminal with a drain and a gate connected, and a source. Is connected to an input terminal of a buffer included in the Schmitt buffer and functions as a transfer gate, an NMOS transistor, first and second inverters connected in cascade to form the buffer, and a drain connected to an input terminal of the buffer. An NMOS transistor having a source connected to a ground potential and a gate connected to a connection point between the output terminal of the first inverter and the input terminal of the second inverter, and the output terminal of the buffer. A semiconductor integrated circuit characterized by being configured as an output terminal.