JPH06260556A - Wiring method of integrated circuit - Google Patents

Abstract

PURPOSE:To simultaneously enable the wiring of an unwired network and the rewiring of a peeled net, in a peeling and rewiring process. CONSTITUTION:When an unwired network A is generated, an obstacle portion which causes the unwiring is decided. A network B which occupies the portions is peeled (steps 1, 2, 3, 4). In order to find a route which does not pass the obstacle portions, a large cost is given to the obstacle portion, and the network B is drawn afresh. After that, the wiring of the network A which has not been completed by the initial wiring is performed (steps 5, 6, 7).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit wiring method.

[0002]

2. Description of the Related Art In the wiring design of an integrated circuit, there are a method of collectively wiring a plurality of nets and a method of wiring one net at a time. It may interfere with the net to be routed and the subsequent net may not be routed. Conventionally, as a technique for solving this, there is a peeling rewiring method. For example,
Institute of Electronics, Information and Communication Engineers Technical Report VLD 89-116 "Peeling and rewiring method based on distance from design violation position". In FIG. 4, when a certain net A cannot be wired without violating the design, the existing wiring B which is the obstacle is peeled off, the wiring order is reversed, and the net A is wired first. The method is to wire the net B later.

That is, as shown in FIG. 4, if there is an unrouted net in step 8, the process proceeds to step 9, and if there is no unrouted net, the process ends 30. In step 10, if the net A cannot be routed, the process returns to step 11, and if it can, the process returns to step 8. In step 11, the faulty net B is peeled off, the net A is wired in step 12, then the net B is wired in step 13, and the process returns to step 8.

[0004]

However, in this method, since the rewiring route of the net B is not considered at all when the wiring of the net A is performed first, the wiring of the net A conversely routes the net B. May be an obstacle when you do. In this case, the net A is peeled off again in order to wire the net B, or the base wirings of other nets are peeled off. Therefore, this method has a drawback that many peeling and rewirings are required and wiring processing time becomes long.

Thus, in the conventional method, the wiring process is continued as long as there is an unwired net (step 8). Unrouted net A cannot be routed (steps 9 and 1)
If 0), the faulty part is detected and the faulty net is peeled off (step 11). Although the net A is immediately routed after this, the reroute route of the net B is not taken into consideration at this time, so that the net B may not be routed after the net A is routed.

It is an object of the present invention to provide a wiring method for an integrated circuit which solves the above-mentioned drawbacks and requires a short wiring processing time.

[0007]

The structure of the wiring method for an integrated circuit according to the present invention has a wiring process for observing design rules at a minimum cost between desired terminals and a case where a desired wiring route cannot be obtained. The process to detect the faulty point and the existing wiring that passes through it, the process to reroute the faulty line by giving a large cost to the faulty point, and the wiring route could not be obtained first. And a process for wiring a net.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a flow chart showing a wiring method of an integrated circuit according to an embodiment of the present invention.

In FIG. 1, in this embodiment, if there is an unwired net of the integrated circuit (step 1), the process goes to the next step 2, and if there is no unfinished net, the process ends 30. In step 2, the unrouted net A is routed. If the net A cannot be routed in the next step 3, the process returns to the next step 4, and if it is possible, the process returns to step 1. In Step 4, failure net B
Is peeled off, and then the cost is given to the obstacle in step 5. Then, in step 6, the net B is wired, and then the net A is wired (step 7). Then, return to step 1 again and repeat.

The wiring process continues as long as there is an unwired net (step 1). When the unrouted net A cannot be routed (steps 2 and 3), the fault location is detected, the fault net is peeled off (step 4), and a large cost is given to the fault location (step 5) to route the fault net B. Redo. Since a large cost is given to the failure point, a route of the net B that does not pass through the failure point can be obtained. Therefore, the obstacle to the net A is removed, and the subsequent wiring process of the net A (step 7) is successful.

The major difference between the conventional method (FIG. 4) and the method of this embodiment (FIG. 1) is that the wiring of the net A is performed before the wiring of the net B in the conventional method, whereas In the method of the embodiment, the net B is wired before the net A.

That is, the feature is that the wiring which is the obstacle is redrawn first.

The following conventional method can be used for the process of finding the wiring route used in this embodiment. A cost is given to each wirable position (called a wiring grid) for each layer and for each traveling direction. The cost is set so that the better the wiring route, the smaller the total cost of the lattices passing through. The wiring process finds the path with the lowest cost. For example, the document “A Detailed Ro
uter Basedon Incremental
Routing Modifications: Mi
ghtyl (IEEE Transaction on
Computer-Aided Design, Vo
l. CAD-6, No. 6, 1987).

Next, a specific wiring example of this embodiment will be described with reference to FIGS. 2 and 3 showing wiring paths. In FIG. 2 (A),
The time when the net A (the net connecting the terminals 15 and 16) is unwired is shown. Second wiring layer downward from the terminal 15 of the net A (mainly used for vertical wiring)
When you scan, you will come across the wiring of net B14,
It is determined that the second layer wiring of the net B14 is an obstacle in wiring the net A.

FIG. 3A shows a state in which the cost of the second layer is set at the fault position and the net B is re-routed.
The area 18 in FIG. 3A is an area to which a large cost is added, and the wiring path 19 of the net B does not use the cost-added second layer but uses the first layer. In this example, if a value larger than (cost in the first layer in the vertical direction)-(cost in the second layer in the vertical direction) is used as the added cost value, the route 19 in FIG. Found as a cost path.

FIG. 3B is a wiring diagram after the wiring of the net A is further performed. Since the additional cost is removed before the wiring of the net A, the net A can use this area and can perform wiring as the wiring route 20 of FIG. 3B.

Here, what kind of method is conventionally used will be described with reference to FIG.

FIG. 2B is a wiring diagram when the conventional method is applied in the state of FIG. In FIG. 2 (B),
In the conventional method, the net A is wired immediately after the net B is peeled off. As a result, the net A is routed through the route such as the routing route 17, and this time, on the contrary, it becomes an obstacle in routing the net B.

[0019]

As described above, according to the peeling wiring method of the present invention, when an unwired net occurs, the cost of the part which is an obstacle to the net is increased and By redrawing the occupied nets, both the current unrouted wiring and the rerouting of the faulty wiring to be peeled off can be performed, reducing the number of peeling and rewiring, This has the effect of shortening the time.

[Brief description of drawings]

FIG. 1 is a flowchart showing a wiring method of an integrated circuit according to an embodiment of the present invention.

2A and 2B are wiring diagrams showing the wiring method of FIG. 1 and a conventional wiring method, respectively.

3A and 3B are wiring diagrams sequentially showing a post-process of the wiring method of FIG.

FIG. 4 is a flowchart showing a wiring method of a conventional integrated circuit.

[Explanation of symbols]

 1 to 13 Process Steps in Flowchart 14 Wiring for Net B 15,16 Net A Terminals 17, 19, 20 Wiring Path 18 Area with Cost Added

Claims (2)

[Claims] 1. A wiring process for observing a design rule and wiring at a minimum cost between desired terminals, and when a desired wiring route cannot be obtained by the wiring process, an obstacle point and a passage therethrough are passed. The process of detecting the existing wiring, the process of re-wiring the faulty wiring by giving a large cost to the faulty place, and the process of wiring the net for which the wiring route is not obtained first. A wiring method for an integrated circuit characterized by being provided. 2. The wiring method for an integrated circuit according to claim 1, wherein the wiring which is the obstacle is redrawn first.