JP3560451B2 - Layout method of semiconductor integrated circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a layout method for a semiconductor integrated circuit, and more particularly, to a layout method for a semiconductor integrated circuit designed using a computer.
[0002]
[Prior art]
2. Description of the Related Art In recent years, in the field of semiconductor integrated circuits, high-mix low-volume production has been remarkable, and shortening of the development and manufacturing period is required. Therefore, in the layout design of a semiconductor integrated circuit, automation of the layout design using a computer has been advanced. Hereinafter, a layout method of a semiconductor integrated circuit according to the related art will be described.
[0003]
FIG. 14 shows a flowchart of a wiring step in a layout method of a semiconductor integrated circuit according to the related art. According to the prior art, first, in step 1401, one net for which wiring has not been completed is selected. Next, in step 1402, wiring is performed between terminals connected to the selected net. Next, in step 1403, it is determined whether or not wiring of all nets has been completed. If the wiring of all nets has not been completed (if “No” is determined in step 1403), the process returns to step 1401 to perform the wiring process again, and the wiring of all nets has been completed. If it is determined ("Yes" in step 1403), the wiring process ends.
[0004]
In the wiring step in the above-described conventional semiconductor integrated circuit layout method, a method of wiring the shortest path between terminals of elements connected to each net at once using a maze method or the like is mainly used. Is being done.
[0005]
[Problems to be solved by the invention]
However, in the above-described layout method according to the related art, when wiring is performed on a semiconductor integrated circuit having a fixed wiring region as in the master slice method, the wiring region cannot be expanded. When wiring is performed by a route, wiring concentrates on a congested portion of an element, and a wiring to be performed later cannot pass. Therefore, there is a problem that a non-wiring area occurs and the number of unwired wirings increases.
[0006]
When wiring is performed using the maze method, since the maze method is a method of wiring the shortest path, the wiring is likely to be bent. If the wiring is bent too much, there is a high possibility that the wiring will be an obstacle to other wirings, and a non-wiring area will be generated. As a result, the number of unwired wirings will increase. Furthermore, since the maze method requires a large amount of calculation time, applying the maze method to the entire semiconductor integrated circuit requires a very long calculation time.
[0007]
Therefore, the present invention has been made to solve such a problem, and when wiring is performed on a semiconductor integrated circuit having a fixed wiring region as in a master slice method, the wiring is bent. Can reduce the number of unwired areas by reducing the number of unwired areas.On the other hand, when wiring is performed using the maze method, the applicable range should be limited. A method of laying out a semiconductor integrated circuit that can reduce the number of unwired areas by reducing the number of unroutable areas by reducing wiring detours, and at the same time, shorten the calculation time The purpose is to provide. In other words, an object of the present invention is to provide a layout method of a semiconductor integrated circuit that can obtain a semiconductor integrated circuit with few unwired portions in a short time.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a semiconductor integrated circuit layout method for wiring a plurality of element terminals provided in each unit constituting a semiconductor integrated circuit. A main line forming step of forming a main line in a non-obstruction-free straight-line region, a main line extending step of extending the main line to an unobstructed region in the wiring region, and a wiring for electrically connecting the main line to the element terminals And an unnecessary trunk line removing step of removing an unnecessary portion of the trunk line that does not contribute to the wiring step. According to the layout method of the semiconductor integrated circuit according to the present invention, the trunk is provided in the non-obstruction straight area in the unit, and the extended trunk and the element terminals are wired. That is, according to the present invention, since the wiring to the element terminal is performed after the main line is formed first, even when the connection to the element terminal at a distant position is performed, the wiring is not connected to the wiring. It passes through the region in a shape close to a straight line, and there is less chance of obstructing other wiring that is subsequently wired. Therefore, it is possible to efficiently use the wiring area (by performing wiring as straight as possible in the wiring area) to prevent concentration of wiring and reduce the number of unwired wiring.
[0009]
In the method of laying out a semiconductor integrated circuit according to the present invention, the main line forming step includes a step of limiting a region where the main line is formed, and a center of gravity of the element terminal to be connected which exists in the limited region. The obtaining step, the step of searching for a non-hazardous straight line area in the limited area, the step of selecting the longest non-hazardous straight area in the linear area, and when there is a plurality of the longest non-hazardous linear areas, It is preferable that the method further includes a step of selecting a non-obstruction straight line area closest to the position of the center of gravity and a step of forming a trunk line in the selected non-obstruction straight area.
[0010]
In the method for laying out a semiconductor integrated circuit according to the present invention, the main line extending step includes a first step of searching for a first fault-free straight line region in a direction perpendicular to the main line from a tip of the main line, A second step of searching for a fault-free straight line area in a direction parallel to the main line from the first fault-free straight line area; and A third step of selecting as a no-obstruction straight line area, and a fourth step of extending the trunk line to the first non-obstruction straight area and the second non-obstruction area straight line, wherein the extended It is preferable that the first to fourth steps are repeatedly performed on both ends of the trunk until the trunk reaches the outside of the limited area.
[0011]
Further, in the layout method for a semiconductor integrated circuit according to the present invention, it is preferable that the wiring step is performed by using a maze method.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 4 shows a structure diagram of a chip in the analog master slice method. This chip has a unit structure, and a plurality of I / O pads 401 are provided on a peripheral (peripheral) portion of the substrate, and a portion surrounded by the plurality of I / O pads 401 (inside of the substrate) Is provided with a plurality of units 402. In the present embodiment, a case is described in which various elements are regularly arranged in the unit 402, and a wiring area for wiring between units is formed in a predetermined peripheral (peripheral) portion in the unit 402. Think.
[0013]
FIG. 5 shows an example of a structural diagram of a unit constituting the chip shown in FIG. This unit includes a plurality of resistance elements 501 and a plurality of transistor elements 502, and a wiring region 503 for wiring is formed at a right edge portion of the unit.
[0014]
Hereinafter, a layout method of a semiconductor integrated circuit according to an embodiment of the present invention will be described with reference to the drawings with respect to the above-described chip structures shown in FIGS. In the unit constituting the semiconductor integrated circuit according to the present embodiment shown in FIG. 5, the resistor 501 and the transistor 502 are not provided even in a region other than the wiring region 503 for wiring. The area is used as a wiring area. Therefore, in the present embodiment, the term “wiring region” includes not only the wiring region 503 for wiring but also a region in the unit where the resistance element 501 and the transistor element 502 are not provided.
[0015]
FIG. 1 shows a flowchart of a wiring step in a layout method of a semiconductor integrated circuit according to an embodiment of the present invention. First, in step 101, one of the nets whose wiring has not been completed is selected. Next, in step 102, a straight line region having no obstacle is searched for from the wiring region on the chip in the net selected in step 101, and a trunk line is created from the longest straight line region. Next, in step 103, the front end of the main line is extended by allowing bending from the front end of the straight main line obtained in step 102, and a longer main line is obtained. Next, in step 104, wiring between the terminals connected to the net is performed by performing wiring between the terminals and the trunk line. Next, in step 105, of the trunk lines formed up to step 104, a portion unnecessary for wiring between terminals is searched for, and this portion is deleted. Next, in step 106, it is determined whether or not wiring of all nets has been completed. Here, if the wiring of all nets has not been completed (if determined to be “No” in step 106), the process returns to step 101 again to perform the wiring process, and the wiring of all nets has been completed. If it is determined ("Yes" in step 106), the wiring process ends.
[0016]
(Main line search and creation process)
Next, the main line search step and the creation step in step 102 of FIG. 1 will be specifically described. FIG. 2 shows a flowchart of the main line search / creation process in step 102 shown in FIG.
[0017]
First, in step 201, a search range of a trunk line is set. In this step 201, the search range of the trunk line is set within the minimum rectangle surrounding the terminals connected to the same net. The reason why the search range of the main line is limited is that, if the search range of the main line is performed for the entire wiring region as in the related art, much calculation time is required. In the present embodiment, since the search range is limited as described above, it is possible to efficiently determine a trunk line in a short time. FIG. 6 is an example of a diagram showing a state in which a main line search range (main line search area) is set in step 201. In FIG. 6, a first terminal 601, a second terminal 602, a third terminal 603, a fourth terminal 604, a fifth terminal 605, and a sixth terminal 606 are connected to the same net. It is. Then, a minimum rectangular range surrounding all the terminals from the first terminal 601 to the sixth terminal 606 is formed like a main line search area 607.
[0018]
Next, in step 202, the position of the center of gravity of the terminal connected to the same net is obtained. FIG. 7 is a diagram illustrating a state where the position of the center of gravity 701 of the first terminal 601 to the sixth terminal 606 illustrated in FIG. 6 is obtained. The reason why the center of gravity position 701 is obtained in this way is to set the position of the trunk line to an optimum position. If the position of the main line is provided as close as possible to the position of the center of gravity 701, the wiring between the main line and the terminal, which is performed thereafter, can be easily performed.
[0019]
Next, in step 203, a straight wiring area without any obstacle is searched from the main line search area. Here, it is assumed that a trunk line is taken in the vertical direction as an example. Further, in the following description, an “x” mark, which is not particularly denoted by a sign, indicates that a certain obstacle exists at that position. FIG. 8 is a diagram illustrating a state in which a straight wiring region without any obstacle is searched from the main line search region. FIG. 8A shows a straight line region (a first straight line region 801, a second straight line region 802, and a third straight line region 803) at a certain coordinate X1 without any obstacle. Since the second straight line region 802 is the longest among the straight line regions having no obstacle at the coordinate X1, the second straight line region 802 is selected at the coordinate X1. This operation is performed for all the X coordinates of the main line search area, and a straight line area without any obstacle in the main line search area is searched. FIG. 8B shows a straight line region (fourth straight line region 804, fifth straight line region 805, sixth straight line region 806, seventh straight line region 807) for all X coordinates of the main line search region. , The eighth straight line area 808).
[0020]
Next, in step 204, the longest straight line area without obstacles in the main line search area is determined and set as the main line. If there are many straight regions without obstacles, the one with the longest region is selected. When the lengths of the straight regions without any obstacles are the same, the one closer to the center of gravity is selected and used as the trunk line. In FIG. 8B, the second linear region 802 is the longest and is close to the center of gravity 701. Therefore, in the present embodiment, the second straight line region 802 is selected as the main line.
[0021]
As described above, in the present embodiment, a trunk line is searched and created by performing steps 201 to 204 in accordance with the flowchart shown in FIG.
[0022]
(Main line extension process)
Next, the main line extension step in step 103 of FIG. 1 will be specifically described. FIG. 3 shows a flowchart of the main line extension process in step 103 shown in FIG. Here, the trunk is extended by permitting the tip of the trunk obtained in step 102 to be bent.
[0023]
First, in step 301, a range free from obstacles from the leading end of the trunk line is determined in a direction perpendicular to the trunk line obtained in step 102.
Next, in step 302, it is determined whether or not there is a "range without a fault" obtained in step 301. Here, when there is no “range without obstacle” (when judged “Yes” in step 302), that is, when the tip of the trunk is surrounded by the obstacle, the trunk cannot be extended any longer. Therefore, in step 302, the extension of the main line ends. If there is a “range without obstacles” (if “No” is determined in step 302), the process proceeds to the next step (step 303) to extend the trunk line.
[0024]
Next, in step 303, an area free from obstacles is determined in a direction parallel to the direction in which the trunk line extends, starting from one point in the area free from obstacles obtained in step 302. Here, a search is made for a region free from obstacles in a direction parallel to the extension direction of the trunk at all the starting points within the range free from obstacles obtained in step 302.
[0025]
Next, in step 304, it is determined whether or not there is a “range free from failure” obtained in step 303. Here, when there is no “range with no obstacle” at all the starting points within the range without obstacle determined in step 302 (when it is determined “Yes” in step 304), the trunk line is extended any longer. In step 304, extension of the main line ends. If there is a “range free from obstacles” (“No” in step 304), the process proceeds to the next step (step 305) to extend the trunk line.
[0026]
Next, in step 305, the longest area is selected from the areas without obstacles obtained in step 303, and the trunk line is extended.
Next, in step 306, it is determined whether or not the extended trunk line is within the trunk line search area. Here, if the extended trunk is in the trunk search area (if “Yes” is determined in step 306), the process returns to step 301 again, and the trunk is further extended at the tip of the extended trunk. If the extended trunk has reached the outside of the trunk search area (if "No" is determined in step 306), the extension of the trunk is terminated at that stage.
[0027]
In the present embodiment, the main line is extended by performing the above steps (steps 301 to 306) on both ends of the main line.
FIG. 9 shows an example of a case where the trunk is actually extended by the trunk extension process described using the flowchart of FIG. In FIG. 9, a main line 901 is the main line obtained in step 102.
[0028]
First, FIG. 9A shows a process of obtaining a range 902 free from obstacles in a direction perpendicular to the trunk 901 from the tip of the trunk 901 (steps 301 and 302). Next, FIG. 9B illustrates a process of searching for a range without obstacles in a direction parallel to the extension direction of the main line at all the start points (each coordinate) of the range 902 without obstacles ( Steps 303 and 304). FIG. 9B shows a first non-failure area 903, a second non-failure area 904, a third non-fault area 905, and a fourth non-fault area 906. Next, FIG. 9C shows a process of selecting the longest one from the no-obstruction areas searched for in FIG. 9B and extending the trunk line (step 305). . Therefore, here, the longest second non-failure area 904 is selected and added to the trunk (the trunk is extended).
[0029]
The main line is extended by performing the process shown in FIG. 9 on both ends of the main line. FIG. 10 shows an example of the trunk line thus formed. In FIG. 10, a trunk 1001 is an extended trunk formed in the process of FIG.
[0030]
(Wiring process between terminal and main line)
Next, a specific description will be given of the wiring step between the terminal and the trunk line in step 104 of FIG. In this step 104, the wiring between the terminals connected to the same net is performed by wiring the terminals and the trunk line. Here, wiring is performed by using a pattern wiring method or a maze method which has been conventionally used. The maze method is a method of searching for wiring routes in all directions by labeling wiring grids in an order that ripples spread from the starting point, and if there is a wiring route, it is necessary to find the shortest one It has the feature of being able to.
[0031]
Specifically, wiring is performed with each terminal as a starting point and a trunk line as a target, and wiring between the terminal and the trunk line is performed. FIG. 11 is an example of a diagram showing a wiring state between a terminal and a trunk line. In FIG. 11, wiring is performed from the third terminal 603 to the main line 1001. In other words, the third terminal 603 and the trunk 1001 are connected by the wiring 1101.
[0032]
When wiring to the main line 1001 is performed for all the terminals (the first terminal 601 to the sixth terminal 606) in this embodiment by using the pattern wiring method or the maze method, the wiring as shown in FIG. Can be
[0033]
(Unnecessary part removal process)
Next, the step of deleting unnecessary portions of the trunk in step 105 of FIG. 1 will be specifically described. In this step 105, a connection point between each terminal and the trunk line is checked, and unnecessary portions of the trunk line are deleted. Since the trunk is determined so as to be as long as possible without considering the connection with the terminal, if the connection is determined based on the wiring result of step 104, a portion not used for the connection between the terminals is formed at the end of the trunk. appear. If this part is left, it may be an obstacle to wiring to be performed later, so it must be deleted. Therefore, in this step 105, the connection point between the main line and the terminal is checked, and unnecessary portions of the main line are deleted.
[0034]
Looking at the wiring diagram between the trunk lines and the terminals shown in FIG. 12, also in the present embodiment, there are unnecessary portions (unnecessary regions 1201 and 1202) as described above. Since the unnecessary areas 1201 and 1202 are not involved in the connection between the trunk line and each terminal, even if they are deleted, they have no effect on the wiring state. In addition, if such unnecessary portions are left, there is a possibility that the wiring will be obstructed later as described above. Therefore, in the present embodiment, these unnecessary areas 1201 and 1202 are deleted. FIG. 13 shows the result of deleting the unnecessary areas 1201 and 1202 in this manner. That is, the wiring between the main line and each terminal shown in FIG. 13 is an example of a wiring diagram formed using the layout method of the semiconductor integrated circuit according to the present embodiment.
[0035]
In the present embodiment, the wiring is performed by the layout method of the semiconductor integrated circuit described with reference to FIGS. 1 to 13 described above, so that the wiring region is efficiently used (the wiring region is formed as linearly as possible). By doing so, it is possible to prevent the concentration of wiring and to reduce the number of unwired wiring. More specifically, in the present embodiment, a straight line region free from obstacles is searched for in a wiring region in a chip, and a trunk line is provided in this region. At this time, the trunk line is wired as close as possible to the position of the center of gravity of the terminal connected to the net. Then, extend the trunk until there are no obstacles, allowing the bend from the end of the trunk. Then, wiring is performed between the trunk line determined in this way and each terminal. In other words, according to the present embodiment, even if the main line is wired first, even if a long distance is connected, the wiring passes through the wiring area in a shape close to a straight line. In this case, the number of obstacles to the wiring is reduced.
[0036]
【The invention's effect】
As described above, according to the present invention, when wiring is performed on a semiconductor integrated circuit in which wiring areas are fixed as in the master slice method, bending of the wiring is reduced to generate a non-wiring area. Can be prevented, it is possible to reduce the number of unwired, on the other hand, in the case of performing wiring using the maze method, by reducing the detour of wiring by limiting the applicable range, It is possible to prevent the generation of a non-wiring area, reduce the number of unwired wirings, and at the same time, obtain a layout method for a semiconductor integrated circuit that can shorten the calculation time. That is, according to the present invention, the wiring area can be effectively used by wiring the wiring in the wiring area direction first as the main line, and the number of unwired areas can be reduced by eliminating congestion around the element. An excellent layout method of a semiconductor integrated circuit that can be performed can be obtained.
[Brief description of the drawings]
FIG. 1 is a flowchart of a wiring process in a semiconductor integrated circuit layout method according to an embodiment of the present invention; FIG. 2 is a flowchart of a main line search / creation process in step 102 shown in FIG. 1 FIG. FIG. 4 is a flowchart of a main line extension process in step 103 shown in FIG. 4; FIG. 5 is a structural diagram of a chip in an analog master slice system; FIG. 5 is a structural diagram of a unit constituting the chip shown in FIG. FIG. 7 is a view showing a state in which a main line search range (main line search area) is set in step 201 shown in FIG. 2 FIG. 7 is a diagram showing a position of the center of gravity of a terminal in the main line search area in FIG. FIG. 8 is a diagram showing the obtained state. FIG. 8 shows a state in which a straight wiring area without any obstacle is searched from the main line search area in step 203 shown in FIG. FIG. 9 is a view showing a state in which a trunk extension process is being performed based on the flowchart shown in FIG. 3. FIG. 10 is a completed view of the trunk formed by FIG. 9. FIG. FIG. 12 is a diagram showing a wiring state between a main line and a third terminal, which is drawn. FIG. 12 is a diagram showing a wiring state between the main line and each terminal shown in FIG. 10, and an unnecessary area of the main line. FIG. 14 is a view showing a wiring result formed by using a semiconductor integrated circuit layout method. FIG. 14 is a flowchart of a wiring step in a conventional semiconductor integrated circuit layout method.
401 I / O pad 402 Unit 501 Resistive element 502 Transistor element 503 Wiring area 601 for exclusive use of wiring First terminal 602 Second terminal 603 Third terminal 604 Fourth terminal 605 Fifth terminal 606 Sixth terminal 607 Main line search area 701 Center of gravity position 801 First linear area 802 Second linear area 803 Third linear area 804 Fourth linear area 805 Fifth linear area 806 Sixth linear area 807 Seventh linear area 808 Eight straight lines 901 main line (determined in step 102)
Reference numeral 902 denotes a non-obstructive area 903 in a direction perpendicular to the trunk line 901. First non-obstruction area 904 Second non-obstruction area 905 Third non-obstruction area 906 Fourth non-obstruction area 1001 Extended main line 1101 Main line 1001 Unnecessary area for wirings 1201 and 1202 connecting to three terminals 603

Claims (5)

In a layout method of a semiconductor integrated circuit for wiring a plurality of element terminals provided in each unit constituting the semiconductor integrated circuit,
A main line forming step of forming a main line in a non-obstruction-free straight region in the wiring region in the unit,
A step of searching for a first non-obstruction straight line region in a direction perpendicular to the main line from the tip of the main line, and a step of searching for a non-obstruction straight line region in a direction parallel to the main line from the first non-obstruction straight region. provided with a main line extension step of extending the main line in the region without failure during the wiring region,
A wiring step of electrically connecting the trunk line and the element terminals,
An unnecessary trunk removing step of removing an unnecessary portion of the trunk that does not contribute to the wiring step. In a layout method of a semiconductor integrated circuit for wiring a plurality of element terminals provided in each unit constituting the semiconductor integrated circuit,
A main line forming step of forming a main line in a non-obstruction-free straight region in the wiring region in the unit,
Main line extending step of extending the main line to a region where there is no obstacle in the wiring region,
A wiring step of electrically connecting the trunk line and the element terminals,
An unnecessary trunk line removing step of removing an unnecessary part of the trunk line that does not contribute to the wiring step,
The main line forming step includes a step of limiting an area in which the main line is formed; a step of determining a position of a center of gravity of the element terminal to be connected existing in the limited area; And the step of selecting the longest non-hazardous straight line area in the linear area, and if there are a plurality of the longest non-hazardous linear areas, the no-hazardous straight line closest to the position of the center of gravity among them A layout method for a semiconductor integrated circuit, comprising: a step of selecting an area; and a step of forming a trunk line in the selected fault-free linear area. The main line extending step, the first step of searching for a first non-obstruction straight line region in a direction perpendicular to the main line from the tip of the main line, and in a direction parallel to the main line from the first non-obstruction straight region A second step of searching for an unobstructed straight line area, and a third step of selecting the longest area from the unobstructed straight area in a method parallel to the trunk line as a second unobstructed straight area, A fourth step of extending the main line to a first non-obstruction straight line area and the second non-obstruction area straight line, until both ends of the main line extend until the extended main line reaches outside the limited area. 3. The layout method for a semiconductor integrated circuit according to claim 2, wherein the first to fourth steps are repeated. In a layout method of a semiconductor integrated circuit for wiring a plurality of element terminals provided in each unit constituting the semiconductor integrated circuit,
  A main line forming step of forming a main line in a non-obstruction-free straight region in the wiring region in the unit,
  A step of searching for a first non-obstruction straight line area in a direction perpendicular to the main line from the tip of the main line, and a step of searching for an obstruction-free linear area in a direction parallel to the main line from the first non-obstruction line area; A main line extending step of extending the main line to a region where there is no obstacle in the wiring region,
  A wiring step of electrically connecting the trunk line and the element terminal to each other. The wiring step, a layout method of a semiconductor integrated circuit according to any one of claims 1 to 4 is carried out using a maze router.

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