JPH0625939U - Data collection device - Google Patents

Abstract

(57) [Abstract] [Purpose] Achieves parallel operation of multiple data collection boards with a simple configuration without using a bus arbitration circuit or a digit chain, and improves processing speed. [Configuration] All addresses of the data to be collected are output from only one of the data collection boards. Each data collection board decodes the address and fetches and processes the data only when it corresponds to itself.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a data collection device, and is particularly useful as a data collection device in an MRI device.

[0002]

[Prior art]

 FIG. 4 shows the configuration of a data collection device 51 in a conventional MRI apparatus. For convenience of illustration, two data acquisition boards (DATA ACQUISITION BOARD: DAB) 54, 55, two receivers 7, 8 and two receiving coils 9, 10 are shown, but even if there are three or more, Good.

FIG. 5 is a block diagram of the data acquisition boards (DATA ACQUISITION BOARD: DAB) 54 and 55.

FIG. 6 is a timing chart of data collection.

The processor 62 of the data acquisition boards 54 and 55 requests the data bus arbitration circuit 60 to use the data bus 6 by a BR (bus request) signal.

The data bus arbitration circuit 60 outputs a signal for prohibiting the use of the data bus 6 as an RS signal when the data bus 6 is in use, and uses the data bus 6 when the data bus 6 is not in use. Is output as an RS signal. Whether or not the data bus 6 is in use is determined by whether or not any of the data collection boards 54 and 55 outputs a BBSY (bus busy) signal.

The RS signal is input to the data acquisition board 54, then output from the data acquisition board 54 and input to the data acquisition board 55. With such a connection (digit chain), the data collection board 54 can acquire the right to use the data bus 6 with priority over the data collection board 55.

When the processor 62 of the data acquisition board 54, 55 acquires the right to use the data bus 6, the address signal and the address strobe are sent to the receivers 7, 8 via the address output circuit 63, the buffer 64 and the data bus 6. (AS) signal is output.

When the address corresponds to itself, the receivers 7 and 8 send data (DTi) obtained by detecting and AD converting the NMR signals detected by the receiving coils 9 and 10 to the data bus 6. It also sends out a data acknowledge (DACK) signal.

The data collection boards 54 and 55 capture the sent data in the data latch 18 via the data bus 6 and the buffer 17. Then, the processor 62 which outputs the address signal and the address strobe signal reads the data in the data latch 18, processes the data, and stores it in the memory 19. The processed data stored in the memory 19 is taken out by the CPU 52 through the system bus 3.

The control register 61 receives control data from the CPU 52.

[0012]

[Problems to be solved by the device]

 In the data collection device 51, since the BR signal, the BBSY signal, and the address are generated and output by the data collection boards 54 and 55, respectively, the circuits and control procedures of the data collection boards 54 and 55 become complicated. is there. Also, since the right to use the data bus 6 is given by the data bus arbitration circuit 60 after waiting for the BR signal from each of the data collection boards 54 and 55, there is a problem that extra processing time is required. Further, a daisy chain is required to determine the priority between the data acquisition boards 54 and 55, and this also causes a problem that the circuit and control procedure become complicated.

That is, the conventional data collection device has a problem that the control overhead for collecting data in parallel by a plurality of data collection means is large.

Therefore, an object of the present invention is to provide a data collection device that can realize parallel data collection by a plurality of data collection means with a simple configuration.

[0015]

[Means for Solving the Problems]

 The data collection device of the present invention, when an address is given, outputs the data corresponding to the data output means on the data bus, and when the address is decoded and corresponds to itself, the data output means outputs the data output by the data output means. The structure is characterized in that it comprises a plurality of data collecting means to be taken in from the bus and an address generating means for sequentially generating an address and outputting it to the data output means and each data collecting means. is there.

[0016]

[Action]

 In the data collection device of the present invention, when the address generating means sequentially generates the addresses, the data output means sends the data corresponding to the addresses onto the data bus. Each data collecting means decodes the address, and when corresponding to itself, fetches the data on the data bus.

Each data collecting means does not generate or output the BR signal, the BBSY signal, and the address, but simply fetches the data of the corresponding address, which simplifies the circuit and control procedure. In addition, the data bus arbitration circuit and the digit chain are not required, so that the processing time is not excessive and the configuration is simple.

[0018]

【Example】

 Hereinafter, the present invention will be described in more detail with reference to the embodiments shown in the drawings. The invention is not limited to this.

FIG. 1 is a block diagram of a data acquisition apparatus 1 in an MRI apparatus according to an embodiment of the present invention. For convenience of illustration, two data acquisition boards 4, 5 and two receivers 7, 8 and two receiving coils 9, 10 are shown, but there may be three or more. A CPU 2 controls the entire data collection device 1.

FIG. 2 is a block diagram of the data collection boards 4 and 5.

The data collection boards 4 and 5 are provided with a control register 11 that receives control data from the CPU 11, a processor 12, an address generation circuit 13 that generates an address and an address strobe signal, a buffer 14, and a self register. It has an address designation register 15 for holding an address, an address decoder 16 for decoding the address to detect whether or not the address corresponds to itself, a buffer 17, and a data latch 18. .

FIG. 3 is a timing diagram of data collection.

Next, the operation will be described. First, the CPU 2 sends control data to the data collecting boards 4 and 5 and specifies the addresses corresponding to the data collecting boards 4 and 5. The processor 12 of the data collection board 4 causes the address register 15 to hold the specified address.

Next, the CPU 2 sets the data collection board 4 as a master and teaches the range of addresses to be generated. Also, the data acquisition board 5 is set as a slave.

The processor 12 of the data collection board 4 set as the master receives the first address and the address strobe (AS) signal in the address range taught by the CPU 2 from the address generation circuit 13 and the buffer 14. To output to the receivers 7 and 8.

When the address corresponds to itself, the receivers 7 and 8 send data (DTi) obtained by detecting and AD converting the NMR signal detected by the receiving coils 9 and 10 to the data bus 6. It also sends out a data acknowledge (DACK1) signal.

The data collection boards 4 and 5 detect whether or not the address of the address decoder 16 is its own address (held in the address designation register 15). The data thus obtained is taken into the data latch 18 via the data bus 6 and the buffer 17, and the processor 12 is informed that the data has been taken in. At the same time, the address generation circuit 13 of the data collecting board 4 is sent with a data acknowledge (DACK2) signal. Inform.

Only when the processor 12 is informed that the address is its own address, the processor 12 reads the data in the data latch 18, processes the data, and stores the data in the memory 19. The processed data stored in the memory 19 is taken out by the CPU 2 through the system bus 3.

When the address generation circuit 13 of the data acquisition board 4 detects the data acknowledge signals (DACK1 and DACK2), it buffers the next address and address strobe (AS) signal in the address range taught by the CPU2. It outputs to the receivers 7 and 8 via 14. Then, the above operation is repeated again, and the data in the range of the address taught by the CPU 2 is collected.

In the data collection device 1 described above, it is not necessary for each of the data collection boards 4 and 5 to acquire the right to use the data bus 6, so that the circuit and the control procedure are simplified. Further, since no extra processing time is required and the addresses are transmitted one after another by the data acknowledge signals (DACK1, DACK2), the data collection can be speeded up. Also, the data bus arbitration circuit and the digit chain are not required.

Since the address acquisition circuit 13 and the buffer 14 are not required in the data collection board which is the slave, the above configuration is omitted from the data collection board when it is known in advance that the slave is the slave. You may.

[0032]

[Effect of device]

 According to the data collection device of the present invention, since each data collection means does not need to acquire the right to use the data bus 6, a data bus arbitration circuit, a digit chain, etc. are unnecessary, and the configuration is simplified.

Further, the extra processing time is not required, and the data collection can be speeded up.

[Brief description of drawings]

FIG. 1 is a block diagram of a data collection device according to an embodiment of the present invention.

FIG. 2 is a block diagram of an example of a data collection board according to the present invention.

FIG. 3 is a timing chart of signals of main parts of FIGS. 1 and 2.

FIG. 4 is a block diagram of an example of a conventional data collection device.

FIG. 5 is a block diagram of an example of a conventional data collection board.

FIG. 6 is a timing chart of signals of main parts of FIGS. 4 and 5.

[Explanation of symbols]

 1 data collection device 2 CPU 3 system bus 4 data collection board 5 data collection board 6 data bus 7 receiver 8 receiver 9 reception coil 10 reception coil 11 control register 12 processor 13 address generation circuit 16 address decoder 19 memory

Claims (1)

[Scope of utility model registration request] 1. Data output means for outputting data corresponding to an address to a data bus when an address is given, and data output by the data output means for decoding the address and corresponding to itself from the data bus. A data collecting apparatus comprising: a plurality of data collecting means for fetching; and an address generating means for sequentially generating an address and outputting the data to the data output means and each data collecting means.