JPH05336380A - Image processing device - Google Patents

Abstract

PURPOSE:To accelerate the compression processing of image information stored on shared memory on a system bus. CONSTITUTION:Dedicated memory 31 which stores unprocessed image information of at least two lines is interposed between the system bus 2 to which the shared memory 1 is connected and a compression device 3 which performs compression processing on the image information in the shared memory 1, and also, the image information in the shared memory 1 is DMA(direct memory access)-transferred to the dedicated memory 31 in unit of at least one line. Thereby. it is possible to perform the compression processing on DMA- transderred image information in the small dead time of the system bus 2 in spite of the free state of the system bus.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image information processing apparatus for compressing image information in a facsimile machine or the like.

[0002]

2. Description of the Related Art A conventional apparatus of this type has a compressor 3 connected to a system bus 2 in a facsimile machine as shown in FIG. 3, and the compressor 3 as shown in FIG. Accessing the shared memory 1 on the system bus 2, the unprocessed raw image information (n-1, n, n + 1, n +) stored in the shared memory 1 is accessed.
, 2) are generated line by line, while compressed image information (Cn, Cn + 1, Cn + 2, ...) Is generated line by line and transferred to the compressed image information memory 4. (For example, the Institute of Electronics and Communication Engineers, "New edition: Basics and Applications of Facsimile, published on August 25, 1983" 39
See pages 3-395).

[0003]

However, according to such a configuration, there is a problem that the compression processing of the image information becomes slow.

The above-mentioned problems occur for the following reasons. That is, the compression device 3 performs compression processing of image information while accessing the shared memory 1. The compression device 3 must continue to access the shared memory 1 during this compression process. On the other hand, the shared memory 1 accessed by the compression device 3 is connected to the system bus 2. Other devices such as the CPU 11 are also connected to the system bus 2. Therefore, the access to the shared memory 1 by the compression device 3 must be performed after waiting for the timing when the system bus 2 becomes idle for a relatively long time. Alternatively, it must be performed intermittently after waiting for the timing when the system bus 2 becomes available. This lengthens the processing time (t4) for image information compression by the compression device 3.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an image information processing apparatus capable of speeding up compression processing of image information stored in a shared memory of a system.

[0006]

In order to solve the above-mentioned problems, the present invention provides at least 2 units between a system bus to which a shared memory is connected and a compression device for compressing image information in the shared memory. In addition to interposing a dedicated memory for storing unprocessed image information for one line, the image information in the shared memory is transferred to the dedicated memory by DMA (Direct Memory Access) in units of at least one line. Be prepared.

[0007]

According to the present invention, with the above-described structure, image information transferred by DMA in a short idle time of the system bus can be compressed regardless of the idle state of the system bus, so that the system can be shared. It is possible to significantly speed up the compression process of the image information stored in the memory.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts. FIG. 1 shows a schematic configuration of an image information processing apparatus according to an embodiment of the present invention.
Is a shared memory for temporarily storing uncompressed image information, 2 is a system bus to which the shared memory 1 is connected together with other devices such as the CPU 11, and 3 is a line of the image information by a two-dimensional encoding method. A compression device for performing compression processing in units, 31 is a dedicated memory interposed between the compression device 3 and the system bus 2 for storing unprocessed image information for at least two lines, and 32 is an image in the shared memory 1. DMAC (Direct Memory) that transfers information to the dedicated memory 31 in units of at least one line
An access control circuit) 4 is a compressed image memory to which the compressed image information is transferred.

The image information in the shared memory 1 is, for example, raw image information read from a document by a scanner. The compressed image information transferred to the compressed image memory 4 is transmitted by facsimile, for example, by a communication control circuit (not shown).

The operation of the image information processing apparatus configured as described above will be described below. FIG. 2 is a time chart showing an operation example of the image information processing apparatus shown in FIG. 1. First, from the common memory 1 to the dedicated memory 31,
Line image information (n-1, n, n + 1, n + 2, ...
・) Is transferred. This transfer is performed in a very short time (t1) by DMA (Direct Memory Access).

When the image information (n) for one line is newly transferred to the dedicated memory 31, the compression device 3 causes the image information (n) of one line before transferred to the dedicated memory 31 (n).
The compression process by the two-dimensional encoding is performed with reference to -1). Since the compression processing at this time can be performed based on only the image information in the dedicated memory 31 regardless of the free state of the system bus 2, it can be performed for a very short time (t
It can be done in 2).

As described above, the image information DMA-transferred in the system bus 2 with a slight free time is
The compression process is performed regardless of the free state of the system bus 2. As a result, the usage time of the system bus 2 by the compression device 3 is shortened, and the image information stored in the shared memory 1 on the system bus 2 can be displayed for a short time t3 (t3 = t1 +).
It can be processed at t2). That is, the compression processing is speeded up.

Also, for the system on the system bus 2 to which the shared memory 1 is connected, the use of the system bus 2 by the compression device 3 is reduced, so that
The processing speed can be improved.

[0015]

As is apparent from the above description, according to the present invention, at least two lines are provided between the system bus to which the shared memory is connected and the compression device for compressing the image information in the shared memory. In addition to interposing a dedicated memory for storing the unprocessed image information, the image information in the shared memory is DMA-transferred to the dedicated memory in units of at least one line, so that the DMA can be performed in a small free time of the system bus. Since the transferred image information can be compressed regardless of the availability of the system bus, the compression of the image information stored in the shared memory of the system can be significantly speeded up. I have.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an image information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a timing diagram showing an outline of the operation of the apparatus shown in FIG.

FIG. 3 is a schematic configuration diagram of a conventional image information processing device.

FIG. 4 is a timing diagram showing an outline of operation of the apparatus shown in FIG.

[Explanation of symbols]

1 shared memory 2 system bus 3 compression device 31 dedicated memory 32 DMAC (direct memory access control circuit) 4 compressed image memory n-1, n, n + 1, n + 2, ... Uncompressed image information Cn, Cn + 1, Cn + 2, ... Compressed image information

Claims (1)

[Claims] 1. An image information processing apparatus for compressing image information in a shared memory connected to a system bus, comprising: a compressing device for compressing image information line by line; and the compressing device and the bus. A dedicated memory for storing at least two lines of unprocessed image information interposed therebetween, and a direct memory access control circuit for transferring image information in the shared memory to the dedicated memory in units of at least one line An image information processing device equipped with.