JPH05216812A - Data processor - Google Patents

Abstract

PURPOSE:To reduce the load on a system bus as to the data processor. CONSTITUTION:This data processor is equipped with a 1st buffer memory 1 wherein specific parallel-bit data sent from a system bus 13 are separated into (n) data having parallel bits 1/n (n:2, 3...) time as many as a specific number of parallel bits and stored, a processing circuit 3 which read the (n) data out of the 1st buffer memory and performs specific processing, and a 2nd buffer memory 2 which is stored with the (n) data processed by the processing circuit 3 in order and then integrates them into data having a specific number of parallel bits, and sends the data out to the system bus 13 or another system bus 14.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to improvements in data processing equipment.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram of a computer terminal. A storage device such as a control memory 5, a floppy disk 6, and a magnetic disk 7 is connected to the system bus 13 in addition to the CPU 4 and the line unit 8. Each device transmits / receives data via the system bus 13 to process data. Done. Further, in order to print the data processed by the above apparatus, the data is sent to the image processing circuit 3 via the system bus 13. Data that has undergone image processing such as enlargement / reduction in the image processing circuit 3 is stored in the system bus 14
To the BMM10 via. Then, the BMM10 expands the bitmap and converts it into print data, which is then sent to the printer 9 and printed out. System bus
The control memory 11 and the magnetic disk 12 store control data necessary for performing data processing such as bit map expansion. The FIFO registers (first-in first-out registers) 15 and 16 are buffer memories provided for adjusting the data transfer speed in the system buses 13 and 14 and the data processing speed in the image processing circuit 3.

In order to improve the data processing speed, it is effective to use data having a large number of bits that can be processed in parallel, and the system buses 13, 14 and the system bus 13,
Most of the devices connected to the 14 can process 32-bit parallel data. However, as the image processing circuit 3 for performing image processing, for example, only an image processing circuit capable of processing 16-bit parallel data is available at present.

In this case, conventionally, 32-bit parallel data is divided into two pieces of data of upper 16 bits and lower 16 bits, and each piece of data is sequentially sent to the image processing circuit 3 via the system bus 13. Then, the image processing circuit 3 processes 16-bit parallel data and sequentially processes the system bus.
I was sending it to 14.

[0005]

As described above, it is effective to use a processing circuit having a large number of parallel bits in order to improve the data processing speed. However, due to cost and manufacturing technology problems, parallel processing is not possible. When it is difficult to obtain a processing circuit having a large number of bits, a processing circuit having a small number of parallel bits and a processing circuit having a large number of parallel bits are mixedly connected to the same system bus. When data is sent from the system bus to a processing circuit having a small number of parallel bits for processing, data having a large number of parallel bits is separated into data having a number of parallel bits that can be processed by the processing circuit, and each data is separated. Were sequentially sent to the processing circuit via the system bus. Therefore, as compared with the case where data having a large number of parallel bits is sent at one time, the data occupies the system bus for a longer time. This means that the load on the system bus becomes heavy, and during that time, it becomes impossible to transfer data via the system bus between other devices connected to the system bus, which causes a problem that the data processing efficiency decreases. ..

Therefore, an object of the present invention is to reduce the load on the system bus.

[0007]

To solve the above-mentioned problems, data having a predetermined number of parallel bits sent from the system bus 13 is converted into 1 / n (n = n) of the predetermined number of parallel bits.
(2, 3, ...) A first buffer memory 1 for separately storing n pieces of data having the number of parallel bits, and the n pieces of data are sequentially read from the first buffer memory to perform a predetermined process. And a processing circuit 3 for performing the above processing, sequentially storing n pieces of data processed by the processing circuit 3 and then connecting the data to the data having the predetermined number of parallel bits and transmitting the data to the system bus 13 or another system bus 14. This is achieved by a data processing device including a second buffer memory 2.

[0008]

In the present invention, the data having the predetermined number of parallel bits sent from the system bus 13 is separated into n pieces of data having the number of parallel bits that can be processed by the processing circuit 3, and the first buffer memory is separated. Store in 1. Then, after sequentially processing n pieces of data by the processing circuit 3, the data is sequentially stored in the second buffer memory 2 and then again connected to the original parallel bit number of data, and the system bus 13 or another system bus 14 is connected.
To send to. Therefore, the system buses 13 and 14 can send data having a predetermined number of parallel bits at one time regardless of the number of parallel bits that can be processed by the processing circuit 3, so that the system buses necessary for sending data to the processing circuit 3 can be obtained. 13,
The occupying time of 14 can be reduced as compared with the conventional one.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention, and those having the same functions as those in FIG. In the figure, 1 is the first buffer memory, 2 is
Is the second buffer memory, 1a, 1b, 2a and 2b are the above-mentioned F
It is an IFO register. In this embodiment, the image processing circuit 3 and the FIFO registers 1a, 1b, 2a and 2b are set to 1
It is assumed that 6-bit parallel data processing can be performed, and that other devices can perform 32-bit parallel data processing including the system buses 13 and 14.

A case of printing 32-bit parallel data stored in the magnetic disk 7 will be described below with reference to FIG. First, 32-bit parallel data of the magnetic disk 7 is transferred via the system bus 13 to the first buffer memory 1
Sent to. In the first buffer memory 1, the upper 16 bits of data are stored in the FIFO register 1a and the lower 16 bits are stored.
The bit data is stored in the FIFO register 1b. Then, the contents of the FIFO register 1a are sent to the image processing circuit 3 and image processing such as enlargement processing is performed and then the FIFO
It is stored in the register 2a. Subsequently, the contents of the FIFO register 1b are sent to the image processing circuit 3 and are subjected to the same processing, and then stored in the FIFO register 2b. Then, FIF
The contents of the O registers 2a and 2b are combined and sent to the system bus 14 as 32-bit data. The 32-bit data is sent to the BMM 10, expanded into a bitmap, converted into print data, and then sent to the printer 9 to be printed out.

As described above, the system buses 13 and 14 have three
2-bit parallel data is transmitted. Therefore, the occupied time of the data on the system buses 13 and 14 is about half that in the case where 16-bit parallel data is sequentially transmitted, and the system buses 13 and 14 can be used for transmitting other data during that time, so that it is possible to compare with the conventional method. Data processing efficiency is improved.

The present invention is not limited to the above embodiment, but can be similarly applied to a system having an arbitrary processing circuit having a number of parallel bits smaller than the number of parallel bits that can be transmitted by the system bus. ..

[0013]

As described above, according to the present invention, the load on the system bus is reduced, which is useful for improving the data processing efficiency.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing the problems of the conventional example.

[Explanation of symbols]

1 first buffer memory, 7, 12 magnetic disk, 1a, 1b, 2a, 2b, 15, 16 FIFO register, 2 second buffer memory, 8 line unit, 3 image processing circuit, 9 printer, 4 CPU, 10 B
MM (bitmap memory) 5, 11 control memory, 13, 14 system bus, 6 floppy disk,

Claims (1)

[Claims] 1. The data having a predetermined number of parallel bits sent from a system bus (13) is converted into a parallel bit number of 1 / n (n = 2, 3, ...) Of the predetermined number of parallel bits. A first buffer memory (1) that stores the n pieces of data separately, and a processing circuit (3) that sequentially reads the n pieces of data from the first buffer memory (1) and performs a predetermined process. And sequentially storing n pieces of data processed by the processing circuit (3), and then combining the data with the predetermined number of parallel bits and sending the data to the system bus (13) or another system bus (14). A data processing device comprising a second buffer memory (2) for