JPH06252177A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To realize a FET of a normally off type, by improving its pinch-off characteristic, and to improve its noise characteristic, by improving its source resistance, in the FET made of a compound semiconductor having a high conductivity even in the case of its growth under an undoped condition. CONSTITUTION:In a FET, on at least one surface of a channel layer 1 of a first conductivity type, a barrier layer 2 having a smaller electron affinity than the channel layer 1 wherein an impurity of a second conductivity type is doped is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (FET), and more particularly to a compound semiconductor FET having InAs as a channel layer.

[0002]

2. Description of the Related Art Compound semiconductors such as GaAs FETs
Is in the direction of being used in fields requiring ultra-high frequency and ultra-high speed, such as satellite broadcasting reception.

InAs is known as a compound semiconductor which is superior in material characteristics to GaAs. In other words, this InAs has a smaller effective electron mass than GaAs,
High electron saturation speed.

Further, this InAs has an advantage that ohmic contact can be made to the electrode without alloying.

From this, it is considered that the FET using InAs as a channel layer can obtain high speed and high frequency characteristics superior to those of GaAs FET.

However, this InAs exhibits n-type conductivity which generally reaches 10 ¹⁶ atoms / cm ³ or more even when it is grown under the undoped condition, and thus the pinch-off characteristic is poor even when an FET is manufactured. There is a problem. For example, InAs using the Al _x Ga ₁ -x Sb layer as a hetero barrier.
Even if a channel FET is manufactured, it is difficult to sufficiently turn off the current by the gate voltage, and therefore a normally-off type FET cannot be realized.

Further, even if the electron concentration of InAs can be made sufficiently low, in this case, the source resistance cannot be made sufficiently small, which causes a problem that noise characteristics are deteriorated.

[0008]

SUMMARY OF THE INVENTION The present invention aims to improve the pinch-off characteristic even in the case of constructing an FET made of a compound semiconductor that exhibits high conductivity even when grown under the undoped condition as described above, and normally-off is achieved. Type FET, and further improve the source resistance and thus the noise characteristic.

[0009]

The first aspect of the present invention, as shown in FIG. 1 which is a sectional view of the basic structure of one example thereof, shows at least one surface of a channel layer 1 of the first conductivity type, for example, n type. An electron affinity smaller than that of the channel layer 1 is provided, and a barrier layer 2 doped with an impurity of the second conductivity type, for example, p type is provided.
Configure T.

According to the second aspect of the present invention, a barrier layer 2 having an electron affinity smaller than that of the channel layer is provided on both sides of the channel layer of the first conductivity type, for example, n type, and the barrier layer 2 is provided in at least one of the barrier layers 2. The second conductivity type, for example, p-type impurities are doped.

In the present invention, the channel layer 1 is an InAs FET in each of the above-mentioned configurations.

[0012]

As described above, according to the present invention, for example, In
The barrier layer of the channel layer 1 is provided by contacting the As channel layer 1 and providing at least one of the barrier layers 2 having a conductivity type smaller than that of the channel layer 1 and a conductivity type different from that of the channel layer 1. Since a depletion layer is formed at the heterojunction with the layer 2, the drain current can be sufficiently modulated by the gate voltage of the FET, and the drain current can be made sufficiently small under the bias condition of pinch-off, thereby forming a normally-off InAs-based FET. to enable.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1 which is a sectional view of the basic structure of the present invention, a first conductivity type, for example n.
Type channel layer 1 and at least one surface thereof, for example, both surfaces thereof, is provided with a barrier layer 2 having an electron affinity smaller than that of the channel layer 1 and at least one having a second conductivity type, for example, a p-type impurity. Configure FET.

The specific construction of the present invention will be described together with its manufacturing method with reference to FIG. First, as shown in FIG. 2, a buffer layer 1 is sequentially formed on a GaSb single crystal substrate 11, for example.
2, the first barrier layer 2A, the n-type channel layer 1, the spacer layer 13, the second barrier layer 2B, and the cap layer 14 are successively MOCVD (Metal Organic Chemical Vapor Depositio).
n) or MEB (Molecular Beam Epitaxy).

The buffer layer 12 has a thickness of, for example, 50 nm to 5 nm.
Undoped GaAs of 00 nm, first barrier layer 2A
Is, for example, a p-type or an
Al having an electron affinity lower than that of the doped channel layer 1_xG
a_1-xSb, and the channel layer 1 has a thickness of 5 nm to 100 n
The spacer layer 13 has a thickness of 2
nm-30 nm undoped Al_xGa_1-xSb,
The second barrier layer 2B is a p-type thin film having a thickness of 5 nm to 200 nm.
Al with smaller electron repulsion than the channel layer 1_xGa _1-xSb
And the cap layer 14 is made of In having a thickness of 10 nm to 50 nm.
Can be As.

This undoped InAs channel layer 1
Shows n-type even though it is undoped.

As shown in FIG. 3, a groove for assisting the separation in separating the electrical insulation between FETs or the elements finally formed to a depth from the cap layer 14 to the buffer layer 12, for example. 14 is formed by chemical etching such as photolithography or dry etching.

As shown in FIG. 4, the gate layer on the cap layer 14 has a thickness of, for example, 50 nm to 500 nm of A.
The gate electrode 15 made of u is formed.

As shown in FIG. 5, the gate electrode 15 is used as a mask to etch away the cap layer 14, the second barrier layer 2B, and the spacer layer 13 which are not covered by the gate electrode 15 to form an undoped channel. The layer 1 is exposed to the outside on both sides of the gate portion.

As shown in FIG. 6, an insulating film 16 made of Si ₃ N ₄ or the like is formed on the surface by a CVD (chemical vapor deposition) method or the like.
Are formed.

As shown in FIG. 7, the insulating film 16 is selectively etched by photolithography or the like on the gate electrode 15 and the source and drain electrode formation portions on the channel layer 1 on both sides thereof to form an electrode window. And a metal such as Au is deposited therethrough to bring the source and drain electrodes 17s and 17d into ohmic contact with the channel layer 1 in this case. A similar electrode may be simultaneously formed on the gate electrode 15 to increase its thickness. This ohmic contact can omit the alloy.

In this way, the desired FET is constructed.

With this structure, the channel layer 1 in the thickness direction of the FET and the barrier layer 2 (2A and 2B) sandwiching the channel layer 1 in the thickness direction in the portion where the second barrier layer 2B exists, that is, the cross section at the gate portion and the first 8 and 9 show energy band models at a gate voltage of zero in the cross section of the portion where the second barrier layer 2A is removed. In this case, the case where the first barrier layer 2A is undoped is shown.

As is clear from FIG. 8, the channel layer 1 is depleted in the state where the gate voltage is zero in the portion where the p-type second barrier layer 2B having a small electron affinity exists, that is, in the gate portion directly below the gate electrode. FE with normally-off
It can be seen that T can be constructed. Since the barrier layer 2B does not exist in regions other than the gate portion, that is, in the source and drain regions, carriers are accumulated and low source resistance is realized.

Here, the barrier layer 2 is provided on either one of the channel layers 1 under the gate portion, and one of the barrier layers is doped with an impurity of a conductivity type different from the conductivity type exhibited by the channel layer 1. With the configuration, depletion of the channel layer 1 can be realized. However, as in the above-described example, the first and second barrier layers 2A and 2B are provided with the channel layer 1 sandwiched therebetween, and the barrier layer 2B on the gate side thereof is provided. It is preferable that the channel layer 1 is doped with impurities having a conductivity type different from that of the channel layer 1.

Further, the doping of impurities in the barrier layer 2, for example, the barrier layer 2B in the above-described structure, can be distributed uniformly over the entire thickness thereof, but the doping is biased in a part in the thickness direction. You can also

For example, as shown in FIG. 10, the spacer layer 1
Dope layer 2B having a so-called δ distribution segregated at the interface with
It is also possible to construct s. In FIG. 10, parts corresponding to those in FIG. 2 are designated by the same reference numerals, and redundant description will be omitted.

It is needless to say that the structure of the FET and the composition of each layer are not limited to the above-mentioned examples and various structures can be adopted.

[0029]

As described above, according to the present invention, for example, at least one of the InAs channel layers 1 is in contact with the InAs channel layer 1 and has an electron affinity smaller than that of the channel layer 1 and a conductivity type different from that of the channel layer 1. With the configuration in which the barrier layer 2 is provided, a depletion layer is generated in the heterojunction with the barrier layer 2 of the channel layer 1, so that the drain current can be sufficiently modulated by the gate voltage, and the drain current can be changed under the bias condition of pinch-off. For example, an InAs-based FET that can be made sufficiently small and exhibits n-type conductivity even under undoped conditions
Also in the above, it is possible to configure a normally-off type n-channel FET.

As described above, the high saturation rate of electrons and the low ohmic contact resistance without alloying can be obtained. For example, the realization of an ultra high frequency and ultra high speed transistor making full use of the characteristics of the InAs material, especially compared with the conventional FET. A normally-off type FET with a significantly reduced source resistance can be realized.

[Brief description of drawings]

1 is a schematic cross-sectional view of the basic structure of a field effect transistor according to the present invention.

FIG. 2 is a manufacturing process drawing of an example of a field effect transistor according to the present invention.

FIG. 3 is a manufacturing process diagram of an example of a field effect transistor according to the present invention.

FIG. 4 is a manufacturing process diagram of an example of a field effect transistor according to the present invention.

FIG. 5 is a manufacturing process diagram of an example of a field effect transistor according to the present invention.

FIG. 6 is a manufacturing process diagram of an example of a field effect transistor according to the present invention.

FIG. 7 is a schematic cross-sectional view of an example of a field effect transistor according to the present invention.

FIG. 8 is an energy band model diagram for explaining the present invention.

FIG. 9 is an energy band model diagram for explaining the present invention.

FIG. 10 is a manufacturing process diagram of another example of the field-effect transistor according to the present invention.

[Description of Reference Signs] 1 channel layer 2 barrier layer 2A first barrier layer 2B second barrier layer 11 substrate 16 gate electrode 17s source electrode 17d drain electrode

Claims (3)

[Claims] 1. A field effect characterized in that a barrier layer doped with impurities of a second conductivity type is provided on at least one surface of the first conductivity type channel layer, the barrier layer having an electron affinity lower than that of the channel layer. Transistor. 2. A barrier layer having an electron affinity lower than that of the channel layer is provided on both sides of the channel layer of the first conductivity type, and at least one of the barrier layers is doped with an impurity of the second conductivity type. A field effect transistor characterized in that 3. The field effect transistor according to claim 1, wherein the channel layer is InAs.