JPH06243599A - Format conversion device and digital vtr - Google Patents

Abstract

PURPOSE:To save the memory capacity. CONSTITUTION:The input data of a transmission format are supplied and written in the input port IN1 of a RAM 41A, and are supplied to an error detector 42A. By the error detector 42A, the error correction data of a certain data frame are outputted for a next frame interval. The error correction data and the data read out to the output port OUT1 of the RAM 41A by adjusting to the output of the error correction data are supplied to an OR circuit 43A, and the error correction data from the OR circuit 43A are supplied and written in the input port IN2 of the RAM 41A. The error correction data of respective buffering units are read out to the output port 0UT2 of the RAM 41A with 18. 1MHz clock to obtain the data of a signal processing format. The memory capacity is saved since the memory for format conversion is shared with the memory for error correction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention converts the format of input data from a transmission format to an internal format, and uses the error correction parity added to the input signal to correct the error in the input data. The present invention relates to a format conversion device and a digital VTR having the format conversion device as an input section.

[0002]

2. Description of the Related Art In a VTR for broadcasting, the D1 system and D2 system have
Digital VTRs based on various digital standards such as the D3 system and the D3 system have been commercialized. On the other hand, in the consumer VTR, various formats have been proposed for practical use of the digital VTR.

For example, the discrete cosine transform (DCT: Discrete)
Cosine Transform) and variable length coding (VLC: Variable Le
A digital VTR which employs high efficiency coding by ngth coding is provided with a recording system and a reproducing system having a configuration as shown in FIG.

In the recording system, the input analog component video signals (Y, RY, BY) are converted into digital component video signals by the A / D converter 1, and the blocking circuit 2 uses a frame memory. 8x8 units (8 samples x 8 lines) are made into blocks, and shuffled and Y
/ C is multiplexed. The data of each block is subjected to discrete cosine transform in the DCT circuit 3, and the data in the time amplitude domain is transformed into the data in the frequency domain. Further, the discrete cosine transformed data is requantized by the encoder 4, variable length coded by a two-dimensional Huffman code or the like, and data compressed.

The variable length coding by the encoder 4 is controlled so that a fixed length is set for each buffering unit composed of a predetermined number of DCT blocks, for example, 30 DCT blocks. Then, the variable-length coded data is processed by the framing circuit 5 with an error correction code (ECC: Erro
r Correction Code), the parity is added by the parity generation circuit 6, the channel coding is performed by the channel encoder 7 in a form suitable for magnetic recording and reproduction, and a magnetic tape (not shown) as serial recording data. Recorded in.

In the reproducing system, the reproduction data reproduced from the magnetic tape is subjected to data detection and serial / parallel conversion by the channel decoder, and time axis correction processing is performed by the time axis correction (TBC) circuit 9. Error correction processing is performed by the error correction circuit 10. Further, the deframing circuit 11 decomposes the variable-length code into word units, the decoder 12 decodes and dequantizes the data, and the inverse DCT circuit 13 performs an inverse discrete cosine transform to obtain 8 × 8 unit data. The deblocking circuit 14 performs deshuffling, Y / C separation, data interpolation, and other processing on the data, restores it to a digital component video signal, and a D / A converter 15 converts the data to an analog signal. It is output as a video signal.

Although not described in the example of FIG. 5, in actuality, recording / reproducing of audio data and sub-code data together with video data is also carried out at the same time.
FIG. 6 shows a recording format of one helical track of the magnetic tape.

At both ends, a preliminary marginal area 3 is provided until the magnetic tape and the magnetic head come into a stable contact state.
1a and 31b are allocated, and the helical track T
A video area 32 in which the actual video data is recorded is allocated in the center of the, and a first AFT area 33a and an audio area 34 in which the audio data is recorded are allocated between one marginal area 31a and the video area 32, respectively. And the other marginal area 31b
A subcode area 35 in which subcode data (time, address, etc.) is recorded and a second AFT area 33b are allocated between the video area 32 and the video area 32.

In addition, between the respective areas, for example, in the head portions of the first and second AFT areas 33a and 33b, both side portions of the audio area 33, both side portions of the video area 32 and both side portions of the sub code area 35, An amble area 36 is assigned to each.

An area 37 indicated by diagonal lines is a block gap area. Further, tracking correction AFT signals are recorded in the first and second AFT areas 33a and 33b, respectively.

FIG. 7 shows a dubbing system in which the above digital VTR is configured as a recorder and a player. That is, the output data of the deframing circuit 11 is supplied to the framing circuit 5 on the recording machine side through the digital interfaces 16 and 17. However, regarding the audio data and the sub-code data, the output data of the error correction circuit 10 is supplied to the parity generation circuit 6 on the recorder side via the digital interfaces 16 and 17, as described later.

FIG. 8 shows a digital interface 16,
17 shows a configuration of 17. In FIG. 8, parts corresponding to those in FIG. 7 are designated by the same reference numerals.

The reproduction data subjected to the time-axis correction processing by the time-axis correction circuit 9 on the reproducing device side is error-corrected by the error correction circuit 10. The error correction circuit 10 corrects an error generated in the recording / reproducing system and outputs an error flag for an uncorrectable error.

The video data error-corrected by the error correction circuit 10 is supplied to the error processing circuit 104 via the deframing circuit 11 and is also supplied to a decoder (not shown) for reproduction video signal processing and monitor video signal. Is output as. Also, the error correction circuit 1
The audio data error-corrected by 0 is supplied to the error processing circuit 105 and also supplied to a decoder (not shown) to be subjected to reproduction audio signal processing and output as a monitor audio signal. Further, the sub-code data error-corrected by the error correction circuit 10 is supplied to the error processing circuit 106 and also to a decoder (not shown) for reproduction processing.

In the error processing circuit 104, based on an error flag indicating an afterimage error, when an error that cannot be corrected by the error correction circuit 10 remains in the deframed video data supplied from the deframing circuit 11. The error processing is performed to replace the data, which cannot decode the variable length code due to the remaining error, with a predetermined error code. Error processing circuit 10
The video data subjected to error processing by 4 is framed by the framing circuit 107 so as to have a product code structure for error correction, and supplied to the multiplexer 109.

The error processing circuit 105 performs error processing for replacing the error data of the audio data corrected by the error correction circuit 10 with a predetermined error code in word units based on an error flag indicating a residual error. The audio data subjected to the error processing by the error processing circuit 105 is the multiplexer 109.
Is supplied to.

The error processing circuit 106 performs error processing for replacing the error data with a predetermined error code on the subcode data error-corrected by the error correction circuit 10 based on an error flag indicating a residual error. The subcode data subjected to the error processing by the error processing circuit 106 is supplied to the multiplexer 109.

The multiplexer 109 time-division multiplexes the error-processed video data, audio data, and subcode data together with the control data from the microcomputer 108, and converts them into a transmission format via the RAM 110.

The data converted into the transmission format is
The synchronization addition circuit 111 adds the transmission synchronization signal SYNC, the parity generation circuit 112 adds the transmission parity, the randomization (RNDM) circuit 113, the parallel / serial converter 114, and the optical or electrical conversion from the driver 115. Is output as serial data.

FIG. 9 shows the format of dubbing data. One frame is composed of data Track0 to Track9 for 10 tracks, and data for one track is data MB0 to MB1 for 14 multiblocks.
3 (28 buffering units). The data in the buffering unit in the first half of one multi-block is composed of control data SB0 for one sync block and video data SB1 to SB5 for five sync blocks, and the data in the buffering unit in the second half is for one sync block. Audio data (or subcode data) SB0 and video data S for 5 sync blocks
It is composed of B1 to SB5.

In the signal processing format, the data of one sync block is composed of 80 bytes. In the data frame of the transmission format, however, the sync signal SYNC (2 bytes) and parity (8 bytes) are added before and after the data of each sync block. Is added to form 90 bytes.

The regenerator side operates at a clock of 18.1 MHz, performs processing of one buffering unit in a period of 2160 clocks, and serial data converted into a transmission format is output at a clock of 36.2 MHz.

Returning to FIG. 8, on the recorder side, the receiver 116 receives the serial data transmitted from the player side by starting the driver 115, and the PLL circuit 117 receives the serial data from the serial data. The clock is generated and the serial data is converted into parallel data by the serial / parallel converter 118.

Then, the synchronization detection circuit 119 detects the synchronization signal SYNC for transmission from the parallel data obtained by the serial / parallel converter 118, and outputs the timing necessary for the subsequent processing. Further, the parallel data obtained by the serial / parallel converter 118 is supplied to the error correction circuit 121 for transmission via the derandomization (DRNDM) circuit 120.

The error correction circuit 121 corrects an error that has occurred on the transmission line, and outputs an error flag in the same manner as the error correction circuit 10 on the reproducing apparatus side when the error cannot be corrected.

The vertical sync detection circuit 122 also detects a vertical sync signal from the data error-corrected by the error correction circuit 121. Then, the recorder side operates by using this vertical synchronizing signal as a reference to establish frame synchronization with the reproducer side.

Further, the data error-corrected by the error correction circuit 121 is returned from the transmission format to the signal processing format by the RAM 123 and supplied to the demultiplexer 124. The control data output from the demultiplexer 124 is supplied to the system control microcomputer 125.

The video data output from the demultiplexer 124 is supplied to the error processing circuit 127 via the deframing circuit 126, and the audio data and the subcode data output from the demultiplexer 124 are respectively processed in the error processing circuit 128. And 12
9 is supplied. These error processing circuits 127 to 12
In 9, the error data is replaced with the error code by the same error processing as that on the reproducing device side according to the error flag from the error correction circuit 121.

The video data output from the error processing circuit 127 is supplied to the parity generation circuit 6 via the framing circuit 5. The audio data and subcode data output from the error processing circuits 128 and 129 are supplied to the parity generation circuit 6, respectively. The parity generating circuit 6 adds new parity for recording to form recording data.

FIG. 10 shows an error correction circuit 12 on the recorder side.
1 (error flag output section is not shown) and the specific configuration of the format conversion circuit 123 is shown.

In the figure, input data is supplied to an error detector 21 which constitutes an error correction circuit 121. The error detector 21 performs an error detection operation in units of data frames. Then, the error correction data of a certain data frame is sequentially output from the error detector 21 in the next data frame period and supplied to an exclusive OR circuit (hereinafter, referred to as "EX-OR circuit") 23 that constitutes the error correction device. To be done. And this EX-OR circuit 2
3, the RAM 22 having a capacity of one sync block supplies the input data with a delay of about one data frame period, and the input data is error-corrected.

The data output from the EX-OR circuit 23 is supplied as write data to the RAMs 24A and 24B that form the format conversion circuit 123 and have a capacity of 6 sync blocks. RAM 24A, 24B
Are write enable signals WENa and WENb and write address signal WA at the timings shown in FIG.
Da and WADb are supplied, and data SB0 to SB5 for 6 sync blocks of each block unit are transferred to the RAM 24A,
Alternately written to 24B.

Further, the RAMs 24A and 24B have a structure shown in FIG.
The read enable signal RENa, at the timing shown in
RENb and write address signals RADa, RAD
b is supplied, and 1 is alternately supplied from the RAMs 24A and 24B.
Data SB0 to SB5 for 6 sync blocks of each block unit are read at a clock of 8.1 MHz, and output data in a signal processing format is obtained (see FIG. 9).

Note that SB0 to SB5 in FIG. 11 represent address signals corresponding to the data SB0 to SB5.

[0035]

By the way, according to the configuration of the error correction circuit 121 and the format conversion circuit 123 as shown in FIG. 10, in addition to the format conversion RAMs 24A and 24B, the error correction RAM is provided.
22 is required, and there is a problem that the required memory capacity becomes large.

Therefore, an object of the present invention is to provide a format conversion device which can save memory capacity.

[0037]

According to the present invention, the format of input data is converted from a transmission format to an internal format, and the error correction parity added to the input data is used to correct the error in the input data. In the format conversion device, the memory used when performing the format conversion process is also used as the memory used when performing the error correction process.

[0038]

In the present invention, the memory for format conversion processing is also used as the memory for error correction processing, so that the memory capacity can be saved.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. This example is applied to the error correction circuit 121 and the format conversion circuit 123 of the digital interface 17 of FIG.

In the figure, 41A and 41B are RAMs each having a capacity of 6 sync blocks. The RAMs 41 and 42 include first and second input ports IN1 and IN2, respectively, and first and second output ports OUT1 and OUT2, which are independent of the first and second ports. It is configured to be accessible by.

Further, 42A and 42B are error detectors, respectively, which perform an error detecting operation in units of data frames. In this case, the error detectors 42A and 42B sequentially output the error correction data for the data of a certain data frame in the next data frame period. Four
Reference numerals 3A and 43B are EX-OR circuits forming an error corrector.

The input data is supplied to the input ports IN1 of the RAMs 41A and 41B as write data and also to the error detectors 42A and 42B. RAM
The data obtained at the output ports OUT1 of 41A and 41B are supplied to one input terminals of the EX-OR circuits 43A and 43B, respectively. The EX-OR circuits 43A and 43
The other input terminal of B is connected to the error detector 42, respectively.
The error correction data output from A and 42B is supplied. The output data of the EX-OR circuits 43A and 43B are supplied to the input ports IN2 of the RAMs 41A and 41B, respectively. Then, the output port O of the RAM 41A, 41B
The data obtained at UT2 is the output data.

In the above configuration, the RAMs 41A, 41
B has write enable signals WENA1 and WEN related to the input port IN1 at the timings shown in FIGS.
B1 and write address signals WADA1, WADB1
The data SB0 to SB5 for 6 sync blocks of each buffering unit are alternately written to the RAMs 41A and 41B.

Further, the read enable signals RENA1 and RENB1 and the read address signals RADA1 and RADB1 related to the output port OUT1 are supplied to the RAMs 41A and 41B at the timings shown in FIGS.
The data SB0 to SB5 supplied to the input port IN1 and written to the output port OUT1 of the RAMs 41A and 41B are delayed by approximately one data frame period, and the error correction data is output from the error detectors 42A and 42B. It is output according to the timing. As a result, the output data of the EX-OR circuits 43A and 43B are error-corrected.

Further, the RAMs 41A and 41B are supplied with write enable signals WENA2 and WENB2 and write address signals WADA2 and WADB2 related to the input port IN2 at the timings shown in FIGS.
The output data of the X-OR circuits 43A and 43B are written.

Then, the RAMs 41A and 41B have the configuration shown in FIG.
Also, the read enable signals RENA2 and RENB2 and the read address signals RADA2 and RADB2 related to the output port OUT2 are supplied at the timings shown in FIG. Data SB0 to SB5 for 6 sync blocks are read out, and output data in the signal processing format is obtained (see FIG. 9).

SB0 to SB5 in FIGS. 2 and 3 are
Address signals corresponding to the data SB0 to SB5 are shown.

Although the above embodiment is applied to the error correction circuit 121 and the format conversion circuit 123 of the digital interface 17 of the digital VTR, the present invention converts the format of the input data from the transmission format to the internal format. In addition, the present invention can be similarly applied to other format conversion devices that correct errors in input data by using error correction parity added to the input data.

In the above embodiment, two error detectors 42A and 42B are used.
It is also possible to use one error detector 42 as shown in FIG. In this case, the error correction data from the error detector 42 is alternately supplied to the EX-OR circuits 43A and 43B based on the read enable signal RENA1.

[0050]

According to the present invention, since the memory for the format conversion process is also used as the memory for the error correction process, the memory dedicated to the error correction is not required, and the memory capacity can be saved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a format conversion device according to the present invention.

FIG. 2 is a timing chart showing an operation timing (RAM 41A) of the embodiment.

FIG. 3 is a timing chart showing the operation timing (RAM 41A) of the embodiment.

FIG. 4 is a block diagram showing another embodiment of the format conversion device according to the present invention.

FIG. 5 is a block diagram showing a circuit configuration of a digital VTR.

FIG. 6 is a diagram showing a track format of a digital VTR.

FIG. 7 is a block diagram showing a dubbing system using a digital VTR.

FIG. 8 is a block diagram showing a digital interface in a dubbing system.

FIG. 9 is a diagram showing a format of dubbing data.

FIG. 10 is a block diagram showing an error correction circuit and a format conversion circuit.

FIG. 11 is a diagram showing operation timing of the format conversion circuit.

[Explanation of symbols]

 16, 17 Digital interface 41A, 41B RAM 42, 42A, 42B Error detector 43A, 43B Exclusive OR circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hirotaka Ishimaru 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (2)

[Claims] 1. A format conversion device for converting the format of input data from a transmission format to an internal format and correcting the error of the input data by using an error correction parity added to the input data, A format conversion device, wherein a memory used when performing the format conversion process is also used as a memory used when performing the error correction process. 2. A digital VTR having the format conversion device according to claim 1 in an input section.