JP3180647B2 - Recording and playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for digitizing a video signal and an audio signal for recording and reproducing.

[0002]

2. Description of the Related Art In recent years, video tape recorders (hereinafter, abbreviated as VTRs) called D1, D2, and D3 for digitizing and recording and reproducing video signals have been developed as broadcast and business equipment. Also, as consumer equipment,
Video floppy disks capable of recording and reproducing digital still images and VTRs capable of recording digital moving images have been developed.

As a format of a consumer digital VTR, an HD digital VCR conference (HD DIG
Specifications of Consumer Use Digital VCRs compiled by ITAL VCR CONFERENCE)
・ Using ・ 6.3mm ・ Magnetic tape (Speci
fications of Consumer-Use Digital VCRs using 6.3mm
magnetic tape) (hereinafter referred to as DVC format)
There is. An example of development of a consumer digital VTR is described in the Journal of the Institute of Television Engineers of Japan (Vol. 46, No. 10, pages 1222 to 1229, 1992). In these consumer digital VTRs, the degree of redundancy of a video signal is reduced to 1/5 by using high efficiency coding.
It is compressed to the extent of recording.

[0004] A conventional recording and reproducing apparatus will be described below. FIG. 6 is a block diagram showing a configuration of a conventional recording / reproducing apparatus, FIG. 7 is a diagram showing a configuration of a SYNC block for recording, and FIG. 8 is a diagram showing an inner code added by error correction.

In FIG. 6, reference numeral 50 denotes a first input terminal to which a digitized audio signal is input, and the input audio signal is interleaved by an audio signal processor 51 within one frame period of a video signal. 52 is an audio signal processor 51
Is a first output terminal from which an audio signal is output. 53
Is a second input terminal to which a digitized video signal is input, and the input video signal is subjected to compression processing or the like by a video signal processor 54. Reference numeral 55 denotes a second output terminal from which a video signal is output from the video signal processor 54. Reference numeral 56 denotes a third input terminal into which the digitized audio signal and video signal are multiplexed and input in a time-division manner. The signal supplied to the third input terminal 56 is supplied to the interface device 57 and is divided into a video signal and an audio signal. 58 is a third output terminal to which the output signal of the interface unit 57 is supplied. Reference numeral 59 denotes an error corrector for adding an error correction code and error correction; 60, a modulator for performing modulation at the time of recording and demodulation at the time of reproduction; and 61, a recording / reproducing device for recording / reproducing on a recording medium.

[0006] The operation of the conventional recording / reproducing apparatus configured as described above will be described below.

First, the operation at the time of recording will be described. The sampling frequency 48 supplied to the first input terminal 50
The two-channel audio signals of kHz are interleaved after being stored for one frame period of the video signal. Then, the signals are supplied to the error corrector 59 and the interface device 57 using the signal lines A1 and A2.

At the same time, the video signal (8-bit luminance signal (Y signal) sampled at 13.5 MHz, supplied to the second input terminal 53, and the 8-bit 3.3
Two types of color difference signals sampled at 75 MHz (C
_R and C _B signal)) is input to the video signal processor 54.
The video signal processor 54 converts the input video signal into adjacent 8
Discrete cosine transform (DCT) is performed in units of × 8 pixels, converted into sync block unit data (77-byte data in the figure), which is the minimum unit for recording shown in FIG. 7, and error is generated using signal lines V1 and V2. It is supplied to the corrector 59 and the interface unit 57, respectively.

The interface unit 57 is a voice signal processor 5
1 and a signal supplied from the video signal processor 54 are converted into a predetermined signal format, and are output from a third output terminal 58 as a digital signal.

The error corrector 59 includes signal lines A1, V1, S
The delay time of the audio signal and the video signal supplied through the first block is adjusted, and as shown in FIG. 7 and FIG.
And a second error correction code (hereinafter, inner code) C1. The outer code C2 is added in units of a sync block corresponding to one track on a tape serving as a recording medium. The audio signal is a 9-byte 5-byte C2 parity, and the video signal is 138.
An 11-byte C2 parity is added to (= 2 + 135 + 1) bytes. Also, 8 bytes of C1 parity are added to the data of the 77-byte sync block.

However, the sync block data of the audio signal and the video signal includes AUX data as auxiliary data as shown in FIG.

The signal to which the additional information and the error correction code are added by the error corrector 59 is added with a SYNC pattern and an ID as shown in FIG.
4-25 modulated. Here, the SYNC pattern is a pattern indicating the head of the sync block, and the ID is information indicating the position of the data of the sync block as a video signal or an audio signal. The output signal of the modulator 60 is supplied to a recording / reproducing device 61 and recorded on a recording medium (not shown) in sync block units shown in FIG.

Next, the operation at the time of reproduction will be described. The signal reproduced from the recording / reproducing device 61 is supplied to the modulator 60 and decoded. The decoded signal is supplied to an error corrector 59, which detects an error portion generated in the recording / reproducing system from the added error correction code (inner code C1 and outer code C2),
Correct the error. Then, the audio signal is supplied to the audio signal processor 51 and the interface device 57 through the signal lines A1 and S. At the same time, the error corrector 59 transmits the video signal to the video signal processor 5 through the signal lines V1 and S.
1 and the interface unit 57.

The audio signal processor 51 deinterleaves the supplied signal (reverse processing of interleaving) and outputs the signal to a first output terminal 52. The video signal processor 54 also extracts a variable-length code for each DCT block from the supplied signal for each sync block, and decodes the video signal. Then, the decoded video signal is output to the second output terminal 55. The interface unit 57 converts the signal supplied from the error corrector 59 into a predetermined signal format, and outputs the signal from a third output terminal 58 as a digital signal.

Finally, a case where a signal (multiplexed audio signal and video signal) input from the third input terminal 56 is recorded (digital interface recording mode) will be described. In this case, the interface unit 57 extracts the audio signal and the video signal from the supplied digital signal, and supplies them to the audio signal processor 51 and the video signal processor 54 via the signal lines A2 and V2, respectively. At this time, the audio signal processor 51 and the video signal processor 54 perform a reproducing operation. The interface unit 57 simultaneously supplies the audio signal and the video signal to the error corrector 59 using the signal line S.

FIG. 9 shows the transmission order of the digital interface in the DVC format.

[0017]

However, in the above configuration, the audio signal and the video signal transmitted through the signal lines connecting the audio signal processor, the video signal processor, the error corrector, and the interface device are all designed at independent timing. Therefore, the size of the timing circuit becomes large in order to match the delay amount between the audio signal and the video signal output from the interface unit and the delay amount between both signals recorded on the recording medium. This problem is caused by the fact that the signal recorded by the recording / reproducing device is not limited to the conventional NTSC video signal, but also the Hi-Vision signal and the MPEG system (a method of video and audio compression discussed in ISO-IEC / JTCI / SC2 / WG11). It becomes fatal when it is expanded to the signal of In other words, the conventional configuration has a problem that when recording a video signal other than the NTSC system, it is necessary to redesign the timing of all the blocks.

The present invention solves the above-mentioned conventional problems by minimizing the circuit scale of the digital interface device described in the DVC format, and furthermore, even if a signal to be recorded is changed or added, the circuit after the error correction device is changed. It is an object of the present invention to provide a recording and reproducing apparatus that can be shared.

[0019]

In order to achieve this object, a recording / reproducing apparatus according to the present invention performs predetermined processing on an audio signal and a video signal in a recording state, and then converts the signal into a signal in block units and outputs the signal. Application processing means for inversely converting a block unit signal into an audio signal and a video signal in a reproducing state, and adding an error correction code to the block unit signal in a recording state, and then performing digital modulation on a recording medium. A data recorder processing means for demodulating a signal reproduced from a recording medium in a recording and reproducing state, correcting an error and outputting a block unit signal, a signal generated by an application processing means and generated by a data recorder processing means And the number of audio signal blocks to be recorded in one track of the recording medium are determined by one bus. Similarly, the number of audio signal blocks divided by the greatest common divisor of the number of audio signal blocks to be recorded and the number of video signal blocks, and the number of video signal blocks to be recorded in one track of the recording medium are also the greatest common divisor And a bus transmission unit for performing transmission with the number of video signal blocks divided by as one transmission unit.

According to the present invention, since the signal on the bus can be used as it is for the signal for the digital interface, the communication with the external device can be easily realized. In particular, since the audio signal block and the video signal block are evenly arranged in the minimum unit, the arrangement is optimal for a digital interface, and an interface unit can be realized with a minimum number of circuits.

Also, when the specifications of the signals processed by the audio signal processor and the video signal processor change, there is no need to change the circuit configuration after the error corrector.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is to perform a predetermined process on an audio signal and a video signal in a recording state, convert the audio signal and the video signal into an audio signal block and a video signal block which are signals in block units, and output the converted signal. Application processing means for inversely converting the audio signal block and the video signal block into an audio signal and a video signal at the time of recording, and adding an error correction code to the audio signal block and the video signal block during a recording state, and then performing digital modulation. Data recorder processing means for performing demodulation, demodulating a signal reproduced from the recording medium in a reproduction state, correcting an error, and outputting the audio signal block and the video signal block, and the application processing. The signal generated by the means and the signal generated by the data recorder processing means are combined by one bus. The number of audio signal blocks obtained by dividing the number of audio signal blocks recorded in one track of the recording medium by the greatest common divisor of the number of audio signal blocks recorded in one track of the recording medium and the number of video signal blocks A recording / reproducing apparatus comprising: a bus transmission unit configured to transmit the number of video signal blocks to be recorded in one track of the recording medium by the greatest common divisor as one transmission unit. The signals on the bus are arranged in the minimum combination of the audio signal block and the video signal block, and the audio signal block and the video signal block are arranged evenly in an array on the bus.

Alternatively, a predetermined process is performed on an audio signal and a video signal in a recording state, and then converted and output into a block unit signal. In a reproduction state, the block unit signal is inverted to an audio signal and a video signal. Application processing means for converting, after adding an error correction code to the block unit signal in a recording state, performing digital modulation and recording the signal on a recording medium, and demodulating a signal reproduced from the recording medium in a reproduction state. A data recorder processing unit for correcting an error and outputting a signal in block units; a signal generated by the application processing unit and a signal generated by the data recorder processing unit are coupled by a single bus; One sector is composed of the same number of blocks as one block to be recorded on one track of the medium, and one sector is composed of a plurality of sectors. And the sector is a recording / reproducing apparatus having a bus transmission means for equally dividing one frame. The signal on the bus is substantially time-dependent in one frame in one block. They are arranged uniformly.

[0024]

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a recording / reproducing apparatus according to an embodiment of the present invention, FIG. 2 is a timing diagram of a data bus of the apparatus, FIG. 3 is an explanatory diagram of a frame structure of the data bus, and FIG. Explanatory diagram,
FIG. 5 is an explanatory diagram of the block structure of the data bus.

In FIG. 1, reference numeral 1 denotes a first input terminal to which a digitized audio signal is input. The input audio signal is interleaved by an audio signal processor 2 within one frame period of a video signal. Reference numeral 3 denotes a first output terminal from which an audio signal is output from the audio signal processor 2. Reference numeral 4 denotes a second input terminal to which a digitized video signal is input. The input video signal is subjected to a compression process or the like by a video signal processor 5. Reference numeral 6 denotes a second output terminal from which a video signal is output from the video signal processor 5. Reference numeral 7 denotes an application processing unit as application processing means constituted by the audio signal processor 2 and the video signal processor 5. Reference numeral 8 denotes a third input terminal to which the digitized audio signal and video signal are multiplexed and input in a time-division manner. The signal supplied to the third input terminal 8 is supplied to the interface unit 9 and is divided into a video signal and an audio signal. 10 is an interface unit 9
Is a third output terminal from which a signal is output. An error corrector 11 adds an error correction code and corrects an error.
Is a modulator / demodulator for performing modulation for recording and demodulation for reproduction.
Reference numeral 13 denotes a data recorder processing unit as a data recorder processing means constituted by the error corrector 11 and the modem 12. Reference numeral 14 denotes a recording / reproducing device 14 which records an output signal of the modem 12 on a recording medium, reproduces the signal from the recording medium, and outputs the reproduced signal to the modem 12.

A data bus 15 is a bus through which a signal including an audio signal block and a video signal block flows.
Audio signal processor 2, video signal processor 5, and error corrector 1
1 and the interface unit 9 are connected.

First, the operation at the time of recording will be described. Sampling frequency 48 k supplied to the first input terminal 1
The two-channel audio signals of Hz are interleaved after being stored for one frame period of the video signal. The audio signal processor 2 converts the interleaved signal into an audio AUX (Audio composed of additional information such as a sampling frequency).
-AUX signal) to form a block having a length of 77 bytes and output it on the data bus as an audio signal block.
The audio signal output on the data bus is supplied to the interface unit 9 and the error correction unit 11.

At the same time, the video signal supplied to the second input terminal 4 (a luminance signal (Y signal) sampled at 13.5 MHz in 8 bits, and a 3.37 signal in 8 bits as well)
Two types of color difference signals (C _R) sampled at 5 MHz
And _CB signals) are input to the video signal processor 5. The video signal processor 5 converts the input video signal into an adjacent 8 × 8
Discrete cosine transform (DCT) is performed on a pixel basis, and is converted into sync block unit data (77-byte data in the figure) which is the minimum unit for recording shown in FIG.
Output to

The video signal output to the data bus 15 is supplied to the interface unit 9 and the error corrector 11.
At this time, the video signal processor 5 also outputs the video AUX (Video-AUX or VAUX) shown in FIG. 8 to the data bus.

The interface unit 9 outputs the signal on the data bus 15 from the third output terminal 10 as it is.

However, the sync block data of the audio signal and the video signal includes AUX data as auxiliary data as shown in FIG.

The error corrector 11 outputs a video signal (a signal in units of 77-byte sync blocks) on the data bus 15,
Audio-AUX and audio signal (in units of 77 bytes), V
The video-AUX is extracted from the data bus 15. Then, these signals are collected in units of one track, as shown in FIG. 8, and error correction codes (inner code C1 and outer code C2) are added. On the data bus 15, the delay time of the audio signal and that of the video signal are the same. The signal format in FIG. 8 is a signal format per track recorded on the recording medium. Here, the ID in FIG. 8, Audio-AUX
(AUX for audio) and Video-AUX (AUX for video) are additional information signals such as audio sample frequency and time code, and SYNC is a synchronization signal.

The signal to which the additional information and the error correction code have been added by the error corrector 11 is supplied from the error corrector 11 after adding the SYNC pattern and the ID as shown in FIG. 24-25 for removing the DC component and generating a pilot signal at the time of reproduction
Perform modulation. The output signal of the modulator / demodulator 12 is supplied to a recording / reproducing device 14.
And recorded on a recording medium (not shown).

Next, the structure of a signal placed on the data bus 15 will be described with reference to FIGS.

The data bus 15 is composed of a signal (SSP) indicating the head of a sector, a signal (SMP) indicating the head of a block, and 4-bit data (BD) (see FIG. 2). The data bus 15 has an 18 MHz clock (CLK
18).

The data bus 15 is composed of a frame, a sector, a group, and a block.

First, the structure of the frame will be described.
A case where an NTSC (525/60) video signal is recorded at 10 tracks per frame on a tape as a recording medium will be described. Hereinafter, this method is referred to as SD: 52
Called 5/60. As shown in FIG. 3, one frame is composed of 10 sectors (Sector0 to Sector9) and 40 clocks (clk).
And a blank. As described above, one frame is constituted by sectors which are almost equally divided by the number of recording tracks.

A case where a PAL (625/50) video signal is recorded on a recording medium at 12 tracks per frame will be described. Hereinafter, this method is referred to as SD: 625 /
Called 50. As shown in FIG. 3, one frame is composed of 12 sectors (Sector0 to Sector11). Thus, one frame is composed of sectors equally divided by the number of recording tracks.

Next, as a case of recording on a tape in the high compression mode, the NTSC system video signal is further recorded on the tape by five tracks which is a half number of tracks, and the PAL system video signal is further recorded by a half track number of 6 tracks. Consider the mode recorded above. In this case, the video signal processor 5
Is a circuit having a compression ratio twice as high as that of the processing described above.

A case where a video signal of the NTSC system (525/60) is recorded with high compression will be described. Hereinafter, this method is referred to as SD-L: 525/60. As shown in FIG. 3, one frame includes five sectors (Sector0 to Sector4) and 40 sectors.
And a clock blank. Like this one
The frame is composed of sectors that are almost equally divided by the number of recording tracks.

The case of recording a video signal of the PAL system (625/50) at high compression will be described. Hereinafter, this method is referred to as SD-L: 625/50. As shown in FIG.
The frame is composed of six sectors (Sector0 to Sector5). Thus, one frame is composed of sectors equally divided by the number of recording tracks.

Next, the configuration of a sector will be described. S
In the case of D: 525/60 and SD: 625/50, 1
The sectors are grouped into 28 groups (Grou) as shown in FIG.
p0 to Group27) and blank. SD: 5
In the case of 25/60, the blank is 248 (= 16 + 23)
2) Clock, and blank in the case of SD: 625/50 is 192 (= 16 + 176) clocks.

SD-L: 525/60 and SD-L:
In the case of 625/50, one sector is composed of 56 groups (Group 0 to Group 55) and blanks as shown in FIG. This is SD: 525/60 and SD:
This is a structure in which two 625/50 sector configurations are connected to form one sector.

Note that a signal called SSP is used to indicate the head of a sector. The group is composed of six blocks (Block0 to Block5) as shown in FIG. SD: 5
In the case of 25/60 and SD: 625/50, the block configuration is as follows.

Group 0 is a control block × 1, S
It consists of 6 blocks of ubCode block x 2 and VAUX block x 3. Group (3n + 1) includes an audio signal block × 1 and a video signal block × 5.
n + 2) is a dummy block × 1, a video signal block ×
Group (3n + 3) is composed of a dummy block × 1 and a video signal block × 5. Note that n is
It takes a value of n = 0 to 8.

Further, SD-L: 525/60 and SD
In the case of -L: 625/50, the block configuration is as follows.

Group 1 is a control block × 1, S
ubCode block × 2, VAUX block × 3, and 6 blocks, and Group (6n + 3) is composed of audio signal block × 1, video signal block × 5, and Group (6
n + 5) is a dummy block × 1, a video signal block ×
Group (6n + 7) is composed of a dummy block × 1 and a video signal block × 5.
m has a configuration with no access block. In addition,
m and n take values of m = 0 to 27 and n = 0 to 8.

That is, the group includes one block storing the control signal, one block storing the Sub-Code, and three blocks storing the Video-AUX, and one block storing the audio signal. And a group consisting of five blocks storing video signals, and a group consisting of one dummy block and five blocks storing video signals.

In this embodiment, the ratio of the signal amounts output from the audio signal processor 2 and the video signal processor 5 is 1:15.
After outputting one audio signal block on the data bus, 15 video signal blocks are output.

In the case of the high compression mode (SD-L),
By accessing every other group, the data amount is reduced by half.

As described above, a 77-byte unit signal to which the inner code C1 on the data bus 15 is added is stored in one block and transmitted. The minimum unit of the signal on the data bus 15 is the same as the unit added with SYNC and recorded on the recording medium.

By connecting the application processing unit 7, the data recorder processing unit 13, and the interface unit 9 via the block unit bus, the versatility of the recording / reproducing unit 14 is greatly expanded.

The data bus 15 performs transmission at a cycle of one audio signal block and 15 video signal blocks. This transmission method is the same as the digital interface specification in the DVC format (see FIG. 9), and as a result, the interface unit 9 can be formed with a minimum circuit.

Further, the audio signal block and the video signal block are distributed as uniformly as possible in the frame (FIG. 3).
5 to FIG. 5), the memory of the interface unit 9 can be minimized.

In the present embodiment, an example of high-compression recording having 1/2 times the information amount (SD-L: 525/60, SD-L
L: 625/50), transmission is possible only by halving the group used for the data bus 15 of SD: 525/60 or SD: 625/50. That is, high-compression recording can be performed without largely changing the processing specifications of the interface unit of the application processing unit 7 and the data recorder processing unit 13.

When a signal different from a video signal or an audio signal (for example, data for a computer) is recorded, a signal in units of 77 bytes is supplied to the data recorder processing unit 13 via the interface unit 9. The recording / reproducing device 14 can be used as a data recorder.

Next, the operation at the time of reproduction will be described. The signal reproduced from the recording / reproducing device 14 is supplied to the modem 12 and decoded. The decoded signal is supplied to the error corrector 11. The error corrector 11 uses an error correction code (inner code C
1 and an outer code C2) to detect an error portion generated in the recording / reproducing system and correct the error. Then, an audio signal of 72 × 9 bytes per track is supplied to the audio signal processor 2 and the interface unit 9 via the data bus 15. At the same time, the error corrector 11
A video signal of bytes (1 sync block) × 135 is supplied to the video signal processor 5 and the interface unit 9 via the data bus 15.

The audio signal processor 2 deinterleaves the supplied signal and outputs it to the first output terminal 3. The video signal processor 5 also calculates D from the supplied signal in sync block units.
A variable length code is extracted for each CT block, this signal is decoded into an original video signal, and output to the second output terminal 6.
The interface device 9 outputs the signal supplied from the data bus 15 to the third output terminal 10 as it is.

As described above, according to the present embodiment, in the recording state, the audio signal and the video signal are subjected to predetermined processing, then converted into a signal in block units, and output. And an application processing unit 7 for inversely converting the signal into an audio signal and a video signal, and after adding an error correction code to the block unit signal in a recording state,
Data is recorded on a recording medium by performing digital modulation, and in a reproduction state, a signal reproduced from the recording medium is demodulated, an error is corrected, and a data recorder processing unit 13 that outputs a signal in block units is generated by an application processing unit 7. The signal to be recorded and the signal generated by the data recorder processing unit 13 are combined by one data bus 15, and the number of audio signal blocks to be recorded in one track of the recording medium is recorded in one track of the recording medium. The greatest common divisor of the number of blocks and the number of video signal blocks (9 in this embodiment)
Divided by the number of audio signal blocks and the number of video signal blocks to be recorded in one track of the recording medium.
The number of video signal blocks divided by the greatest common divisor of the number of audio signal blocks and the number of video signal blocks to be recorded in a track is transmitted as one transmission unit, and the arrangement of the audio signal blocks and the video signal blocks is determined by the digital interface. The interface unit 9 can be realized with a minimum circuit scale by arranging the blocks in the same order as the transmission order and almost uniformly over one frame. Also, when the specifications of the signals processed by the audio signal processor 2 and the video signal processor 5 change, it is not necessary to change the specifications of the error corrector 11 and thereafter (data recorder processing unit 13). A signal (data) other than a video signal and an audio signal is put on the data area on the data bus 15 and supplied to the data recorder processing unit 13 via a digital interface, so that it can be easily used as a data recorder such as a computer. Therefore, the versatility of the recording / reproducing apparatus can be greatly expanded. At this time, there is almost no need to increase the circuit of the interface unit 9.

In this embodiment, the data bus 1
Although the signal is directly input / output to / from the external device via the interface unit 9, a new block may be formed based on a 77-byte block. In this case, an identification signal may be added to the block to perform packet transmission in which the order of the blocks is arbitrary.

Further, the block of the video signal included in one sector does not need to match the signal stored in one track of the recording medium. This is for shuffling blocks within one frame to improve image quality during high-speed reproduction or slow reproduction.

[0063]

As described above, according to the present invention, communication with an external device can be easily realized by directly using the signal on the bus as a signal for the digital interface. In particular,
By arranging the audio signal blocks and the video signal blocks in the same order as the transmission order of the digital interface and arranging the blocks substantially uniformly over one frame, the circuit scale of the digital interface unit can be minimized.

Further, even when the specification of the signal processed by the application processing means changes, it is not necessary to change the specification of the data recorder processing means.

Further, a signal (data) other than a video signal and an audio signal is put on the data area on the bus and supplied to the data recorder processing means via a digital interface, so that it can be easily used as a data recorder for a computer or the like. Therefore, the versatility of the recording / reproducing apparatus can be greatly expanded, and its practical effect is great.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a recording / reproducing apparatus according to an embodiment of the present invention.

FIG. 2 is a signal timing chart of a bus according to the embodiment;

FIG. 3 is a diagram showing a bus frame configuration according to the embodiment;

FIG. 4 is a diagram showing a bus sector configuration according to the embodiment;

FIG. 5 is a diagram showing a bus group configuration according to the embodiment;

FIG. 6 is a block diagram showing a configuration of a conventional recording / reproducing apparatus.

FIG. 7 is an explanatory diagram showing a configuration of a sync block.

FIG. 8 is an explanatory diagram showing an error correction code.

FIG. 9 is an explanatory diagram of a digital interface of a conventional example.

[Explanation of symbols]

 2 audio signal processor 5 video signal processor 7 application processing unit 9 interface unit 11 error correction unit 12 modulator / demodulator 13 data recorder processing unit 14 recording / reproducing unit 15 data bus

Continuation of front page (72) Inventor Masashi Sato 1006 Kazuma Kadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (56) References JP-A-7-23335 (JP, A) (58) Fields investigated (Int .Cl. ⁷ , DB name) H04N 5/91-5/596 G11B 20/10-20/12 H04N ^7/ 24-7/68

Claims (6)

(57) [Claims] An audio signal and a video signal are subjected to predetermined processing in a recording state, converted into an audio signal block and a video signal block which are signals in block units, and output, and in a reproduction state, the audio signal block is outputted. And an application processing means for inversely converting the video signal block into an audio signal and a video signal; and, in a recording state, after adding an error correction code to the audio signal block and the video signal block, performing digital modulation on a recording medium. A data recorder processing unit that demodulates a signal reproduced from the recording medium in a recording and reproduction state, corrects an error, and outputs the audio signal block and the video signal block; and a signal generated by the application processing unit. And a signal generated by the data recorder processing means are connected by one bus, and The number of audio signal blocks to be recorded in a track divided by the greatest common divisor of the number of audio signal blocks to be recorded in one track of the recording medium and the number of video signal blocks; A bus transmission means for transmitting the number of video signal blocks to be recorded in one track by the maximum common divisor and the number of video signal blocks as one transmission unit. 2. The recording / reproducing apparatus according to claim 1, wherein the transmission unit is composed of one audio signal block and 15 video signal blocks. 3. The transmission unit according to claim 1, wherein a video signal block is arranged after the audio signal block.
Or the recording / reproducing apparatus according to 2. 4. A signal on a bus is composed of an audio signal block and a video signal block corresponding to the number of blocks to be recorded on one track of a recording medium, and a plurality of sectors are collected to generate a signal of one frame. The recording / reproducing apparatus according to claim 1, wherein the recording / reproducing apparatus is formed. 5. In a recording state, after performing predetermined processing on an audio signal and a video signal, the signal is converted into a block unit signal and output, and in a reproduction state, the block unit signal is inverted to an audio signal and a video signal. Application processing means for converting, after adding an error correction code to the signal in block units in a recording state, performing digital modulation and recording on a recording medium, and demodulating a signal reproduced from the recording medium in a reproducing state. A data recorder processing unit for correcting an error and outputting a block-based signal; a signal generated by the application processing unit and a signal generated by the data recorder processing unit are coupled by one bus; One sector is composed of the same number of blocks as one block to be recorded on one track of the medium, and one frame is composed of a plurality of sectors. Forming a signal, and the sector recording and reproducing apparatus and a bus transmission means for equally dividing one frame. 6. A recording and reproducing apparatus according to claim 1 or 5, wherein the use in the digital interface signals connected to the external device a signal of the block unit on the bus.