JP2000149456A - Data processor and processing method, and data recorder and recording method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable dealing with each of plural shuffling patterns of audio data. SOLUTION: Audio data of 8 channels are supplied to a block 11, rate- converted by RAM 13 (A, B), an outer code parity is given by a block 14, and packetized. The number of outer code is given to every packet. A table by which a shuffling is performed with a channel unit based on the number of outer code is externally loaded in accordance with a format and stored in a RAM 15, and a table by which a shuffling is performed with a channel unit based on the result of shuffling by the RAM 15 is externally loaded in accordance with a format and stored in a RAM 16. Output of the RAM 16 is further shuffled with a track unit, and outputted as an address of a SDRAM 18. Packets are stored in a SDRAM 18 in order of recording by this address. An inner code parity is given to a packet outputted from the SDRAM 18 in order of recording, and recorded in a magnetic tape.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus and method for rearranging audio data in a predetermined length block unit, for example, on a tape-shaped recording medium in a different order from the original order, and And a data recording apparatus and method.

[0002]

2. Description of the Related Art In recent years, digital video tape recorders, which use a magnetic tape as a recording medium and record and reproduce digital video signals and digital audio signals, are becoming widespread.

In such a device, digital video data and digital audio data are subjected to error correction coding using, for example, a product code, and an outer code parity and an inner code parity are added. A block completed with the outer code parity and the inner code parity is called an error correction block. For example, one line of the inner code direction of the error-correction-coded data is stored in units of packets of a predetermined length, and each packet has a sync pattern for synchronization detection, a block ID for identifying each packet, and a data ID. A sync block is configured by adding an ID representing the content and a parity for error correction. Then, the sync blocks are grouped into sectors according to the type of data, and are recorded on the magnetic tape as serial data in sector units. Recording is performed by a helical scan method in which tracks are formed diagonally on a magnetic tape by a rotating head.

FIG. 37 schematically shows an example of the arrangement of each sector on a track. The rotating head traces from the left side to the right side of the figure to form a track. As described above, the track is actually formed obliquely with respect to the magnetic tape, and one frame of video data is recorded using a plurality of, for example, four tracks. A plurality of audio sectors for recording audio data are arranged between video sectors for recording video data. In this example, 4
In each of the tracks, 8 of Ch1 to Ch8
Since audio signals for channels can be handled, eight audio sectors A1 to A8 are arranged. An edit gap (EG) in which audio data is not recorded is arranged between the sectors so that, for example, insert editing can be performed in units of sectors of the audio signal. Such a recording pattern on a tape is called a footprint.

In actual recording, data is rearranged so that the order of the data is different from the original order in order to increase the resistance to read errors during reproduction due to scratches and stains on the tape. . This is called shuffling. In the case of audio data, shuffling is performed in units of sectors for each track, and shuffling is performed in units of sync blocks. The shuffling pattern is previously stored in, for example, an IC (integrated circuit) that encodes audio data.

[0006]

On the other hand, in an environment such as the development of digital broadcasting, video and audio formats (field frequency, number of lines, interlace / progressive, screen size, aspect ratio, etc.)
There are many types. Therefore, the video,
It is desired that a digital video tape recorder supports a plurality of audio formats.

Conventionally, an IC that performs the above-described shuffling is adapted to only a specific recording format, and has only one type of shuffling pattern dedicated to that format. Therefore, for example, in order to support a plurality of formats, it is necessary to provide a plurality of processing means (ICs) dedicated to each format capable of processing shuffling patterns of each format in one model, and to switch between them. Was. As described above, in the related art, there is a problem in that the flexibility for supporting a plurality of formats is lacking.

Accordingly, it is an object of the present invention to provide a data processing apparatus and method, and a data recording apparatus and method that can correspond to each of a plurality of shuffling patterns.

[0009]

According to the present invention, in order to solve the above-mentioned problems, digital audio data of a plurality of channels is stored for each packet of a predetermined length, and the digital audio data is stored in the original order in packet units. In a data processing device that rearranges data in a different order, a shuffling table is stored, position information indicating a position of a packet unit in an input data sequence is supplied as an address, and converted position information obtained by converting position information according to the shuffling table is converted. A data processing apparatus comprising: a shuffling table memory for outputting; and a means for storing a shuffling table selected from a plurality of different shuffling tables in the shuffling table memory.

The present invention also provides a data processing apparatus for storing digital audio data of a plurality of channels for each packet of a predetermined length, and for rearranging the digital audio data in a packet unit in an order different from the original order. A first shuffling unit that rearranges an input data sequence composed of a plurality of channels input in packet units in packet units, and a second shuffling unit that rearranges data rearranged in the first shuffling unit in channel units. A data processing apparatus comprising: a second shuffling unit; and a third shuffling unit for rearranging the data rearranged by the second shuffling unit in units of a plurality of channels. .

Further, according to the present invention, a plurality of channels of digital audio data are stored for each packet of a predetermined length, and the digital audio data is rearranged in a packet unit in an order different from the original order, thereby forming a track unit comprising a plurality of channels. In a data recording apparatus for recording on a recording medium, data storage memory means for storing input data and a shuffling table are stored, and position information indicating a position of a packet unit in the input data sequence is supplied as an address, and shuffling is performed. A shuffling table memory means for outputting a write or read address of a data storage memory by converting position information according to the table, and a shuffling table selected from a plurality of shuffling tables different from each other. A shuffling table storage means for storing the error correction code for at least one of the input data and the output data of the data storage memory; and an error correction encoder for performing error correction encoding by the error correction encoder. Recording means for recording the recorded data on a recording medium.

The present invention also provides a data processing method for storing digital audio data of a plurality of channels for each packet of a predetermined length and rearranging the digital audio data in a packet unit in an order different from the original order. Is stored in a shuffling table memory, position information indicating a position in a packet unit in the input data sequence is supplied as an address, and according to the shuffling table, a step of outputting converted position information obtained by converting the position information is performed. Storing the selected shuffling table from the shuffling tables in the shuffling table memory.

Further, the present invention provides a data processing method for storing digital audio data of a plurality of channels for each packet of a predetermined length and rearranging the digital audio data in a packet unit in an order different from the original order. A first shuffling step of rearranging an input data sequence composed of a plurality of channels input in packet units in packet units, and data rearranged in the first shuffling step are further arranged in channel units. A second shuffling step of rearranging, and a third shuffling step of rearranging the data rearranged in the second shuffling step in units of a plurality of channels. It is a data processing method.

Further, according to the present invention, the digital audio data of a plurality of channels is stored for each packet of a predetermined length, and the digital audio data is rearranged in a packet unit in an order different from the original order, so that a track unit composed of a plurality of channels is arranged. In the data recording method for recording on a recording medium, a step of storing input data in a data storage memory, a shuffling table is stored in the shuffling table memory, and position information indicating a position of a packet unit in the input data sequence is an address. Outputting the write or read address of the data storage memory by converting the position information according to the shuffling table, and shuffling the selected shuffling table among a plurality of different shuffling tables. A step of storing a shuffling table to be stored in a table memory, a step of performing error correction coding for coding at least one of input data and output data of a data storage memory, and a step of performing error correction coding. Recording the error-correction-encoded data on a recording medium by the step.

As described above, the present invention according to claim 1, claim 8, claim 11, or claim 13 is characterized in that the shuffling table is stored in the shuffling table and the input data sequence is stored in the shuffling table. Is supplied as an address. With this address, converted position information obtained by converting the position information based on the shuffling table is output, and the shuffling table selected from a plurality of mutually different shuffling tables is output. Since the ring table is stored in the shuffling table memory, it is possible to flexibly adapt to different shuffling patterns.

According to the seventh or twelfth aspect of the present invention, the audio data is shuffled stepwise by the first, second and third shufflings. Can be done on a small scale.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to digital VC.
An embodiment applied to R will be described. This embodiment is suitable for use in a broadcast station environment,
Recording and recording of video signals of multiple different formats
It enables playback. For example, a signal (480i signal) having 480 effective lines in the interlaced scanning based on the NTSC system and a signal (576 signals) having 576 effective lines in the interlaced scanning based on the PAL system.
i) are recorded with almost no hardware changes.
It is possible to reproduce. Furthermore, a signal having 1080 lines (1080i signal) in interlaced scanning,
In progressive scanning (non-interlace), the number of lines is 480, 720, and 1080, respectively.
Recording / reproduction such as 0p signal, 720p signal, and 1080p signal) can also be performed.

Further, in this embodiment, the video signal is compression-coded based on the MPEG2 system, and the audio signal is handled uncompressed. As is well known, MPEG
No. 2 is a combination of motion compensation predictive coding and compression coding by DCT. The data structure of MPEG2 has a hierarchical structure, and includes a block layer, a macroblock layer, a slice layer, a picture layer, a GOP layer, and a sequence layer from the lowest level.

The block layer is a unit for performing DCT, D
It consists of a CT block. The macroblock layer includes a plurality of D
It is composed of CT blocks. The slice layer is composed of a header section and any number of macroblocks that do not extend between rows. The picture layer includes a header section and a plurality of slices. A picture corresponds to one screen. G
The OP (Group Of Picture) layer includes a header portion, an I picture that is a picture based on intra-frame coding, and P and B pictures that are pictures based on predictive coding.

A GOP includes at least one I picture, and P and B pictures are allowed even if they do not exist. The top sequence layer is composed of a header section and multiple GOPs.
It is composed of

In the MPEG format, a slice is one variable length code sequence. A variable-length code sequence is a sequence in which a data boundary cannot be detected unless a variable-length code is decoded.

At the head of the sequence layer, GOP layer, picture layer, slice layer, and macroblock layer, an identification code (referred to as a start code) having a predetermined bit pattern arranged in byte units is provided. Be placed. Note that the header section of each layer described above collectively describes a header, extension data, or user data. In the header of the sequence layer, the size of the image (picture) (the number of vertical and horizontal pixels) and the like are described. The time code, the number of pictures constituting the GOP, and the like are described in the header of the GOP layer.

The macro blocks included in the slice layer are:
It is a set of a plurality of DCT blocks, and the encoded sequence of the DCT block is a variable of a sequence of quantized DCT coefficients, with the number of consecutive 0 coefficients (run) and a non-zero sequence (level) immediately after it as one unit. It is a long code. The macroblock and the DCT block in the macroblock are not added with the identification codes arranged in byte units.
That is, they are not one variable-length code sequence.

A macroblock is a screen (picture) of 1
It is divided into a grid of 6 pixels × 16 lines. A slice is formed by connecting these macroblocks in the horizontal direction, for example. The last macroblock of the previous slice of a continuous slice and the first macroblock of the next slice are continuous, and it is not allowed to form a macroblock overlap between slices. When the size of the screen is determined, the number of macroblocks per screen is uniquely determined.

On the other hand, in order to avoid signal degradation due to decoding and encoding, it is desirable to edit the encoded data. At this time, the P picture and the B picture require a temporally preceding picture or a preceding and succeeding picture for decoding. Therefore, the editing unit cannot be set to one frame unit. In consideration of this point, in this embodiment, one GOP is made up of one I picture.

The recording area in which, for example, one frame of recording data is recorded is predetermined. MPEG2
Since the variable length coding is used, the amount of generated data for one frame is controlled so that data generated during one frame period can be recorded in a predetermined recording area. Further, in this embodiment, one slice is composed of one macroblock so as to be suitable for recording on a magnetic tape, and one macroblock is applied to a fixed frame having a predetermined length.

FIG. 1 shows an example of the configuration on the recording side of the recording / reproducing apparatus according to this embodiment. At the time of recording, a predetermined interface, for example, SDI (Serial Data Interface)
The digital video signal is input from the terminal 101 via the receiving unit of the above. SDI is an interface defined by SMPTE for transmitting (4: 2: 2) component video signals, digital audio signals, and additional data. An input video signal is converted by a video encoder 102 into a DCT (Discrete Cosine Transform).
form), is converted into coefficient data, and the coefficient data is subjected to variable length coding. The variable length coded (VLC) data from the video encoder 102 is an elementary stream compliant with MPEG2. This output is supplied to one input terminal of the selector 103.

On the other hand, through the input terminal 104, the ANSI
SDTI (Serial Data Transport Inter), which is an interface defined by / SMPTE 305M
face) format data is input. This signal is synchronously detected by SDTI receiving section 105. And
Once stored in the buffer, the elementary stream is extracted. The extracted elementary stream is supplied to the other input terminal of the selector 103.

The elementary stream selected and output by the selector 103 is supplied to a stream converter 106. In the stream converter 106, the MPE
The DCT coefficients arranged for each DCT block based on the G2 rule are replaced with a plurality of DCTs constituting one macroblock.
Through the T block, frequency components are grouped, and the grouped frequency components are rearranged. The rearranged converted elementary stream is stored in the packing and shuffling unit 1.
07.

Since the video data of the elementary stream is variable-length coded, the data length of each macroblock is not uniform. In the packing and shuffling unit 107, macro blocks are packed in a fixed frame. At this time, the portion that protrudes from the fixed frame is sequentially packed into a surplus portion with respect to the size of the fixed frame. Also, system data such as time code is input to the input terminal 108.
Is supplied to the packing and shuffling unit 107, and the system data is subjected to a recording process similarly to the picture data. Also, shuffling is performed in which the macroblocks of one frame generated in the scanning order are rearranged and the recording positions of the macroblocks on the tape are dispersed. Shuffling can improve the image update rate even when data is reproduced in pieces during variable speed reproduction.

Video data and system data from the packing and shuffling unit 107 (hereinafter, also referred to as video data even when system data is included unless otherwise required) are supplied to the outer code encoder 109. A product code is used as an error correction code for video data and audio data. The product code encodes an outer code in a vertical direction of a two-dimensional array of video data or audio data, encodes an inner code in a horizontal direction thereof, and encodes data symbols doubly. As the outer code and the inner code, a Reed-Solomon code can be used.

The output of the outer code encoder 109 is supplied to a shuffling unit 110 and a plurality of ECCs (Error Correction
ig Code) blocks are shuffled to change the order in sync block units. The shuffling in sync block units prevents errors from concentrating on a specific ECC block. Shuffling part 1
Shuffling performed at 10 may be referred to as interleaving. The output of the shuffling unit 110 is
1 and mixed with audio data. In addition,
The mixing unit 111 includes a main memory, as described later.

Audio data is supplied from an input terminal denoted by reference numeral 112. In this embodiment, an uncompressed digital audio signal is handled. The digital audio signal is supplied to an input SDI receiver (not shown)
These are separated by the DTI receiving unit 105 or input through an audio interface. The input digital audio signal is supplied to A
It is supplied to the UX adding unit 114. The delay unit 113 is for time alignment of the audio signal and the video signal.
The audio AUX supplied from the input terminal 115 is auxiliary data, and is data having information related to audio data such as the sampling frequency of audio data. The audio AUX is added to the audio data by the AUX adding unit 114, and is treated the same as the audio data.

The audio data and AUX from the AUX adding unit 114 (hereinafter, AUX unless otherwise necessary)
Is also simply referred to as audio data. ) Is supplied to the outer code encoder 116. Outer code encoder 11
No. 6 encodes an outer code for audio data. The output of the outer code encoder 116 is the shuffling unit 1
17 and undergoes a shuffling process. As audio shuffling, shuffling in sync block units and shuffling in channel units are performed.

The output of the shuffling unit 117 is
1 and the video data and the audio data are converted into data of one channel. The output of the mixing unit 111 is ID
The adding unit 118 is supplied, and the ID adding unit 118 adds an ID including information indicating a sync block number. The output of the ID addition unit 118 is the inner code encoder 119
, And the inner code is encoded. Further, the output of the inner code encoder 119 is supplied to the synchronization adding section 120, and a synchronization signal for each sync block is added. By adding the synchronization signal, recording data in which the sync blocks are continuous is configured. This recording data is supplied to the rotary head 122 via the recording amplifier 121, and is recorded on the magnetic tape 123. In practice, the rotary head 122 is configured such that a plurality of magnetic heads having different azimuths of heads forming adjacent tracks are attached to the rotary drum.

The recording data may be subjected to scramble processing as required. Further, digital modulation may be performed at the time of recording, and a partial response class 4 and Viterbi code may be used.

Recording of a signal on a magnetic tape is performed by a helical scan method in which a diagonal track is formed by a magnetic head provided on a rotating rotary head. A plurality of magnetic heads are provided on the rotating drum at positions facing each other. That is, when the magnetic tape is wound around the rotary head at a winding angle of about 180 °, a plurality of tracks can be simultaneously formed by rotating the rotary head by 180 °. The magnetic heads are formed as a set of two magnetic heads having different azimuths. The plurality of magnetic heads are arranged such that azimuths of adjacent tracks are different from each other.

FIG. 2 shows an example of the configuration on the reproducing side according to an embodiment of the present invention. Rotating head 1 from magnetic tape 123
The reproduction signal reproduced at 22 is supplied to the synchronization detection unit 132 via the reproduction amplifier 131. Equalization and waveform shaping are performed on the reproduced signal. Further, demodulation of digital modulation, Viterbi decoding, and the like are performed as necessary. The synchronization detection unit 132 detects a synchronization signal added to the head of the sync block. The sync block is cut out by the synchronization detection.

The output of the synchronization detection block 132 is supplied to the inner code encoder 133, where the error of the inner code is corrected. The output of the inner code encoder 133 is the ID interpolation unit 13
The ID of the sync block, which has been supplied to the block No. 4 and made an error by the inner code, for example, a sync block number is interpolated. I
The output of the D interpolation unit 134 is supplied to a separation unit 135, where the video data and the audio data are separated. As described above, video data means DCT coefficient data and system data generated by MPEG intra coding, and audio data is PCM (Pulse Code Modulati
on) means data and AUX.

The video data from the separation unit 135 is subjected to the reverse processing of the shuffling in the deshuffling unit 136. The deshuffling unit 136 performs a process of restoring the shuffling in sync block units performed by the shuffling unit 110 on the recording side. Deshuffling part 136
Is supplied to the outer code decoder 137, and error correction by the outer code is performed. When an error that cannot be corrected occurs, an error flag indicating the presence or absence of the error is set to indicate the presence of the error.

The output of the outer code decoder 137 is supplied to a deshuffling and depacking unit 138. The deshuffling and depacking unit 138 performs processing for restoring shuffling in macroblock units performed by the packing and shuffling unit 107 on the recording side. In the deshuffling and depacking unit 138,
Disassemble the packing applied during recording. That is, the length of the data is returned in units of macroblocks, and the original variable length code is restored. Further, in the deshuffling and depacking unit 138, the system data is separated,
It is taken out to the output terminal 139.

Deshuffling and depacking unit 13
The output of No. 8 is supplied to the interpolation unit 140, and the data for which the error flag is set (that is, there is an error) is corrected. That is, if it is determined that there is an error in the macroblock data before the conversion, the DCT coefficients of the frequency components after the error location cannot be restored. Therefore, for example, the data at the error location is replaced with a block end code (EOB), and the DCT coefficients of the subsequent frequency components are set to zero. Similarly, at the time of high-speed reproduction, only DCT coefficients up to the length corresponding to the sync block length are restored, and the coefficients thereafter are replaced with zero data. Further, the interpolation unit 1
In 40, when the header added to the head of the video data is an error, the header (sequence header, GOP
Header, picture header, user data, etc.) are also recovered.

Since the DCT coefficients are arranged from the DC component and the low-frequency component to the high-frequency component over the DCT block, even if the DCT coefficients are ignored from a certain point onward, the macro block , DCT coefficients from DC and low-frequency components can be distributed evenly to each of the DCT blocks constituting.

The output of the interpolation section 140 is supplied to the stream converter 141. In the stream converter 141, the reverse process to that of the stream converter 106 on the recording side is performed. That is, the DCT coefficients arranged for each frequency component across the DCT blocks are rearranged for each DCT block. Thereby, the reproduced signal is converted into an elementary stream conforming to MPEG2.

As with the recording side, a sufficient transfer rate (bandwidth) is secured for the input and output of the stream converter 141 in accordance with the maximum length of the macroblock. When the length of the macroblock is not limited, it is preferable to secure a bandwidth three times the pixel rate.

The output of the stream converter 141 is supplied to the video decoder 142. Video decoder 142
Decodes the elementary stream and outputs video data. That is, the video decoder 142 performs an inverse quantization process and an inverse DCT process. The decoded video data is taken out to the output terminal 143. For the interface with the outside, for example, SDI is used. In addition, the elementary stream from the stream converter 141 is supplied to the SDTI transmitting unit 144. Although illustration of the path is omitted, the SDTI transmission unit 144 is also supplied with system data, reproduced audio data, and AUX, and
It is converted into a stream having a data structure of the TI format. The stream from the SDTI transmission unit 144 is output to the outside through the output terminal 145.

The audio data separated by the separation unit 135 is supplied to the deshuffling unit 151. The deshuffling unit 151 performs a process opposite to the shuffling performed by the shuffling unit 117 on the recording side. The output of the deshuffling unit 117 is supplied to the outer code decoder 152, and error correction by the outer code is performed. Outer code decoder 152
Output the error-corrected audio data. An error flag is set for data having an uncorrectable error.

The output of the outer code decoder 152 is supplied to an AUX separation section 153, where the audio AUX is separated.
The separated audio AUX is taken out to the output terminal 154. The audio data is supplied to the interpolation unit 155. The interpolating unit 155 interpolates a sample having an error. As the interpolation method, it is possible to use an average value interpolation for interpolating with the average value of correct data before and after in time, a previous value hold for holding a previous correct sample value, and the like. The output of the interpolation unit 155 is supplied to the output unit 156. The output unit 156 performs a mute process for inhibiting the output of an audio signal that is in error and cannot be interpolated, and performs a delay amount adjustment process for time alignment with a video signal. The reproduced audio signal is extracted from the output unit 156 to the output terminal 157.

Although not shown in FIGS. 1 and 2, a timing generator for generating a timing signal synchronized with input data, a system controller (microcomputer) for controlling the overall operation of the recording / reproducing apparatus, and the like are provided. Have been.

Next, a description will be given of a footprint for a magnetic tape and a format of audio data in this embodiment.

FIGS. 3 to 5 show types of audio error correction blocks which can be supported by the recording / reproducing apparatus according to this embodiment. Audio error correction blocks can be broadly classified according to differences in field (frame) frequency. The field (frame) frequency is 29.97
Hz, 59.94 Hz, 25 Hz, 50 Hz, 23.9
There are five types of 76 Hz. 29.97Hz, 25Hz,
23.976 Hz is a frequency in the case of progressive (non-interlace) scanning, and the other frequencies are interlaced scanning. FIG. 3 shows an example of a field (frame) frequency of 29.97 Hz / 59.94 Hz, and FIG. 4 shows an example of a field (frame) frequency of 25 Hz / 50 Hz. FIG. 5 shows a frame frequency of 23.976 Hz.
This is an example.

Since the frame period of the progressive scan is the same as the field period of the interlace, the frame and the field of the interlace scan will be simply referred to as a frame and a field hereinafter to avoid complexity. Are referred to as P frames.

The number of bits per audio sample is 16 depending on the difference in sound quality required in each format.
There are two types, bit and 24-bit. 3A, 4A and 5A show 16 bits / sample, and FIGS. 3B, 4B and 5B show 24 bits / sample. Note that the sampling frequency is all 48 KHz.

In the error correction block, error correction coding is performed in units of one symbol consisting of, for example, 8 bits (1 byte), and one row in the horizontal direction corresponds to a sync block. SY is a sync pattern on tape recording, and is assigned 2 bytes. The ID stores important information unique to the sync block, such as a sync number and a segment number video / audio, and is assigned 2 bytes. DID is audio 5FSe
Important information about audio data such as q (to be described later) information is stored therein, and one byte is allocated.

For example, an error correction block of 59.94 Hz, 16 bytes / sample is shown in the upper left of FIG. 1 and the number of data of one sync block is 119 bytes, the inner code parity is 12 bytes, and the outer code parity is 12 bytes. 1
It turns out that it is 0 bytes.

FIG. 6 shows the structure of a sync block. FIG. 7 shows the bit assignment of ID and DID in the sync block. In FIG. 6A, SYNC is a sync pattern on tape recording, and is 2 bytes (76 bytes).
B4h: h represents hexadecimal notation). S
Following YNC, a 2-byte ID is arranged, and a data area whose capacity is variable from 112 bytes to 189 bytes is arranged. The next 12 bytes are parity, and the inner code parity is stored.

In the data area, as shown in FIG. 6B, a 1-byte DID is arranged at the beginning, and audio data is subsequently stored. This entire data area is called the payload.

As shown on the left side of FIG. 7A, a sync ID which is an identification number of a sync block is stored in ID0. According to ID0, a different ID is assigned to each audio sync block on one track. I
D1 stores a segment number, video / audio identification bits, and the like, as shown on the right side of FIG. 7A. Azimuth number is azimuth information,

[0] or [1] is entered. Upper / Lower is the sink ID
In the additional information, the sync block on the track can be distinguished and identified by the 8 bytes of ID0, the video / audio identification bit, and the Upper / Lower. Edit IN is edit information, and this bit is recorded as [1] at the IN point at the time of editing.

FIG. 7B shows the bit assignment of the DID. NT Seq in DID is used to identify which sync block is the same field in non-tracking reproduction. For data / audio, [1] is set when data other than uncompressed audio data is stored in an audio sync block. 5FSeq
Has a frame (field) frequency of 59.94 Hz,
Information about a 5-field sequence generated in the case of 29.97 Hz is entered.

The 5-field sequence means that when the sampling frequency of audio data is 48 KHz,
Since one field is composed of five fields, which is 4004 samples / 5 fields, 800, 801, 801, 801, and 801 are assigned to each field.
Assign samples / fields, etc. This is called a 5-field sequence.

FIG. 8 shows a layout of an error correction block for one channel and one field audio when the frame (field) frequency is 29.97 Hz and 59.94 Hz. FIG. 8A schematically shows the arrangement, and FIG. 8B shows in more detail. The same applies to FIGS. 9 and 10 below. 8 per field
00 or 801 samples are divided into two error correction blocks in which even-numbered samples and odd-numbered samples are stored, respectively. In FIG. 8, AUX0, AUX1, A
UX2 is AUX data, in which auxiliary data relating to audio is stored.

Each frame corresponds to the data length of one sample, and the numbers in the frames correspond to sample numbers indicating the sample order of audio data. Further, PVx is an outer code parity described later. Numbers 0 to 800 are audio sample data. As described above, there are five field sequences, and 800 or 8
01 samples / field. In the case of 800 samples / field, the 798th sample stored in the 798th is copied to the 800th.

Each of PV0 to PV9 is an outer code parity of a vertical sequence and has 10 bytes. The outer code number is a number for collectively calling sync blocks that are horizontal data. Since one field (1P frame) has 36 sync blocks, the outer code number is 0 to 35.

FIGS. 9 and 10 show that the frame (field) frequency is 25 Hz / 50 Hz and 23.976H, respectively.
7 is a layout of an audio error correction block in the case of z. These are the same as those shown in FIG. 8 except for the difference in the sample number accompanying the change in the total number of samples.
It is the same as the case of 97 Hz / 59.94 Hz.

FIGS. 11 to 14 show examples of channel allocation on the footprint in each format. There are four types of formats referred to as SD1 to SD4, respectively. 11 is SD1, FIG. 12 is SD
2, FIG. 13 shows SD3, and FIG. 14 shows SD4. In each figure, a square represents one sector, and Ax in the square represents an audio channel number. The numbers “9” and “6” on the right side of each figure are the number of sync blocks per sector.

For example, in the case of the format SD1,
As shown in FIG. 11, there are four channels from A0 to A3, and 9 [sync block] × 2 [sector / track, channel] × 4 [track / frame] = 72
It can be seen that they are sync blocks / channels and frames. That is, it is understood that each channel is 72/2 = 36 sync blocks per field. When the formats SD2 to SD4 are similarly calculated, in one field or 1P frame, there are 36 sync blocks / channel and field per channel. This corresponds to the 36 outer code numbers per field (1P frame) in FIGS. 8 to 10 described above.

The number of tracks per field or 1P frame is different because the amount of data differs in each format due to the difference in compression ratio in video, and the required number of tracks differs accordingly. In this embodiment, audio data is treated uncompressed, and the amount of audio data per field (1P frame) is:
Always the same. Therefore, the audio is also divided into SD1 to SD4 formats according to the number of tracks required for video.

FIG. 15 shows an audio outer code number allocation in each format. FIG. 15A is an example of the format SD1, and FIG. 15B is an example of the SD4. FIG. 15C shows an arrangement common to the formats SD2 and SD3. It shows how the outer code numbers of one channel and one field are arranged with respect to the segment and the azimuth. In this figure,
The number written in the square is the outer code number. The arrows in the figure indicate the direction of head tracing. One row in the horizontal direction corresponds to one sector. For example, in SD1, 1
It can be seen that the audio data for one channel is arranged over two sectors.

As can be seen from FIGS. 15A to 15C, the 36 outer code numbers for one field are shuffled and rearranged in order. It is shown that the left side is recorded first depending on the direction of the head trace. For example, in the case of SD3 (SD2) in FIG. 15C, outer code numbers 19 and 18 are recorded at the head.

In this example, one sector of azimuth 0 and segment 0 has outer code numbers 19, 21, 0, 4, 8, 1
It consists of 2, 16, 23 and 25 9 sync blocks. This one sector is azimuth 0 and segment 0. If this is A0, this one sector is written in azimuth 0 and segment 0 of format SD3 shown in FIG. Also, the outer code numbers 28, 30, 1, 5,.
One sector 9, 13, 17, 32 and 34 is azimuth 1 and segment 1. If this is A0, this one sector is written to azimuth 1 of SD3 and A0 of segment 1 in FIG. Become.

Next, the audio encoding processing in this embodiment will be described. FIG. 16 shows an example of the configuration of the encoder 1 used in the recording / reproducing apparatus. This configuration corresponds to the configuration of the audio signal processing system from the delay unit 113 to the inner code encoder 119 in FIG. The encoder 1 supports input of audio data of four channels / 8 channels.

First, the entirety of the encoder 1 will be schematically described, and then each part of the encoder 1 will be described in detail. In FIG. 16, in the AIF-TG block 10,
Based on the supplied various signals, various timing signals and control signals required in the encoder 1 and various information are generated. The control signal generated by the AIF-TG block 10 is supplied to the AIF-MAIN block 11, and the field bank number information is supplied to the SDRAM controller 12.

For the AIF-MAIN block 11,
Four systems / 8 channels of serial audio data are supplied. AUX data, which is auxiliary data relating to audio data, is supplied to the AIF-MAIN block 11 from a system controller (not shown). This is, for example, AAUX supplied from the terminal 115. These audio data and A
The UX data is converted into an 8-bit parallel signal by serial / parallel conversion, multiplexed, and supplied to the rate converter RAMs 13A and 13B together with an address signal. In FIG. 16, the address signal is indicated by adding “A” on the signal path. Also, AI
A control signal is supplied from the F-MAIN block 11 to the AOT block 14.

RAMs 13A and 1 for rate converter
The audio data subjected to the rate conversion in 3B is supplied to the AOT block 14 in 8-bit parallel. In the AOT block 14, an outer code parity is generated in a vertical sequence for the supplied audio data, and a DID is added to a horizontal sequence. Then, the RAM 15 for sync shuffle and the R for channel shuffle
Audio data is converted to SDRAM (Synchronous DRAM) based on the shuffling table supplied from AM16.
18 to generate an address for writing. The shuffling of the audio data is performed by making this address a shuffled address. The generated addresses are stored in the SDRAM assignment RAMs 17A and 17B.
Is written while switching appropriately.

The AOT block 14 is sent from the system controller (not shown) to the sync shuffle RAM 15 and the channel shuffle RAM 16.
, A bit allocation signal 19 indicating input or output bit allocation is supplied. The bit allocation signal 19 is supplied according to the format.

Under the control of the AOT block 14, the SDR
AM assign RAM 17A and 17B to SDRAM
18 are read out, SDRAM is added together with the shuffled audio data to which the outer code parity is added.
It is supplied to the M controller 12. The audio data is stored in the SDRAM controller 1 with a bit width of 32 bits.
2 is supplied. In the SDRAM controller 12, A
While switching the banks of the SDRAM 18 based on the bank number supplied from the IF-TG block 10, the audio data is transferred with a bit width of 32 bits based on the address supplied from the AOT block 14.
Write to.

The SDRAM controller 12 has:
The video data output from the shuffling circuit 110 is also supplied. Video data is written to a predetermined address of the SDRAM 18. In this way SDR
An inner code parity (not shown) built in the SDRAM controller 12 adds an inner code parity to the audio and video data written in the AM 12 in a horizontal sequence, that is, in sync block units. Then, the audio and video data to which the inner code parity has been added are read from the SDRAM 18 in sync block units in an order corresponding to the footprint, and output from the encoder 1.

Next, each part of the encoder 1 will be described in more detail. The AIF-TG block 10 includes a TG-frame which is a frame signal, a TG-AVSTO which is a field signal, a TG-5F-ID which is a reference 5 field sequence ID, a PB-5F-ID which is a playback 5 field sequence ID, Further, it receives FS, which is a sample separation signal, and generates necessary timing, control, and various information inside the encoder 1 based on these signals.

The AIF-MAIN block 11 performs a serial / parallel conversion on the supplied 4-sequence / 8-channel audio data. Audio data is
AES / EBU (Audio Engineering Society / European
Broadcasting Union)
C, for example, channels 1 and 2, channels 3 and 4, channels 5 and 6, channel 7
And 8 are paired, and two channels for one system are transmitted as time-division serial data every time the signal FS is inverted. In FIG. 17C, V, U,
C, P, Z, M, J and E are control and parity bits.

The audio data can be transmitted with a bit width of 24 bits per sample based on the standard. When transmitting data of 16 bits per sample, the data is transmitted after the signal FS. Audio data having a bit width of 16 bits and 24 bits each day is referred to as 16-bit audio data and 24-bit audio data, respectively.

The AIF-MAIN block 11 converts serial data into 8-bit parallel data so that audio data can be easily handled inside the encoder 1. The 24-bit audio data is, as shown in FIG. 17B, data of upper, middle and lower 8 bits each (audio 2, 1 and 0), and the 16-bit audio data is as shown in FIG. 17A. Top 8
Bit and lower 8 bit data (audio 2
And 1).

In the block 11, the AUX data supplied from, for example, a system controller (not shown) is added to the audio data, and the write control of the rate converter RAMs 13A and 13B is also performed.

RAMs 13A and 1 for rate converter
3B changes the frequency of the audio data clock from the audio frequency to a high-speed system clock, and also serves as a buffer in processing. FIG.
4 is a map showing an example of an address assignment of the rate converter RAMs 13A and 13B. Shown here is a map for one channel.
Indicates a byte. The outer code numbers shown in FIG.
This corresponds to the outer code number shown in FIGS. The audio data that does not include the outer code parity has outer code numbers 0 to 15, and the outer code numbers 0 to 15 in FIG.
Matches.

The AUX data is added to the audio data by the AIF-MAIN block 10 and written into the rate converter RAM 13A and / or 13B. Data for channels 0 to 3 are written in the rate converter RAM 13A, and are written in the RAM 13B.
Data of channels 4 to 7 is written. The rate converter RAMs 13A and 13B can be controlled independently of each other. Hereinafter, channels 0 to 3 will be described unless otherwise specified, and channels 4 to 3 will be described.
The description about 7 is omitted.

In the case of 16-bit audio data, 2 bytes / sample are written in the rate converter RAM 13A in the horizontal direction in FIG. For example, every two bytes of audio 2 and audio 1 shown in FIG. 17A are written as the write unit (16 bits) shown in FIG. On the other hand, the 24-bit audio data is written as a write unit (24 bits) for each three bytes of audio 2, 1 and 0 shown in FIG. 17B.

The capacity of the rate converter RAM 13A (and 13B) is set to a capacity required as a buffer in the circuit. Therefore, writing is performed by AIF
Based on the control of the MAIN block 11, in the outer code number, when the byte number 17 is obtained, the byte number 0 is written in a cyclic manner so that the byte number 0 follows.
For example, writing is controlled like a FIFO.

In this manner, the RA for the rate converter
When 8 bytes have been stored in the M13A with the byte number of FIG. 18, a control signal is sent from the AIF-MAIN block 11 to the AOT block 14. Based on this control signal, the AOT block 14 reads data from the rate converter RAM 13A. The reading is performed in the vertical direction in the map of FIG. At this time, eight byte numbers are read out at once in the vertical direction. That is, two read units shown in FIG. 18 are read.

At this time, the rate converter RAM 13
First, only data having an even outer code number, such as outer code numbers 0, 2, 4, 6,... Then, an outer code parity is generated and added to the read data.

The rate converter RAM 13A
(And 13B), by reading data with the system clock, it is possible to perform rate conversion with respect to the rate of input data. For example, if the sampling frequency of the input data is, for example, 48 kHz, the frequency is 12
By reading with a clock of MHz, the rate is approximately 256 times. Subsequent processing is performed based on this clock frequency.

The data to which the outer code parity is added is S
The data is written to the DRAM assignment RAM 17A. Note that the SDRAM assignment RAMs 17A and 17B
Are two banks of the same RAM, for example, RAM
17A is bank 0, and RAM 17B is bank 1.

After the writing to the SDRAM assignment RAM 17A is completed, the outer code numbers 1, 3, 5,
Data of odd outer code numbers such as 7,..., 15 are read. Then, the read data is subjected to generation and addition of an outer code parity, and
The data is written to the RAM assignment RAM 17B (bank 1).

FIG. 19 shows a RAM 1 for SDRAM assignment.
7 shows an example of an address assignment map of 7A and 17B. Here, the half outer code number is a value obtained by INT [outer code number / 2]. These SDRAM assignment RAMs 17A and 17B have a data width of 32.
Bit width. Therefore, at the time of writing, writing is performed byte by byte using a write enable signal of 8 bits for each byte.

When all the bytes in the SDRAM assignment RAM 17A (bank 0) have been written, the data is read in the horizontal direction in FIG. That is, RAM for SDRAM assignment
17A and 17B have a smaller capacity than the entire data capacity of one error correction block. When the reading process of the bank 0 (RAM 17A) is completed, the reading process of the bank 1 (RAM 17B) is similarly performed. Bank 0 and bank 1 are subjected to bank alternate processing such that when one of the banks is being read, the other is being written.

When data is read from the SDRAM assignment RAM 17A, the data is read from the outer code number corresponding to the data to be read into the SDRAM 18 using the shuffling table stored in the sync shuffle RAM 15 and the channel shuffle RAM 16. The address is determined by the AOT block 14.
The obtained SDRAM address is stored in the SDRAM controller 12 together with the data read from the RAM 17A.
Supplied to

Then, according to the address supplied by the SDRAM controller 12, data is transferred to the SDRAM.
18 is written. The same processing is performed in the SDRAM assignment RAM 17B.

The SDRAM controller 12 is also supplied with the video data shuffled by the shuffling circuit 110. The supplied video data is SD
The data is written to a predetermined address in the RAM 18.

The SDRAM controller 12 controls S
Audio and video data are read from the DRAM 18. Then, an inner code parity (not shown) is generated and added to the read data by an inner code encoder (not shown) and output. Note that the SDRAM controller 12 is supplied with the above-described field bank number information, and is also supplied with the system controller-set field delay information from the system controller. SDRA
In the M controller 12, based on these information, the SD
The data is read from the SDRAM 18 according to the footprint, while appropriately switching the bank of the RAM 18 and adding a predetermined amount of delay.

FIG. 20 is a schematic timing chart in the case of 3 bytes / sample (24-bit audio data) by the processing of the encoder 1 described above. FIG. 20A shows fields of video data accompanying audio data. In this embodiment, audio data is handled uncompressed and is input continuously. Therefore, data is always input without interruption between fields. This is subjected to serial / parallel conversion by the AIF-MAIN block 11 and the rate conversion RAM 1
3A (FIG. 20B). What is written as 16sp means 16 samples, and FIG.
That is, one vertical column of eight write units (24 bits) is filled.

When two read units shown in FIG. 18 are accumulated, reading from the RAM 13A is started in the vertical direction (FIG. 20C). AO for the read data
An outer code parity is added in the T block 14 and SD
The data is written into the RAM 17A (or 17B) for RAM assignment in the vertical direction in FIG. 19 (FIG. 20D).
The written data is read out in the horizontal direction, as shown in FIG. 20E, and written to the SDRAM 18 by the SDRAM controller 12.

This will be described in more detail with reference to FIGS. 20F to 20H. First, of the rate conversion RAM 13A,
For example, data of even number of the outer code of channel 0 is read out vertically by 8 bytes (one line) (FIG. 20F). An outer code parity is added to the read data, and a total of 18 bytes of the data and the outer code parity are written in the SDRAM assignment RAM 17A in the vertical direction (FIG. 20).
G). When this is done eight times, the RAM for SDRAM assignment
Data is full at 17A.

Then, data is read from the RAM 17A in the horizontal direction, and the read data is stored in the sync shuffling RAM 15 and the channel shuffling RAM.
Shuffling is performed based on the 16 shuffling tables, and an address for the SDRAM 18 is generated. This address is stored in the SDRAM together with the read data.
It is supplied to the controller 12 and written to the SDRAM 18. In this way, the processing for the data of channel 0 with the outer code number even is completed.

The SDRAM 18 has a bit width of 32.
By setting one bit and specifying one address, a burst write in which a plurality of data are continuously written can be performed.

On the other hand, the processing for the data of channel 0 having an odd outer code number is performed in the SDRAM assign RAM 1.
While data is being read in 7A, 8 bytes (one) of data having an odd outer code number of channel 0 in the rate conversion RAM 13A are read in the vertical direction,
Add outer code parity to read data,
A total of 18 bytes of data and outer code parity
The data is written in the AM assignment RAM 17B in the vertical direction. Then, the same processing as in the above-described bank 0 is performed, and
The processing of the data having the odd outer code number is ended.

Thus, the processing of the data of channel 0 is performed. Similarly, the processing of channels 1 to 7 is performed. In this process, the rate conversion RAM 1
Eight vertical series of 3A and 13B (lead unit 2
That is, the processing of channels 0 to 7 has been completed.
The above-described processing is performed and data is written to the SDRAM 18 each time data for eight vertical lines is accumulated in the rate conversion RAMs 13A and 13B.

In each format, the number of audio samples per field is not always a multiple of 16 (see FIG. 20A and FIG. 20B), so the last of the field is vertical to the rate conversion RAMs 13A and 13B. 8 lines do not accumulate. Therefore, as shown in FIG. 20B, FIG. 20C, FIG. 20D, etc., the RAM read / write processing at the end of a field is performed immediately before processing of a new field is started.

FIG. 21 is a schematic timing chart in the case of 2 bytes / sample (16-bit audio data). RAMs 13A and 1 for rate conversion
The same processing as in the case of 3 bytes / sample in FIG. 20 described above is performed except that the accumulation of eight 3B vertical series is slow because it is 2 bytes / sample.

FIG. 22 shows that the field frequency is 59.94.
Hz, 50 Hz and 23.976 Hz formats, the number of bytes of audio data of one sync block, the number of bytes after DID addition, and DID
Indicates the number of units for performing the outer code encoding process on the data to which is added. FIG. 22A is for 24-bit audio data and corresponds to the processing in FIG. FIG.
B is for 16-bit audio data and corresponds to the processing in FIG.

Next, the RAM 15 for the sync shuffle and the RAM 16 for the channel shuffle, which are the parts related to the gist of the present invention, will be described. AOT block 1
4, the SDRAM assignment RAMs 17A and 1
When reading from 7B, it is necessary to find an address for writing to SDRAM 18 based on the outer code number and the channel number.

This is shown in FIG. 1 in the tape format.
As described with reference to FIGS. 1 to 15, the data is rearranged in the original order and shuffled.
This is because, when writing to the DRAM 18, it is easier to perform the subsequent processing by arranging the addresses in the final RF output order, that is, the addresses in the tape head trace order (footprint order).

FIG. 23 is a schematic diagram of the sync shuffle RAM 15.
The process will be described more specifically. Reading of the SDRAM assignment RAMs 17A and 17B is controlled by the AOT block 14. Therefore, AO
In the T block 14, the RAM 17 for SDRAM assignment is used.
The outer code numbers of the data read from A and 17B are known. The outer code number of the data read from the SDRAM assignment RAMs 17A and 17B is given to the sink shuffle RAM 15 as an address. The sync shuffle RAM 15 returns the sector number in the channel field, the sync number in the sector, and the azimuth number as return values. That is, the outer code number is converted into the sector number in the channel field, the sync number in the sector, and the azimuth number.

As described above, the audio sector is divided into the same channel and the same field according to the format in the same field. The sector number in the channel field is a number indicating the number of the outer code number of interest in the head trace order. Referring to the example of the format SD4 shown in FIG. 14, as a counting method, azimuths 0 and 1 are counted as 1 in a segment unit. The intra-sector sync number is a number indicating the order of the sync block on the head trace of the outer code number of interest in the same sector. The azimuth number is a number indicating which azimuth the outer code number of interest is on the head trace.

The bit assignment width of the sector number in the channel field, the sync number in the sector, and the azimuth number differs depending on the format (FIG. 24A). Specifically, for example, as shown in FIGS. 25A and 25B,
In the formats SD1 and SD4, the bit widths of the sector number in the channel field and the sync number in the sector are different.

That is, in the format SD1, one field is recorded using two tracks, and the sector number in the channel field is 0 or 1, which is represented by one bit. In SD4, one field is recorded by six tracks. , The sector number in the channel field takes 0, 1, or 2, and 2 bits are required. On the other hand, regarding the intra-sector sync number, in SD1 in which 9 sync blocks are arranged in one sector, 4 bits are required to represent 0 to 8, whereas in SD4, 6 sync blocks are arranged in one sector. Only 3 bits are required.

In this embodiment, the output bit width is always the same as 6 bits in total of the sector number in the channel field, the sync number in the sector, and the azimuth number (FIG. 24B). The bit width of the sync shuffle RAM 15 is saved. This bit allocation is indicated by a bit allocation signal 19 supplied from a system controller (not shown).

The lower side of FIGS. 25A and 25B
An example of conversion of an outer code number to a sector number in a channel field, a sync number in a sector, and an azimuth number is shown.

FIG. 26 shows a channel shuffling RAM.
The 16 processes will be described more specifically. For example, SD1
In the case of SD3 and SD3, as can be seen from FIGS. 11 and 13, a frame is provided, one frame is composed of two fields, and the frame is also one unit on the footprint. At this time, it is the field number that distinguishes between the first half field and the second half field. For example, the first half field has field number = 0, and the second half field has field number = 1.

Field number and R for sync shuffle
The sector number in the channel field and the channel number read from the AM 15 are given to the channel shuffling RAM 16 as addresses. The channel shuffle RAM 15 outputs a track sector number as a return value. That is, the field number, the sector number in the channel field, and the channel number are converted into the sector number in the track by the channel shuffling RAM 16. The sector number in the track is a field number, a sector number in a channel field, and a number indicating the number of the sector on the head trace in the same track.

FIG. 27 shows a channel shuffling RAM.
16 shows an example of an address assignment to No. 16. brackets[]
Is the required bit width indicated by the bit position.
[0] indicates that it can be represented by 1 bit,
[2: 0] indicates that three bits 0 to 2 are required. As shown in FIG. 27A, the field number, the sector number in the channel field, and the channel number have different bit widths depending on the format. In this embodiment, as shown in FIG. The number of addresses required to support the format is reduced. That is, in this example, 7 bits are allocated to all formats. Such bit allocation is indicated by a bit allocation signal 19 supplied from a system controller (not shown).

FIGS. 28 to 30 show formats SD3,
Examples of audio sector channel allocation in SD2 and SD1 are shown below. The lower part of FIGS. 28 to 30 shows an example of the correspondence between the field number, the sector number in the channel field, the channel number, and the sector number in the track in each format.

In the present invention, the sink shuffle RAM is used.
The above-described conversion in the RAM 15 and the channel shuffling RAM 16 is performed by referring to tables stored in the RAMs 15 and 16. For example, in the sync shuffling RAM 15, for the address specified based on the outer code number, the corresponding sector number in the channel field, the sync number in the sector, and the azimuth number are stored. The table values stored in the sync shuffle RAM 15 and the channel shuffle 16 are appropriately loaded from a system controller (not shown). That is, RA
The values in M15 and RAM 16 can correspond to each format by loading an appropriate shuffle value from the system controller according to the format.

FIGS. 31 to 34 show SD1 to SD, respectively.
4 shows an example of a track number in the format No. 4. The track number is assigned to distinguish tracks one by one in the same field. In the head trace order, the azimuth number 0 is 2N (even number), and the azimuth number 1 is 2N +
The number is 1 (odd number). FIGS. 31 to 34 are the same as the channel allocations of FIGS. 11 to 14 already described. In FIGS. 31 to 34,
The sector number and the track number in the channel field are added.

The track number can be obtained from the sector number in the channel field and the azimuth number.
Here, in this embodiment, the calculation method for obtaining the track number differs depending on each format. 31 to 34
Below, the calculation method of the track number in each format is shown.

For example, the format SD1 shown in FIG.
In, the azimuth number is the track number as it is. In the format SD4 shown in FIG. 34, the track number is obtained by setting the upper two bits of the sector number in the channel field and the lower azimuth number. As described above, the method of calculating the track number differs depending on each format. The track number is calculated by the AOT block 14 based on each calculation method.

FIG. 35 shows an example of an address assignment of audio data in the SDRAM 18 (hereinafter referred to as an SDRAM address assignment). In the SDRAM 18, the audio data is written in a manner delimited by fields. The area of the SDRAM 18 storing one field is called a field bank. In this embodiment, the SDRAM 18 has 16 field banks, and can store audio data for 16 fields. As shown in FIG. 35, the SDRAM address assignment includes a field bank, a track number, a sector number in a track, a sync number in a sector, and a byte number in a sync.

The field bank is supplied from the AIF-TG block 10 and indicates which of the 16 field banks of the SDRAM 18 is to be written. The track number is assigned to each track, and the intra-track sector number is a value from 0 to 7. The intra-sector sync number indicates the order of the 9 or 6 sync blocks constituting one sector.

The in-sync byte number is a number in byte units in the sync block. The byte number in the sink is
As shown in FIG. 36A, the DID at the head of the payload is numbered 0, and 1, 2 for each byte.
, N. In this embodiment, the SDR
AM18 is 32 bits wide. As shown in FIG. 36B, the data is LS-based with respect to a 32-bit (4 byte) width in byte units in the sync block in byte units.
Ordered from B to MSB. Therefore, SDRAM
On the address assignment, the lower 2 bits of the byte number in the sink are not used. In other words, the upper 6
Bits [7: 2] are assigned addresses.

As described above, the sync shuffle RAM 1
5 and the RAM 16 for channel shuffling,
The track number is obtained in the T block 14, and an address corresponding to the SDRAM address assignment shown in FIGS. 35 and 36 is calculated. Then, from AOT block 14 to SD
The address and data are sent to the RAM controller 12. The SDRAM controller 12 writes data to the SDRAM 18 based on the transmitted address.

Incidentally, the SDRAM 18 address assignment is arranged in a tape format. SDR
When reading data from the AM 18, the SDRAM controller 12 calculates a field bank that is behind the writing by a field delay set by a system controller (not shown). This is a read bank.

The SDR in the read bank
From the lower order of the AM address assignment, the byte number in the sync is incremented from 0, the sync number in the sector is incremented from 0, the sector number in the track is incremented from 0, and the track number is incremented from 0. This allows for easy head trace order,
Data can be read from the SDRAM 18 in the order of footprint.

The SDRAM controller 12 adds the inner code parity to the data read out from the SDRAM 18 in this manner, and outputs the data from the encoder.

In the present invention, audio data shuffling is divided into three components, namely, a sync shuffling RAM, a channel shuffling RAM, and a track number conversion circuit (that is, an AOT block). Thus, audio data can be shuffled with a smaller configuration.

This will be described more specifically. For example, consider a case where shuffling of audio data is performed using a RAM having a single shuffling pattern. In this case, the address is 8 channels × 3
6 outer codes × 2 fields = 576 words, the RAM bit width requires a track number of 3 bits, a track sector number of 3 bits, and a sector sync number of 4 bits, for a total of 10 bits. Therefore, a RAM of 576 words × 10 bits = 5760 bits is required.

On the other hand, in the present invention, the sync shuffle RAM 15 requires 36 words × 6 bits = 216 bits, and the channel shuffle RAM 16 requires 32 words × 3 bits = 96 bits. Thus, in total, only 312 bits are required.

When the configuration for performing shuffling is incorporated into an audio encoder IC as in this embodiment, the embedded configuration for embedding in the IC is used.
RAM requires a large chip area. In other words, if a large-capacity RAM is used for shuffling, the cost increases, and the necessary RAM is used.
Reducing the number of bits leads to a significant reduction in the chip unit price.

In the recording / reproducing apparatus according to the above-described embodiment, a magnetic tape is used as a recording medium. However, the present invention is not limited to this example. As a recording medium, for example, a hard disk or a magneto-optical disk,
A disk-shaped recording medium can be used. Further, the present invention can be applied to other recording media that performs shuffling on audio data in packet units.

Furthermore, in the above description, the present invention is applied to a digital video tape recorder. However, the present invention can be applied to an apparatus that handles only digital audio data.

[0137]

As described above, according to the present invention, a shuffling pattern of audio data is stored in a RAM for sync shuffle and a RAM for channel shuffle.
And by referring to the tables stored respectively. Therefore, by rewriting the shuffling pattern table stored in the RAM by, for example, an external system controller, there is an effect that it is possible to easily cope with a plurality of audio formats having different shuffling patterns.

Therefore, for example, there is an effect that a plurality of audio formats can be flexibly handled with only one audio encoding IC.

Further, according to the present invention, the shuffling of audio data is supported by being divided into three configurations of a RAM for sync shuffle, a RAM for channel shuffle, and a track number conversion circuit (that is, an AOT block). Therefore, audio data can be shuffled with a small configuration.

Further, according to this embodiment, the RAM for sync shuffle has the effect that the required bit width can be reduced because the RAM bit assignment is changed depending on the format.

Specifically, unless the bit assignment of the RAM for sync shuffle is changed, a total of 7 bits are required, ie, 2 bits for the sector number in the channel field, 4 bits for the sync number in the sector, and 1 bit for the azimuth number.
When the RAM bit assignment is changed depending on the format, only 6 bits are required and 1 bit can be reduced. In this embodiment, since the 36 words RAM is used as the RAM for sync shuffle, the number of bits to be reduced is:
36 words × 1 bit = 36 bits.

Similarly, in this embodiment, the RAM for channel shuffling changes the RAM address assignment depending on the format, so that the number of required addresses can be reduced.

Specifically, the channel shuffle RA
Unless the address assignment of M is changed, an address assignment of 6 bits, that is, 64 words ( ²⁶ words) in the field number, the sector number in the channel field, and the channel number is required. RAM by format
If the address assignment is changed, 5 bits = 32 words ( ²⁵ words) are required, and 32 words can be reduced. Since the RAM is 3 bits wide, 32 words × 3 bits = 96 bits can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration on a recording side according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a reproducing side according to an embodiment of the present invention.

FIG. 3 is a schematic diagram illustrating types of audio error correction blocks that can be supported by the recording / reproducing apparatus according to the embodiment;

FIG. 4 is a schematic diagram illustrating types of audio error correction blocks that can be supported by the recording and reproducing apparatus according to the embodiment;

FIG. 5 is a schematic diagram showing types of audio error correction blocks that can be supported by the recording and reproducing apparatus according to the embodiment;

FIG. 6 is a schematic diagram illustrating a structure of a sync block.

FIG. 7 is a schematic diagram showing bit assignment of ID and DID in a sync block.

FIG. 8 shows a frame (field) frequency of 29.97H.
FIG. 9 is a schematic diagram illustrating a layout of an error correction block for one channel and one field audio in the case of z, 59.94 Hz.

FIG. 9 shows a frame (field) frequency of 25 Hz / 5.
FIG. 4 is a schematic diagram illustrating a layout of an audio error correction block in the case of 0 Hz.

FIG. 10 is a schematic diagram showing a layout of an audio error correction block when the frame frequency is 23.976 Hz.

FIG. 11 is a schematic diagram illustrating an example of channel allocation on a footprint in a format SD1.

FIG. 12 is a schematic diagram illustrating an example of channel allocation on a footprint in a format SD2.

FIG. 13 is a schematic diagram illustrating an example of channel allocation on a footprint in a format SD3.

FIG. 14 is a schematic diagram illustrating an example of channel allocation on a footprint in a format SD4.

FIG. 15 is a schematic diagram illustrating audio code number allocation in each format.

FIG. 16 is a block diagram illustrating an example of a configuration of an encoder used in the recording / reproducing apparatus.

FIG. 17 is a schematic diagram illustrating input audio data.

FIG. 18 is a map showing an example of an address assignment of a rate converter RAM.

FIG. 19 is a map showing an example of an address assignment of an SDRAM assignment RAM;

FIG. 20 is a schematic timing chart of processing of 3 bytes / sample by the encoder.

FIG. 21 is a schematic timing chart of processing of 2 bytes / sample by an encoder.

FIG. 22 is a schematic diagram showing the number of bytes of audio data of one sync block, the number of bytes after DID addition, and the number of units for performing outer code encoding processing on data to which DID is added, in each format. It is.

FIG. 23 is a schematic diagram for explaining processing of a RAM for sync shuffle.

FIG. 24 is a diagram for explaining that the bit assignment width of the sector number within the channel field, the sync number within the sector, and the azimuth number differs depending on the format.

FIG. 25 is a diagram for explaining that the bit assignment width of the sector number in the channel field, the sync number in the sector, and the azimuth number differs depending on the format.

FIG. 26 is a schematic diagram for describing processing of a channel shuffling RAM.

FIG. 27 is a schematic diagram illustrating an example of address assignment to a channel shuffling RAM.

FIG. 28 is a schematic diagram illustrating an example of channel allocation of an audio sector in a format SD3.

FIG. 29 is a schematic diagram illustrating an example of channel allocation of an audio sector in a format SD2.

FIG. 30 is a schematic diagram illustrating an example of channel allocation of an audio sector in a format SD1.

FIG. 31 is a schematic diagram illustrating an example of a track number in the format of SD1.

FIG. 32 is a schematic diagram illustrating an example of a track number in the format of SD2.

FIG. 33 is a schematic diagram illustrating an example of a track number in the SD3 format.

FIG. 34 is a schematic diagram showing an example of a track number in the format of SD4.

FIG. 35 is a schematic diagram illustrating an example of an address assignment of audio data of an SDRAM.

FIG. 36 is a schematic diagram for explaining byte numbers in a sink;

FIG. 37 is a schematic diagram schematically showing an example of the arrangement of each sector on a track.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Encoder, 11 ... AIF-MAIN block, 12 ... SDRAM controller, 13A, 1
3B: RAM for rate conversion, 14: AO
T block, 15: RAM for sync shuffle, 1
6 ... RAM for channel shuffle, 17A, 17
B: RAM for SDRAM assignment, 18: SD
RAM, 114: AUX addition circuit, 116: outer code encoder, 117: shuffling, 118
..ID addition circuit, 119 ... inner encoder, 1
20: synchronous addition circuit, 123: magnetic tape, 1
32: SYNC detection circuit, 133: inner code decoder, 134: ID interpolation circuit, 151: deshuffling circuit, 152: outer code decoder, 153
..AUX separation circuit, 155... Interpolation circuit, 156
..Output section

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C053 FA20 FA21 FA22 FA30 GB11 GB15 GB18 GB38 JA07 JA21 JA24 JA26 JA30 KA01 KA08 KA24 KA30 5D044 AB05 BC01 CC01 DE03 DE14 DE38 DE54 DE68 DE81 DE83 EF03 FG10 GK10

Claims (13)

[Claims] 1. A data processing apparatus in which digital audio data of a plurality of channels is stored for each packet of a predetermined length, and wherein the digital audio data is rearranged in a packet unit in an order different from an original order, wherein a shuffling table is stored. Then, position information indicating a position in a packet unit in the input data sequence is supplied as an address, and according to the shuffling table, shuffle table memory means for outputting converted position information obtained by converting the position information, Means for storing the shuffling table selected from the shuffling tables in the shuffling table memory means. 2. The data processing device according to claim 1, further comprising data storage memory means for storing the input data, wherein the conversion position information is write address information for the data storage memory means. Characteristic data processing device. 3. The data processing apparatus according to claim 1, wherein said shuffling table memory means performs said conversion of said position information on a packet-by-packet basis. 4. The data processing apparatus according to claim 3, wherein the conversion position information is output in parallel as a plurality of data having different bit widths depending on the format, and the total bit width output in parallel is A data processing device characterized in that the different formats are made equal to each other. 5. The data processing device according to claim 1, wherein the shuffling table memory means performs the conversion of the position information on a channel basis. 6. The data processing device according to claim 5, wherein the address as the position information is input in parallel as a plurality of data having bit widths different from each other depending on a format, and a total of the total input in parallel is input. A data processing device characterized in that the bit widths of the formats are different from each other. 7. A data processing apparatus for storing digital audio data of a plurality of channels for each packet of a predetermined length and rearranging the digital audio data in an order different from the original order in the unit of the packet. A first shuffling unit that rearranges the input data sequence composed of a plurality of channels input in the above-mentioned packet unit, and further rearranges the data rearranged by the first shuffling unit in the above-mentioned channel unit. A data processing apparatus comprising: a second shuffling unit; and a third shuffling unit for rearranging the data rearranged by the second shuffling unit in units of a plurality of channels. apparatus. 8. Digital audio data of a plurality of channels is stored for each packet of a predetermined length, and the digital audio data is rearranged in a unit of a packet different from the original order, and in a unit of a track composed of the plurality of channels. In a data recording apparatus for recording on a recording medium, data storage memory means for storing input data and a shuffling table are stored, and position information indicating a position of a packet unit in an input data sequence is supplied as an address, and the shuffling is performed. The shuffling table memory means for outputting a write or read address of the data storage memory by converting the position information according to the table, and the shuffling table selected from the plurality of shuffling tables different from each other. Sha A shuffling table storage means for storing in a fling table memory means, an error correction encoder for encoding an error correction code for at least one of input data and output data of the data storage memory, and an error correction encoder. Recording means for recording error-correction-coded data on a recording medium. 9. The apparatus according to claim 1, wherein the shuffling table is selected in response to a format of digital audio data. 10. The data recording apparatus according to claim 8, wherein the error correction code is a product code that double codes each data symbol by an outer code and an inner code. 11. A data processing method in which digital audio data of a plurality of channels is stored for each packet of a predetermined length and the digital audio data is rearranged in an order different from the original order in units of the packet. A step of outputting position information stored in a ring table memory and indicating a position in a packet unit in an input data sequence as an address, and outputting converted position information obtained by converting the position information according to the shuffling table; Storing the selected shuffling table from the shuffling tables in the shuffling table memory. 12. A data processing method for storing digital audio data of a plurality of channels for each packet of a predetermined length and rearranging the digital audio data in an order different from the original order in the packet unit. A first shuffling step of rearranging an input data sequence composed of a plurality of channels input in the above-mentioned packet unit; and a data rearranged in the above-mentioned first shuffling step. 2nd to sort
And a third shuffling step of rearranging the data rearranged in the second shuffling step in units of a plurality of channels. Processing method. 13. A digital audio data of a plurality of channels is stored for each packet of a predetermined length, and said digital audio data is rearranged in an order different from an original order in a unit of said packet, and in a track unit composed of said plurality of channels. In a data recording method for recording on a recording medium, a step of storing input data in a data storage memory; and a step of storing a shuffling table in the shuffling table memory, wherein position information indicating a position of a packet unit in the input data sequence is used as an address. Outputting the write or read address of the data storage memory by converting the position information supplied in accordance with the shuffling table; and selecting the shuffling table selected from the plurality of different shuffling tables. Storing a table in the shuffling table memory, and performing an error correction code on at least one of input data and output data of the data storage memory. And a recording step of recording, on a recording medium, data that has been error-correction-encoded by the error-correction-encoding step.