JP2000173188A - Audio signal processor and video/audio recording/ reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To share a processing circuit after error correction with plural channels when the audio data of plural channels are processed. SOLUTION: The audio data of plural channels are time division multiplexed to be supplied from an RC 19 to an AIF 20. The data and error flags are stored in a register group 203 at every channel. An audio processing part 220 performs prescribed processing for the supplied audio data by using the data of the corresponding channel of the register group 203 at need. The output of the processing part 220 is stored in the corresponding register of the register group 209 at every channel of a pair each other, and the time division multiplex is separated. The outputs of respective registers of the register group 209 are latched respectively on the corresponding registers of a P/S register group 210, and the data of respective output systems are outputted parallel in the timing corresponding to a sampling period. The processing part 220 is used commonly with plural channels.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an audio signal processing device and a video / audio recording / reproducing device which process multi-channel audio data.

[0002]

2. Description of the Related Art At present, an analog audio signal is A / D-converted.
Convert and process as digital audio data,
Digital audio equipment has become widespread. One example of such digital audio equipment is a digital video tape recorder (hereinafter abbreviated as DVTR) that records and reproduces digital video data and audio data on a recording medium.

In the DVTR, digital video data and audio data are subjected to error correction encoding using, for example, a product code, and an ID and a synchronization pattern are added for each predetermined unit (sync block).
It is recorded on a recording medium such as a magnetic tape.

At the time of reproduction, a sync block is cut out from data reproduced from a recording medium based on a synchronization pattern, aligned based on the ID in the sync block, and decoded with an error correction code. At this time, if an error exists in the data beyond the error correction capability of the error correction code, the data is not corrected and an error flag indicating the presence of the error is added to the data. After such error correction processing, data that has not been subjected to error correction is error-corrected by a predetermined method and output.

[0005] After error correction, in addition to the above-described error correction, processes such as a mute process, a shuttle filter, and a ramp-up process are performed as necessary. The mute process is a process of setting the output to a silent state, and is performed, for example, when an error state continues for a long time or when data other than audio data is reproduced. The shuttle filter is
During shuttle playback in which the tape is played at a higher speed than during recording, the data to be played back is interpolated by filter processing. The ramp-up is a process of gradually raising the level of the reproduced audio signal when the above-mentioned mute processing is canceled, and suppressing pulse-like noise generated due to a steep waveform of the audio signal. .

On the other hand, in recent years, for example, a surround sound system, which is an audio reproduction system that forms a sound field spatially and enhances a sense of reality, has become widespread, and there is a demand for multi-channel audio equipment. In addition, a larger number of channels is required to support multilingual languages. Even in the above-mentioned DVTR, most are, for example, 4 or 8
It supports multiple channels such as channels.

[0007] Particularly, in the case of professional equipment such as for a broadcasting station, an output for confirmation is provided in addition to a normal reproduction output for editing. In this case, the number of output channels is It is even more doubled.

[0008]

Conventionally, a circuit for performing each processing after the above-described error correction processing is provided exclusively for each of a plurality of output channels. Therefore, there is a problem that the same circuit is required for the number of channels and the circuit scale becomes large.

Accordingly, an object of the present invention is to provide an audio signal processing apparatus and a video / audio recording / reproducing apparatus which can share a processing circuit after error correction with a plurality of channels.

[0010]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides an audio signal processor adapted to handle a plurality of channels of digital audio data by time-division multiplexing a plurality of channels of audio data. Time-division multiplexing means for inputting and receiving audio data multiplexed by the time-division multiplexing means, and performing predetermined processing on the input audio data for each channel; An audio signal processing apparatus comprising: a data holding unit that holds data necessary for the above processing for each channel; and an output unit that outputs audio data processed for each channel by the signal processing unit.

Further, the present invention is directed to a video image in which digital video data and digital audio data of a plurality of channels are both recorded on a recording medium, and the digital video data and the digital audio data of the plural channels are reproduced from the recording medium. In an audio recording / reproducing apparatus, recording means for performing error correction encoding using a product code on input video data and audio data of a plurality of channels, adding ID information and a synchronization signal, and recording on a recording medium. And reproducing the video data and the audio data of the plurality of channels recorded on the recording medium, and performing an error correction code by a product code on the reproduced video data and the audio data of the plurality of channels based on the synchronization signal and the ID information, respectively. Do decryption Means, time-division multiplexing means for transmitting time-division multiplexed audio data of a plurality of channels reproduced by the reproduction means, and audio data multiplexed by the time-division multiplexing means. Signal processing means for performing predetermined processing for each channel, data holding means for holding data required for predetermined processing by the signal processing means for each channel, and outputting audio data processed for each channel by the signal processing means. And a video / audio recording / reproducing apparatus.

As described above, according to the present invention, a plurality of channels of audio data are time-division multiplexed and transmitted,
The audio data is subjected to predetermined processing by the signal processing means for each channel, data necessary for processing by the signal processing means is held for each channel, and audio data processed for each channel is output. Therefore, the signal processing means can be commonly used for a plurality of channels.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to a digital VT.
An embodiment applied to R will be described. This embodiment is suitable for use in a broadcast station environment,
Recording and recording of video signals of multiple different formats
It enables playback. For example, a signal (480i signal) having 480 effective lines in the interlaced scanning based on the NTSC system and a signal (576 signals) having 576 effective lines in the interlaced scanning based on the PAL system.
i) are recorded with almost no hardware changes.
It is possible to reproduce. Furthermore, a signal having 1080 lines (1080i signal) in interlaced scanning,
In progressive scanning (non-interlace), the number of lines is 480, 720, and 1080, respectively.
Recording / reproduction such as 0p signal, 720p signal, and 1080p signal) can also be performed.

In this embodiment, a video signal is compression-encoded based on the MPEG2 system, and an audio signal is handled uncompressed. As is well known, MPEG
No. 2 is a combination of motion compensation predictive coding and compression coding by DCT. The data structure of MPEG2 has a hierarchical structure, and includes a block layer, a macroblock layer, a slice layer, a picture layer, a GOP layer, and a sequence layer from the lowest level.

The block layer is a unit for performing DCT, D
It consists of a CT block. The macroblock layer includes a plurality of D
It is composed of CT blocks. The slice layer is composed of a header section and any number of macroblocks that do not extend between rows. The picture layer includes a header section and a plurality of slices. A picture corresponds to one screen. G
The OP (Group Of Picture) layer includes a header portion, an I picture that is a picture based on intra-frame coding, and P and B pictures that are pictures based on predictive coding.

A GOP includes at least one I picture, and P and B pictures are allowed even if they do not exist. The top sequence layer is composed of a header section and multiple GOPs.
It is composed of

In the MPEG format, a slice is one variable length code sequence. A variable-length code sequence is a sequence in which a data boundary cannot be detected unless a variable-length code is decoded.

At the head of each of the sequence layer, GOP layer, picture layer, slice layer and macroblock layer, an identification code (referred to as a start code) having a predetermined bit pattern arranged in byte units is provided. Be placed. Note that the header section of each layer described above collectively describes a header, extension data, or user data. In the header of the sequence layer, the size of the image (picture) (the number of vertical and horizontal pixels) and the like are described. The time code, the number of pictures constituting the GOP, and the like are described in the header of the GOP layer.

The macro blocks included in the slice layer are:
It is a set of a plurality of DCT blocks, and the encoded sequence of the DCT block is a variable of a sequence of quantized DCT coefficients, with the number of consecutive 0 coefficients (run) and a non-zero sequence (level) immediately after it as one unit. It is a long code. The macroblock and the DCT block in the macroblock are not added with the identification codes arranged in byte units.
That is, they are not one variable-length code sequence.

A macroblock is a picture (picture) of 1
It is divided into a grid of 6 pixels × 16 lines. A slice is formed by connecting these macroblocks in the horizontal direction, for example. The last macroblock of the previous slice of a continuous slice and the first macroblock of the next slice are continuous, and it is not allowed to form a macroblock overlap between slices. When the size of the screen is determined, the number of macroblocks per screen is uniquely determined.

On the other hand, in order to avoid signal deterioration due to decoding and encoding, it is desirable to edit the encoded data. At this time, the P picture and the B picture require a temporally preceding picture or a preceding and succeeding picture for decoding. Therefore, the editing unit cannot be set to one frame unit. In consideration of this point, in this embodiment, one GOP is made up of one I picture.

A recording area in which recording data for one frame is recorded is a predetermined area. MPEG2
Since the variable length coding is used, the amount of generated data for one frame is controlled so that data generated during one frame period can be recorded in a predetermined recording area. Further, in this embodiment, one slice is composed of one macroblock so as to be suitable for recording on a magnetic tape, and one macroblock is applied to a fixed frame having a predetermined length.

FIG. 1 shows an example of the configuration of the recording side of the recording / reproducing apparatus according to this embodiment. At the time of recording, a predetermined interface, for example, SDI (Serial Data Interface)
The digital video signal is input from the terminal 101 via the receiving unit of the above. SDI is an interface defined by SMPTE for transmitting (4: 2: 2) component video signals, digital audio signals, and additional data. An input video signal is converted by a video encoder 102 into a DCT (Discrete Cosine Transform).
form), is converted into coefficient data, and the coefficient data is subjected to variable length coding. The variable length coded (VLC) data from the video encoder 102 is an elementary stream compliant with MPEG2. This output is supplied to one input terminal of the selector 103.

On the other hand, through the input terminal 104, the ANSI
SDTI (Serial Data Transport Inter), which is an interface defined by / SMPTE 305M
face) format data is input. This signal is synchronously detected by SDTI receiving section 105. And
Once stored in the buffer, the elementary stream is extracted. The extracted elementary stream is supplied to the other input terminal of the selector 103.

The elementary stream selected and output by the selector 103 is supplied to a stream converter 106. In the stream converter 106, the MPE
The DCT coefficients arranged for each DCT block based on the G2 rule are replaced with a plurality of DCTs constituting one macroblock.
Through the T block, frequency components are grouped, and the grouped frequency components are rearranged. The rearranged converted elementary stream is stored in the packing and shuffling unit 1.
07.

Since the video data of the elementary stream is variable-length coded, the data length of each macroblock is not uniform. In the packing and shuffling unit 107, macro blocks are packed in a fixed frame. At this time, the portion that protrudes from the fixed frame is sequentially packed into a surplus portion with respect to the size of the fixed frame. Also, system data such as time code is input to the input terminal 108.
Is supplied to the packing and shuffling unit 107, and the system data is subjected to a recording process similarly to the picture data. Also, shuffling is performed in which the macroblocks of one frame generated in the scanning order are rearranged and the recording positions of the macroblocks on the tape are dispersed. Shuffling can improve the image update rate even when data is reproduced in pieces during variable speed reproduction.

Video data and system data from the packing and shuffling unit 107 (hereinafter, also referred to as video data even when system data is included unless otherwise required) are supplied to the outer code encoder 109. A product code is used as an error correction code for video data and audio data. The product code encodes an outer code in a vertical direction of a two-dimensional array of video data or audio data, encodes an inner code in a horizontal direction thereof, and encodes data symbols doubly. As the outer code and the inner code, a Reed-Solomon code can be used.

The output of the outer code encoder 109 is supplied to the shuffling unit 110 and a plurality of ECCs (Error Correction
ig Code) blocks are shuffled to change the order in sync block units. The shuffling in sync block units prevents errors from concentrating on a specific ECC block. Shuffling part 1
Shuffling performed at 10 may be referred to as interleaving. The output of the shuffling unit 110 is
1 and mixed with audio data. In addition,
The mixing unit 111 includes a main memory, as described later.

Audio data is supplied from an input terminal denoted by reference numeral 112. In this embodiment, an uncompressed digital audio signal is handled. The digital audio signal is supplied to an input SDI receiver (not shown)
These are separated by the DTI receiving unit 105 or input through an audio interface. The input digital audio signal is supplied to A
It is supplied to the UX adding unit 114. The delay unit 113 is for time alignment of the audio signal and the video signal.
The audio AUX supplied from the input terminal 115 is auxiliary data, and is data having information related to audio data such as the sampling frequency of audio data. The audio AUX is added to the audio data by the AUX adding unit 114, and is treated the same as the audio data.

The audio data and AUX from the AUX adding unit 114 (hereinafter, AUX unless otherwise necessary)
Is also simply referred to as audio data. ) Is supplied to the outer code encoder 116. Outer code encoder 11
No. 6 encodes an outer code for audio data. The output of the outer code encoder 116 is the shuffling unit 1
17 and undergoes a shuffling process. As audio shuffling, shuffling in sync block units and shuffling in channel units are performed.

The output of the shuffling unit 117 is
1 and the video data and the audio data are converted into data of one channel. The output of the mixing unit 111 is ID
The adding unit 118 is supplied, and the ID adding unit 118 adds an ID including information indicating a sync block number. The output of the ID addition unit 118 is the inner code encoder 119
, And the inner code is encoded. Further, the output of the inner code encoder 119 is supplied to the synchronization adding section 120, and a synchronization signal for each sync block is added. By adding the synchronization signal, recording data in which the sync blocks are continuous is configured. This recording data is supplied to the rotary head 122 via the recording amplifier 121, and is recorded on the magnetic tape 123. In practice, the rotary head 122 is configured such that a plurality of magnetic heads having different azimuths of heads forming adjacent tracks are attached to the rotary drum.

The scramble processing may be performed on the recording data as needed. Further, digital modulation may be performed at the time of recording, and a partial response class 4 and Viterbi code may be used.

Recording of signals on the magnetic tape is performed by a helical scan method in which a diagonal track is formed by a magnetic head provided on a rotating rotary head. A plurality of magnetic heads are provided on the rotating drum at positions facing each other. That is, when the magnetic tape is wound around the rotary head at a winding angle of about 180 °, a plurality of tracks can be simultaneously formed by rotating the rotary head by 180 °. The magnetic heads are formed as a set of two magnetic heads having different azimuths. The plurality of magnetic heads are arranged such that azimuths of adjacent tracks are different from each other.

FIG. 2 shows an example of the configuration on the reproducing side according to an embodiment of the present invention. Rotating head 1 from magnetic tape 123
The reproduction signal reproduced at 22 is supplied to the synchronization detection unit 132 via the reproduction amplifier 131. Equalization and waveform shaping are performed on the reproduced signal. Further, demodulation of digital modulation, Viterbi decoding, and the like are performed as necessary. The synchronization detection unit 132 detects a synchronization signal added to the head of the sync block. The sync block is cut out by the synchronization detection.

The output of the synchronization detection block 132 is supplied to the inner code decoder 133, where the error of the inner code is corrected. The output of the inner code decoder 133 is supplied to the ID interpolation unit 134, and the ID of the sync block in which the error occurred due to the inner code, for example, the sync block number is interpolated. The output of the ID interpolation unit 134 is supplied to the separation unit 135, where the video data and the audio data are separated. As described above, the video data means DCT coefficient data and system data generated by MPEG intra coding,
Audio data is PCM (Pulse Code Modulation)
Means data and AUX.

The video data from the separation unit 135 is subjected to a process reverse to shuffling in the deshuffling unit 136. The deshuffling unit 136 performs a process of restoring the shuffling in sync block units performed by the shuffling unit 110 on the recording side. Deshuffling part 136
Is supplied to the outer code decoder 137, and error correction by the outer code is performed. When an error that cannot be corrected occurs, an error flag indicating the presence or absence of the error is set to indicate the presence of the error.

The output of the outer code decoder 137 is supplied to a deshuffling and depacking unit 138. The deshuffling and depacking unit 138 performs processing for restoring shuffling in macroblock units performed by the packing and shuffling unit 107 on the recording side. In the deshuffling and depacking unit 138,
Disassemble the packing applied during recording. That is, the length of the data is returned in units of macroblocks, and the original variable length code is restored. Further, in the deshuffling and depacking unit 138, the system data is separated,
It is taken out to the output terminal 139.

Deshuffling and depacking section 13
The output of No. 8 is supplied to the interpolation unit 140, and the data for which the error flag is set (that is, there is an error) is corrected. That is, if it is determined that there is an error in the macroblock data before the conversion, the DCT coefficients of the frequency components after the error location cannot be restored. Therefore, for example, the data at the error location is replaced with a block end code (EOB), and the DCT coefficients of the subsequent frequency components are set to zero. Similarly, at the time of high-speed reproduction, only DCT coefficients up to the length corresponding to the sync block length are restored, and the coefficients thereafter are replaced with zero data. Further, the interpolation unit 1
In 40, when the header added to the head of the video data is an error, the header (sequence header, GOP
Header, picture header, user data, etc.) are also recovered.

Since the DCT coefficients are arranged from the DC component and the low-frequency component to the high-frequency component over the DCT block, even if the DCT coefficients are ignored from a certain position onward, the macro block , DCT coefficients from DC and low-frequency components can be distributed evenly to each of the DCT blocks constituting.

The output of the interpolation section 140 is supplied to the stream converter 141. In the stream converter 141, the reverse process to that of the stream converter 106 on the recording side is performed. That is, the DCT coefficients arranged for each frequency component across the DCT blocks are rearranged for each DCT block. Thereby, the reproduced signal is converted into an elementary stream conforming to MPEG2.

As for the input / output of the stream converter 141, a sufficient transfer rate (bandwidth) is secured in accordance with the maximum length of the macroblock, as in the recording side. When the length of the macroblock is not limited, it is preferable to secure a bandwidth three times the pixel rate.

The output of the stream converter 141 is supplied to the video decoder 142. Video decoder 142
Decodes the elementary stream and outputs video data. That is, the video decoder 142 performs an inverse quantization process and an inverse DCT process. The decoded video data is taken out to the output terminal 143. For the interface with the outside, for example, SDI is used. In addition, the elementary stream from the stream converter 141 is supplied to the SDTI transmitting unit 144. Although illustration of the path is omitted, the SDTI transmission unit 144 is also supplied with system data, reproduced audio data, and AUX, and
It is converted into a stream having a data structure of the TI format. The stream from the SDTI transmission unit 144 is output to the outside through the output terminal 145.

The audio data separated by the separation unit 135 is supplied to the deshuffling unit 151. The deshuffling unit 151 performs a process opposite to the shuffling performed by the shuffling unit 117 on the recording side. The output of the deshuffling unit 117 is supplied to the outer code decoder 152, and error correction by the outer code is performed. Outer code decoder 152
Output the error-corrected audio data. An error flag is set for data having an uncorrectable error.

The output of the outer code decoder 152 is supplied to an AUX separation section 153, where the audio AUX is separated.
The separated audio AUX is taken out to the output terminal 154. The audio data is supplied to the interpolation unit 155. The interpolating unit 155 interpolates a sample having an error. As the interpolation method, it is possible to use an average value interpolation for interpolating with the average value of correct data before and after in time, a previous value hold for holding a previous correct sample value, and the like. The output of the interpolation unit 155 is supplied to the output unit 156. The output unit 156 performs a mute process for inhibiting the output of an audio signal that is in error and cannot be interpolated, and performs a delay amount adjustment process for time alignment with a video signal. The reproduced audio signal is extracted from the output unit 156 to the output terminal 157.

Although not shown in FIGS. 1 and 2, a timing generator for generating a timing signal synchronized with input data, a system controller (microcomputer) for controlling the entire operation of the recording / reproducing apparatus, and the like are provided. Have been.

Next, the footprint for the magnetic tape and the format of the audio data in this embodiment will be described.

FIGS. 3 to 5 show types of audio error correction blocks which can be supported by the recording / reproducing apparatus according to this embodiment. Audio error correction blocks can be broadly classified according to differences in field (frame) frequency. The field (frame) frequency is 29.97
Hz, 59.94 Hz, 25 Hz, 50 Hz, 23.9
There are five types of 76 Hz. 29.97Hz, 25Hz,
23.976 Hz is a frequency in the case of progressive (non-interlace) scanning, and the other frequencies are interlaced scanning. FIG. 3 shows an example of a field (frame) frequency of 29.97 Hz / 59.94 Hz, and FIG. 4 shows an example of a field (frame) frequency of 25 Hz / 50 Hz. FIG. 5 shows a frame frequency of 23.976 Hz.
This is an example.

Since the frame period of the progressive scan is the same as the field period of the interlace, the frame and the field of the interlace scan are referred to simply as “frame and field” to avoid complexity. Are referred to as P frames.

The number of bits per audio sample is 16 depending on the difference in sound quality required in each format.
There are two types, bit and 24-bit. 3A, 4A and 5A show 16 bits / sample, and FIGS. 3B, 4B and 5B show 24 bits / sample. Note that the sampling frequency is all 48 KHz.

In the error correction block, error correction coding is performed in units of one symbol consisting of, for example, 8 bits (1 byte), and one row in the horizontal direction corresponds to a sync block. SY is a sync pattern on tape recording, and is assigned 2 bytes. The ID stores important information unique to the sync block, such as a sync number and a segment number video / audio, and is assigned 2 bytes. DID is audio 5FSe
Important information about audio data such as q (to be described later) information is stored therein, and one byte is allocated.

For example, an error correction block of 59.94 Hz, 16 bytes / sample is shown in the upper left of FIG. 1, and the number of data in one sync block is 119 bytes, the inner code parity is 12 bytes, and the outer code parity is 12 bytes. 1
It turns out that it is 0 bytes.

FIG. 6 shows the structure of a sync block. FIG. 7 shows the bit assignment of ID and DID in the sync block. In FIG. 6A, SYNC is a sync pattern on tape recording, and is 2 bytes (76 bytes).
B4h: h represents hexadecimal notation). S
Following YNC, a 2-byte ID is arranged, and a data area whose capacity is variable from 112 bytes to 189 bytes is arranged. The next 12 bytes are parity, and the inner code parity is stored.

In the data area, as shown in FIG. 6B, a 1-byte DID is arranged at the beginning, and audio data is subsequently stored. This entire data area is called the payload.

As shown in the left side of FIG. 7A, a sync ID which is an identification number of a sync block is stored in ID0. According to ID0, a different ID is assigned to each audio sync block on one track. I
D1 stores a segment number, video / audio identification bits, and the like, as shown on the right side of FIG. 7A. Azimuth number is azimuth information,

[0] or [1] is entered. Upper / Lower is the sink ID
In the additional information, the sync block on the track can be distinguished and identified by the 8 bytes of ID0, the video / audio identification bit, and the Upper / Lower. Edit IN is edit information, and this bit is recorded as [1] at the IN point at the time of editing.

FIG. 7B shows the bit assignment of the DID. NT Seq in DID is used to identify which sync block is the same field in non-tracking reproduction. For data / audio, [1] is set when data other than uncompressed audio data is stored in an audio sync block. 5FSeq
Has a frame (field) frequency of 59.94 Hz,
Information about a 5-field sequence generated in the case of 29.97 Hz is entered.

A five-field sequence is a five-field sequence when the sampling frequency of audio data is 48 KHz.
One cycle of a field is 4004 samples / 5 fields. When these are assigned to each field, 800, 801, 801, 801, 801 samples / field are assigned. This is 5
This is called a field sequence.

FIG. 8 shows a layout of one channel and one field audio error correction block when the frame (field) frequency is 29.97 Hz and 59.94 Hz. FIG. 8A schematically shows the arrangement, and FIG. 8B shows in more detail. This is the same in FIGS. 9 and 10 described below. 800 or 801 samples per field are divided into two error correction blocks in which even-numbered samples and odd-numbered samples are stored, respectively. In FIG. 8, AUX0, AUX1,
AUX2 is AUX data and stores auxiliary data relating to audio.

Each frame corresponds to the data length of one sample, and the numbers in the frames correspond to sample numbers indicating the sample order of audio data. Further, PVx is an outer code parity described later. Numbers 0 to 800 are audio sample data, and as described above, there are five field sequences, 800 or 80.
One sample / field. In the case of 800 samples / field, the 798th sample stored in the 798th is copied to the 800th.

PV0 to PV9 are outer-code parities of a vertical series and have 10 bytes. The outer code number is a number for collectively calling sync blocks that are horizontal data. Since one field (1P frame) has 36 sync blocks, the outer code number is 0 to 35.

FIGS. 9 and 10 show that the frame (field) frequency is 25 Hz / 50 Hz and 23.976H, respectively.
7 is a layout of an audio error correction block in the case of z. These are the same as those shown in FIG. 8 except for the difference in the sample number accompanying the change in the total number of samples.
It is the same as the case of 97 Hz / 59.94 Hz.

FIGS. 11 to 14 show examples of channel allocation on the footprint in each format. There are four types of formats referred to as SD1 to SD4, respectively. 11 is SD1, FIG. 12 is SD
2, FIG. 13 shows SD3, and FIG. 14 shows SD4. In each figure, a square represents one sector, and Ax in the square represents an audio channel number. The numbers “9” and “6” on the right side of each figure are the number of sync blocks per sector.

For example, in the case of the format SD1,
As shown in FIG. 11, there are four channels from A0 to A3, and 9 [sync block] × 2 [sector / track, channel] × 4 [track / frame] = 72
It can be seen that they are sync blocks / channels and frames. That is, it is understood that each channel is 72/2 = 36 sync blocks per field. When the formats SD2 to SD4 are similarly calculated, in one field or 1P frame, there are 36 sync blocks / channel and field per channel. This corresponds to the 36 outer code numbers per field (1P frame) in FIGS. 8 to 10 described above.

The number of tracks per field or 1P frame is different because the amount of data is different in each format due to the difference in compression ratio in video, and the required number of tracks is different accordingly. In this embodiment, audio data is treated uncompressed, and the amount of audio data per field (1P frame) is:
Always the same. Therefore, the audio is also divided into SD1 to SD4 formats according to the number of tracks required for video.

FIG. 15 shows the outer code number allocation in each format. FIG. 15A is an example of the format SD1, and FIG. 15B is an example of the SD4. FIG. 15C shows an arrangement common to the formats SD2 and SD3. It shows how the outer code numbers of one channel and one field are arranged with respect to the segment and the azimuth. In this figure,
The number written in the square is the outer code number. The arrows in the figure indicate the direction of head tracing. One row in the horizontal direction corresponds to one sector. For example, in SD1, 1
It can be seen that the audio data for one channel is arranged over two sectors.

As can be seen from FIGS. 15A to 15C, the 36 outer code numbers for one field are shuffled and rearranged in order. It is shown that the left side is recorded first depending on the direction of the head trace. For example, in the case of SD3 (SD2) in FIG. 15C, outer code numbers 19 and 18 are recorded at the head.

In this example, one sector of azimuth 0 and segment 0 has outer code numbers 19, 21, 0, 4, 8, and 1
It consists of 2, 16, 23 and 25 9 sync blocks. This one sector is azimuth 0 and segment 0. If this is A0, this one sector is written in azimuth 0 and segment 0 of format SD3 shown in FIG. Also, the outer code numbers 28, 30, 1, 5,.
One sector 9, 13, 17, 32 and 34 is azimuth 1 and segment 1. If this is A0, this one sector is written to azimuth 1 of SD3 and A0 of segment 1 in FIG. Become.

Next, an audio decoding process in this embodiment will be described. FIG. 16 shows an example of the configuration of the decoder 1 used in this storage / reproduction device.
The decoder 1 is configured without, for example, one IC (integrated circuit). This configuration is similar to the configuration of the separation circuit 135 and the deshuffling circuit 151 in FIG.
To the output unit 156. The decoder 1 deshuffles the shuffled reproduction signal during recording and rearranges the reproduced signal in the original order. Then, they are called Adv and Conf, respectively.
It outputs audio data of a total of 16 channels, two channels at a time.

The timing generation block 10 generates various timing signals, control signals, and various information required in the decoder 1 based on the supplied various signals.
The control signal generated by the timing generation block 10 is supplied to the RC block 19. Various information generated by the timing generation block 10 is supplied to the deshuffling unit 11 and the AOT block 16.

The reproduced data reproduced from the magnetic tape 123 and subjected to synchronization detection, inner code correction and ID interpolation are supplied to the deshuffling unit 11 in sync block units.
The deshuffling unit 11 includes a channel deshuffling RAM 14 and a sync deshuffling RAM 15.
Based on the deshuffling tables respectively stored in the SDRAM (Synchronous DRAM) 13, an address for writing data to the SDRAM (Synchronous DRAM) 13 is generated. This address is supplied to the SDRAM controller 12 together with the reproduction data. The playback data is in SDR based on the supplied address.
Under the control of the AM controller 12, the data is rearranged in the original data order and written to the SDRAM 13.

The data read from the SDRAM 13 is supplied to the AOT block 16 and is stored in the outer code RAM 1.
Outer code correction is performed using 7A and 17B. In the AOT block 16, an error flag and AUX data are extracted. The reproduced data whose outer code has been corrected is classified into Adv and Conf based on the information of ID1 and AUX data, is divided for each channel, and is output from the AOT block 16. At this time, the signal path for two channels is used as one signal path, for a total of 8 signal paths.
A book signal is output. The four outputs of the Adv system are supplied to the rate conversion RAMs 18A to 18D, respectively. Similarly, four outputs of the Conf system are supplied to the rate conversion RAMs 18E to 18H, respectively. In each figure, the RA for rate conversion is used.
M is abbreviated as RC RAM.

RAMs 18A-18H for rate conversion
Are controlled by the RC block 19. The RC block 19 includes the AOT block 1
6 supplies a control signal to the RC block 19
Supplies a field start signal to the AOT block 16. Based on the control of the RC block 19, the reproduced audio data is read from the rate conversion RAMs 18 </ b> A to 18 </ b> H in 8-bit parallel and supplied to the AIF block 20.

The AIF block 20 converts the supplied reproduced audio data into parallel / serial data and outputs it as output data of eight channels and two systems. In the AIF block 20, modification of audio data, mute processing, and the like are performed as necessary.

Next, each part of the decoder 1 will be described in more detail. The timing generation block 10 receives a TG-frame which is a frame signal, a TG-AVSTO which is a field signal, a TG-5F-ID which is a reference 5-field sequence ID, and an FS which is a sample separation signal, and is necessary inside the decoder 1. It generates various timing signals, control signals, and various information.
The timing generation block 10 includes an Adv path number, Ad
v Light field bank number, Conf pass number, and Conf light field bank number (described later)
To the deshuffling unit 11 as a control signal.

The deshuffling unit 11 is supplied with reproduced data whose inner code has been corrected. The outer code has not been corrected for this reproduced data. Then, by using the channel deshuffling RAM 14 and the sync deshuffling RAM 15, deshuffling is performed, and an address for writing reproduction data to the SDRAM 13 is generated. According to this address, the reproduced data is transferred to the SDRAM 12
, The reproduction data is deshuffled. The address information and the reproduction data are supplied to the SDRAM controller 12 and the SDRAM controller 1
The reproduction data is written to the SDRAM 13 by the address control of 2.

The processing in the channel deshuffling RAM 14 and the sink and shuffling RAM 15 will be described in more detail. The RAMs 14 and 1
The processing in 5 is a part related to the gist of the present invention.

Referring to FIGS. 17 to 19, SDRAM 13
Will be described. SDRAM13
Then, write the audio data separated by fields. The area of the SDRAM 13 where one field is stored is called a field bank. In this embodiment, S
The DRAM 13 has eight field banks, and can store audio data for eight fields.

FIG. 17A shows a data block stored in one field bank. One row in the horizontal direction is a sync block.
A byte number in the sink is assigned to each byte. The sync blocks are arranged in the column direction, and an outer code number is assigned to each. The address assignment of the SDRAM 13 is
As shown in FIG. 17B, following the 2-bit ID, 1
Conf / Adv value of bits, outer code number of 6 bits,
The field bank value of 3 bits, the channel number of 3 bits, and the byte number in the sync of 6 bits are 2 in total.
It consists of one bit.

FIG. 18 shows an example of the configuration of a sync block on the SDRAM 13. The sync block is shown in FIG. 18A
As shown in (1), on the SDRAM 13, it is composed of PS number 0, PS number 1, AIX0, AIX1, DID and data.

The PS number is an abbreviation of a path number. For PS Nos. 0 and 1, the new data is SD
When the data is not written on the RAM 13, the data is used to determine that the data is old. The PS numbers 0 and 1 are simply incremented every eight fields (each cycle of the field bank of the SDRAM 13). That is, the 16 sent from the timing generation block 10
Bits and numerical values from 0 to 65535 are stored in PS numbers 0 and 1. Rsv is an abbreviation for Reserved,
Dummy data is stored.

FIG. 18B shows the bit assignment of AIX0. Bits 7 and 6, bits 4-0 are Re
serviced. FabSYNC of bit 5 is a bit that is set when it is determined that there is a high possibility that this sync block is not a normal sync block due to a disorder in the distance between sync blocks when correcting the inner code.

FIG. 18C shows the bit assignment of AIX1. Jump is used, for example, at the time of variable-speed reproduction in which reproduction is performed at a speed different from that of recording. DT (Dynam
ic Tracking) The value is set to 1 when the head jumps one field. TapeDir is the tape running direction, and has a value of 1 at the time of forward and a value of 0 at the time of reverse. The value of the inner code error is set to 1 in the case of a sync block in which an error occurred during the inner code correction.

The DID is the DI which has already been described with reference to FIG.
D itself is stored.

The sync blocks stored in the SDRAM 13 correspond to the above-mentioned PS numbers 0 and 1, AIX 0 and 1 for one row of data in the horizontal direction in FIG. 3 to FIG. 5 or FIG. , And DID to which additional information is added.

As described above, in the sync block, the byte number in the sync is assigned to each byte. In this embodiment, the SDRAM 13 has a 32-bit width. Therefore, the data of the sync block is
As shown in FIG. 19, an address is provided every four bytes. Therefore, on the SDRAM 13, the address is assigned by the upper 6 bits ([7: 2]) of the byte number in the sink.

As shown in FIG. 18B, SDRAM 1
Address 3 is created and written using Adv / Conf, outer code number, field bank and channel number, and in-sync byte number. Adv / Conf
Is determined based on the information given by the system when the inner-code corrected data arrives at the deshuffling unit 11. The field bank is the Adv / Conf Wr field bank number itself supplied from the timing generation block 10.

In the byte numbers in the sink, numbers 0 to 7 are assigned to the numbers of the additional information. On the other hand, the number of the data is determined by offsetting and incrementing the value when the data whose inner code is corrected is supplied. The additional information for the inner code corrected data is only ID0 and ID1 shown in FIG. 7, and there is no information of the outer code number and the channel number. Therefore, in order to create an outer code number and a channel number from the information of ID0 and ID1, the channel deshuffling R
The AM 14 and the sink deshuffling RAM 15 are used.

The processing in the channel deshuffling RAM 14 will be described with reference to FIG. First, a sector number within a track is generated from the sync number of ID0 and the information of upper / lower of ID1. The sector number within a track indicates an audio sector within one track,
The numbers are given in the order of the head trace.

ID0 is, as shown in FIG.
In each audio sector of “per / lower”, the audio sectors are assigned in ascending order in the head trace direction. Therefore, the sector number in the track is the upper ID of ID1.
/ Lower and ID0. In the example of FIG. 21, ID0 is [24h] and ID1 is up.
If per / lower is [1], the sector number in the track is [6].

The channel deshuffling RAM 14 stores a deshuffling table that gives a channel number as a return value when a sector number within a track and the SEG number of ID1 are given as addresses.
These values are supplied as addresses from the deshuffling unit 11 to the channel deshuffling RAM 14, and the corresponding channel number is output from the RAM 14. The RAM 14 for channel deshuffling
Can be rewritten by a system controller (not shown). By rewriting this deshuffling table according to the format of the data, any format change can be handled.

FIG. 22 shows the R for channel deshuffling.
Track sector number and SEG supplied to AM14
An example of bit assignment with numbers is shown. As shown in FIG. 22A, the number of bits required for each value differs in each of the formats SD1 to SD4. In this embodiment, as shown in an example in FIG. 22B, bits are assigned to each format.

The processing in the sink deshuffling RAM 15 will be described with reference to FIG. Given the sector number in the channel field and the sync number in the sector as an address, the sink deshuffling RAM 15 returns the outer code number as a return value. The sector number in the channel field is a number indicating the number of sectors in the same channel and the same field in the same channel, with the sectors of azimuths 0 and 1 as a pair. For example, in the example of FIG. 21 described above, each sector of Seg1 becomes the second sector when sectors of azimuths 0 and 1 are counted as a pair in the same channel and the same field. Therefore, in the counting method of 0, 1, and 2, the sector number is 1 in the channel field.

Similarly, since Seg2 is the first sector of a new field, the sector number is 0 in the channel field.

FIG. 24 shows the bit assignment of the sector number in the channel field, the azimuth number, the sync number in the sector, and the outer code number in each of the formats SD1 to SD4. In the case of SD2 and SD3, the sector number and Seg number in the channel field have the same value of 1 bit. In the case of SD4, the sector number and the Seg number in the channel field have the same value of 2 bits. On the other hand, in the case of SD1, as can be seen from FIG. 11 described above, the same channel enters Upper and Lower in the same track.
Therefore, the sector number in the channel field is
This is the same 1-bit value as 1 upper / lower.

In FIG. 24, the intra-sector sync number is a number indicating the number of the sync block counted in the head trace order within the same sector. FIG.
In the example of SD2, there are 9 sync blocks in one sector, and the sync number in the sector is the lower 4 of ID0.
Required in bits. As described above, when the sector number in the channel field, the azimuth number, and the sync number in the sector obtained in this way are provided as addresses from the deshuffling unit 11 to the RAM 15 for sync deshuffling, RAM
From 15, the outer code number is returned to the deshuffling unit 11 as a return value.

FIGS. 25 and 26 show more specific examples in which the outer code number is obtained as described above. FIG. 25A
Is an example of the format SD1, and FIG. 25B is an example of the format SD4. FIG. 26 shows an example of the format SD2.

The sink deshuffling RAM 15
Can be rewritten by a system controller (not shown). By rewriting this deshuffling table according to the format of the data, any format change can be handled.

As shown in FIG. 24B, the number of bits required for the sector number in the channel field and the sync number in the sector are different between the formats SD1 to SD3 and SD4. However, since the total required number of bits is equal to the total number of required bits, by changing the bit allocation according to the format when generating the address, the required number of bits is finally saved.
A bit assignment according to the format is instructed by a system controller (not shown).

As described above, the value required for the address calculation of the SDRAM 13 in the deshuffling unit 11 is obtained by using the RAM 14 for channel deshuffling and the RAM 15 for sink deshuffling. The obtained address is sent to the SDRAM controller 12 together with the data.
The data is written to the SDRAM 12 according to the transmitted address under the control of the SDRAM 12 controller 12. The address assignment of the SDRAM 13 is Con
Since they are arranged and arranged in the SDRAM 13 by f / Adv, field bank, channel, and outer code number, the subsequent processing such as outer code correction is simplified.

The AOT block 16 controls reading of the SDRAM 13, extracts an error flag from the read data, reads control, extracts an error flag, controls the outer code RAMs 17A and 17B, corrects the outer code, and converts the rate to the RAM 18A. It has the functions of writing control of ~ 18H and sampling of AUX data.

FIG. 27 is a timing chart of audio processing performed by the AOT block 16. The field generation control signal (Fld-Start) is supplied from the timing generation block 10 (FIG. 27A). The signal Fld-Start is, for example, a pulse signal output at a transition of a field. In the AOT block 16, various processes are performed based on this signal. In the following description, the signal F output immediately after
A field starting from ld-Start is defined as a new field, and a field before the signal Fld-Start is defined as an old field to distinguish them.

As described above, as a general process flow, data is read from the SDRAM 13 by the AOT block 16 and written to the outer code RAM 17A or 17B (FIG. 27B). Then, outer code correction is performed on the data written in the outer code RAM 17A or 17B. The outer code corrected data is read out from the outer code RAM 17A or 17B (FIG. 27C), and the rate conversion RAMs 18A to 18A are output.
8H is written to the corresponding one (FIG. 27
D). The data written in the rate conversion RAMs 18A to 18H are read out in a time-division manner for each channel based on a predetermined clock.

The AOT block 16 allows the SDRAM
Of the thirteen field banks, the bank corresponding to the new field is calculated. This is calculated based on information supplied from the timing generation block 10 as an Adv / Conf RdFld bank number. Then, an error flag is read from the data stored in the bank. Data is read from the bank and written to the corresponding side of the outer code RAM 17A or 17B. By the AOT block 16,
Using the error flag read from the SDRAM 13,
Outer code correction is performed on the data written in the outer code RAM 17A or 17B (the processing of the portion "A" in FIG. 27B).

[0103] These processes will be described in more detail.
The AOT block 16 specifies the address of the SDRAM 13 having the corresponding field bank number. This address is sent from the AOT block 16 to the SDRAM controller 12. The SDRAM controller 12 reads data from the SDRAM 13 according to this address.

As shown in FIGS. 27F to 27I, the outer code correction processing is performed in a time-division manner by dividing into slots. Note that FIG. 27 shows only the signal system Adv among the two signal systems Adv and Conf. In FIG. 27F to FIG. 27I, what is indicated by “Conf” is a slot for processing the Conf system, and it can be seen that Adv and Conf are processed alternately in a time division manner.

The slots are further divided into smaller slots. First, Ps numbers 0 and 1, AIX 0 and 1, DID, and D0 to D11 are read from data having an even outer code number of channel 0. At this time, AIX1
The bit 0 error flag is stored in a register. When the error flag is determined, the Adv / Conf path number supplied from the timing generation block 10 and the SD
The pass numbers read from the RAM 13 are compared, and if they are different, it is determined that old data remains,
The old data sync block is treated as an error.

FIG. 28 shows how the pass number (PS number) is written and read. 28A and 28
B is a chart at the time of writing. 28C and 28D are charts at the time of reading. SDRA
When data is written to M13, Adv /
The Conf light field number is compared with the pass number. Each time the inner code corrected data is supplied based on the comparison result, the SDR of the corresponding field bank number is
Data is written to the address of AM 13 with a pass number.

Here, if all the sync block data for one field has arrived, all the pass numbers are updated to new ones. On the other hand, if there is no sync block data, that part of the SDRAM 13 has not been updated. At that time, the pass number is not updated, but contains the old value.

The path number information to be read from the SDRAM 13 is supplied from the timing generation block 10 to the AOT block 16. If the supplied pass number is different from the pass number of the corresponding portion of the SDRAM 13, it is determined that the data on the SDRAM 13 is old data that has not been updated. In the example of FIG. 28, the Ps number 297 and the Ps number 298 are mixed in the bank 2, and it can be seen that there is a sync block that has not been updated.

As described above, even if the data has not been updated, the outer code is corrected as usual, mainly with the old data. In order to prevent this, when there is a certain number of unupdated sync blocks, normal outer code correction is prohibited, and outer code correction mainly using old data is prevented. However, erasure correction is allowed. In this embodiment, it is determined whether or not the sync block has been updated using the Ps number, and the unupdated data is treated as an error. The data to which the outer code parity is added after the data D0 in the sync block is temporarily stored in the outer code RAM 17A or 17B.

FIG. 29 shows the outer code RAMs 17A and 17A.
7B shows an example of an address assignment of 7B. The dummy in the figure is an area that is not actually used, but has no meaning in the address assignment. In FIG. 29,
The byte numbers given in the row direction are for convenience of explanation.
It is a number in byte units. In the column direction,
An outer code number is assigned. First, FIGS. 27F to 27H
Of the parts described as Ch0 and Evn are performed.
Here, the processing is performed on the data of channel 0 whose outer code number is even.

The data read from the SDRAM 13 is written into, for example, the outer code RAM 17A. Then, byte numbers 0 to 11 are filled in FIG. Next, data is read from the outer code RAM 17A one by one (that is, one byte number) in the vertical direction (column direction) of FIG. 29 from the outer code RAM 17A. An error flag stored in the above-described register is added to the read data. And the outer code RAM 17
The AOT block 16 performs outer code correction on the data read from A and to which the error flag has been added. The outer code correction is performed on 12 bytes of data in FIG. 29, that is, on 12 data in the column direction.

In this embodiment, the decoders 1 are provided with outer code RAMs 17A and 17B. Of these, the outer code RAM 17A is
The outer code RAM 17B corresponds to the Con system and corresponds to the v system.

The data whose outer code has been corrected is written to the rate conversion RAMs 18A to 18H. FIG. 27F
27I, in the Adv sequence, processing of data having an even outer code number of channel 0 continues from processing of data having an even outer code number of channel 0. In the same manner, the process of the channels 1, 2,... In this way,
Outer code corrected data is stored in the corresponding one of the rate conversion RAMs 18A to 18H.
In this example, the data of the channels 0 and 1, the channels 2 and 3, the channels 4 and 5, and the channels 6 and 7 of the Adv sequence are stored in the rate converter RAM 18.
A, 18B, 18C, and 18D, respectively.

FIG. 30 shows a RAM 18 for rate conversion.
An example of address assignment of A to 18H is shown. Byte numbers are assigned in the row direction, and the column direction corresponds to the outer code number. As described above, in this embodiment, two types of audio data are used, one sample being 16 bits and one sample being 24 bits. These two
For the type of data, the rate conversion RAM 18A ~
The storage method for 18H differs from each other. Data of 16 bits (2 bytes) where one sample is 16 bytes (0 and 1), for example, two byte numbers are set as one set, and data is packed in the row direction. On the other hand, data of one sample of 24 bits (3 bytes) is a set of three byte numbers, for example, byte numbers 0, 1, and 2, and the data is packed in the row direction.

The rate conversion RAMs 18A-
18H includes three banks, banks 0, 1, and 2.
These banks 0, 1 and 2 respectively correspond to 12 banks of the outer code RAMs 17A and 17B shown in FIG.
The data portion of the main data excluding the outer code parity can be stored. In FIG. 27E described above, the numbers written in the squares indicate the bank numbers. The rate conversion RAMs 18A to 18H are read cyclically. Therefore, as shown in FIG. 27E, the bank number is also cyclically set to 0, 1, 2, 0,
It can be switched to 1, 2,...

On the other hand, in FIG. 27B, each outer code RA
The numbers (for example, 2, 0) written above the line indicating the write timing for M17 are the outer code RAM17.
Write to A or 17B, outer code RAM1
It indicates the bank number for reading from 7A or 17B and writing to the rate conversion RAMs 18A to 18H. RAM 18A for rate conversion
-18H are controlled so that writing and reading do not overlap in time.

After the process of “A” in FIG. 27B, the process proceeds to a process described as “B”. In “B”, D0 to D
The processing subsequent to 11 is performed. That is, D12 to D2
5 in the same manner as described above.
It is read from AM13. The read data is stored in a byte number 24 in the outer code RAM 17A or 17B.
Written for all of them. Then, the data is outer-code corrected, and the rate conversion RAMs 18A to 18A are output.
8H is written to the corresponding one. In the example of FIG.
For example, banks 0, 1 of the rate conversion RAM 18A
Is written to. Thus, hereinafter, D26 to D4
9, D50 to D73,..., And one field of data is processed.

Returning to FIG. 16, the RAM for rate conversion
The reading of 18A to 18H is controlled by the RC block 19. Reading from the rate conversion RAMs 18A to 18H is controlled by the RC block 19, and audio data of a total of 16 channels of Adv channels 0 to 7 and Conf channels 0 to 7 is time-division multiplexed and transmitted to the AIF block 20. Supply.

FIG. 31 schematically shows a time division process of data transmission from the RC block 19 to the AIF block 20. FIG. 31 illustrates an example in which one sample is audio data of 24 bits. The sample top signal shown in FIG. 31A is a signal having an FS cycle corresponding to a sample cycle having a frequency of 48 KHz. With this sample top signal, a break in each sample of the audio data transmitted as shown in FIG. 31B is identified. The data is a data and an error flag, and the bit width is 9
Transmitted in bits. Data for 16 channels of the Adv sequence and the Conf sequence are time-division multiplexed and transmitted.

FIGS. 31C and 31D show the one FS cycle in FIGS. 31A and 31B in more detail. The data of 24 bits / sample is handled by MSB (most significant byte), MDB (intermediate byte) and LSB (least significant byte) of 8 bits each. First,
Each of these MSB, MDB and LSB is FS
A clock (ck) having a speed 256 times the cycle is output every four clocks. First, the data of the channel 0 of the Adv sequence is output.
The data of channels 2, 4, and 6 of the v series are sequentially output, and further, channels 0, 2, 4, and 6 of the Conf series are output.
Are sequentially output. Subsequently, data of Adv-sequence channels 1, 3, 5, and 7 are sequentially output, and further, data of Conf-sequence channels 1, 3, 5, and 7 are sequentially output. There is an interval of 16 clocks between each channel. In this way, audio data for a total of 16 channels, that is, the data of the Adv channel 0 to 7 and the data of the Conf channel 0 to 7 are time-division multiplexed and transmitted to the AIF block 20.

FIG. 32 shows an example of the configuration of the AIF block 20. In the AIF block 20, 16 channels supplied as parallel data from the RC block 19 are divided into, for example, AES / E for each channel.
The data is converted into serial data conforming to the BU standard. Also,
The AIF block 20 performs data modification based on an error flag added to the supplied audio data, simple mute processing, filter processing during variable-speed reproduction (shuttle filter), inclination level control processing, and the like.

First, with reference to FIG. 33, each processing of data modification, simple mute, and shuttle filter will be schematically described. In FIG. 33, “x (cross)” indicates a sample that should be originally there but has been lost due to an error, and “△ (triangle)” indicates data actually complemented. . Further, “○ (circle)” indicates a normal sample.

FIG. 33A shows a data modification process. The data correction is performed by complementing the error data by taking the average of the preceding and following samples. FIG. 33B shows a simple mute process. The simple mute performs a simple mute when an error continues or when, for example, the video tape recorder stops reproduction and a mute is required.
The held normal data is shifted to reduce the data value by half. Thereby, simple muting is performed. FIG. 33C shows the shuttle filter processing. The shuttle filter reduces noise caused by abrupt changes in data at the time of shuttle reproduction in which reproduction is performed at a speed different from that at the time of recording. Find the average of the data at that time and the next sample data,
The result data is output as processing sample data.

FIG. 34 is a diagram for explaining the inclination level control processing. The slope level control process prevents a steep waveform from occurring in a transitional state when sound is produced from a mute state. For example, as shown in FIG. 34A, when the waveform becomes steep at the rising edge, pulse-like noise appears at that time. In order to prevent this, the data value is gradually inclined so as not to have a steep waveform. Specifically, the upper 8 bits of the audio sample are first shifted by 8 bits to a state of 0, and the shift amount is gradually reduced to increase the value by two times. As a result, as shown in FIG. 34B, the data level is controlled with a slope.

In FIG. 32, audio data input to the AIF block 20 is supplied to a delay circuit 201 and also to first input terminals of averaging circuits 204 and 205 and a selector control circuit 202. The delay circuit 201 compares the supplied data and the error flag for one FS cycle (that is, for one sample).
Delay. The data delayed by the delay circuit 201 and the error flag are supplied to the second input terminals of the hold register unit 203, the average value circuits 204 and 205, respectively.
The signal is supplied to the gradient level control circuit 206 and the selector control circuit 202.

The error flag is stored in the hold register section 20.
3, channels 0 to 7 of the Adv system, Co
These are stored in registers of channels 0 to 7 of the nf system, respectively. Of course, in the hold register unit 203,
Audio data is also stored in the register of the corresponding channel.

The selector 208 includes a delay circuit 201
Is output as current data. Further, the hold register unit 203 and the average value circuit 20
4 and 205, and a slope level control circuit 206
Are supplied to the selector 208. The selector 208 is controlled by the selector control circuit 202 to select a selection input terminal based on the state of the error flag, and a process for audio data is selected.

If there is an error flag and data modification processing is necessary, the average value circuit 204 calculates an average value from the output of the hold register unit 203 and the data directly supplied from the RC block 19. , And use the result as modified data.

When simple mute is required, the hold data held in the hold register section 203 is output, and then the data is shifted by the 1/2 circuit 207,
Reduce the data value by half. Then, the hold data is recursively reduced by ２, for example, the data is stored in the hold register unit 203, and a simple mute is performed.

The shuttle filter processing is performed by always calculating the average value of the current data and the data supplied from the RC block 19 by the average value circuit 205 and using the result.

The slope level control circuit 206 controls the shift amount of the 8 bits on the MSB side as needed to perform the slope level control. The selector control circuit 202 monitors the status of the error flag, and based on the status, based on the status, the hold register unit 203, the average value circuits 204 and 205, the slope level control circuit 206, and the delay circuit 201.
Select each output. This allows simple mute processing,
Data correction processing, shuttle filter processing, gradient level control processing, and non-processing (current data) are appropriately selected.

The register group 209 is composed of Adv channels 0/1, 2/3, 4/5, 6/7, and Co
nf channel 0/1, 2/3, 4/5, 6/7
Has eight registers respectively corresponding to. The audio data supplied from the selector 208 in a time-division manner is temporarily stored in the corresponding registers of the register group 209, respectively. The audio data output from each of the registers of the register group 209 is P / S
The data is sent to the register group 210, and the parallel / serial conversion is performed by shifting the register. Then, audio data converted into serial data is output for each system and channel. The data is output as one signal for every two channels.

FIG. 35 conceptually shows the structure of AIF block 20 shown in FIG. The data output from the RC block 19 is supplied to the delay circuit 201 and to the audio processing unit 220. The data output from the delay circuit 201 is supplied to the hold register unit 203 and the audio processing unit 2
20.

The hold register section 203 has registers 203A to 203P corresponding to each of Adv and Conf channels. Registers 203A-20
3H is for 8 channels of the Adv system, and the registers 203I to 203P are for 8 channels of the Conf system. From the RC block 19 to the hold register unit 20
31, data and error flags are supplied in a time-division manner for each channel as shown in FIG. The data and the error flag are stored in the registers corresponding to the channels of the registers 203A to 203P via the switch 230.

The data and error flags of each channel stored in the hold register section 203 are supplied to the audio processing section 220 as needed. For example, when performing the above-described simple mute processing, data modification processing, and shuttle filter processing, the data and error flags stored in the hold register unit 203 are used. At this time, the register 2 is switched by the switch 230 '.
03A to 203P are selected in a predetermined order.

The audio processing section 220 includes the selector control section 202, the average value circuits 204 and 20 shown in FIG.
5. Slope level control circuit 206 and selector 2
08 are collectively expressed. The half circuit 207 for performing the simple mute processing is also provided in the audio processing unit 2.
20, but omitted in FIG.

From the RC block 19 to the audio processing unit 2
A plurality of channels are time-division multiplexed to supply audio data. On the other hand, in the hold register unit 203, audio data and an error flag of each channel are stored in the corresponding registers 203A to 203P, respectively. Registers 203A-20
By selecting a register corresponding to the input audio data from among the 3Ps and using the audio data and the error flag stored in the register, the audio processing unit 220 allows the audio data of each channel to be Processing can be performed.

For example, at the time of data modification processing, a register corresponding to the channel of the data supplied to the average value circuit 204 is selected from the registers 203A to 203P.
The error flag and data are read. In the average value circuit 204, a data modification process is performed based on this data and data directly supplied from the delay circuit 201 and the RC block 19.

Thus, the audio processing unit 220
Commonly used for each channel. That is, there is no need to prepare the audio processing unit 220 for each channel.

The audio data that has been subjected to predetermined processing by the audio processing unit 220 is output serially from the audio processing unit 220 for each channel,
Supplied to The register group 209 includes eight registers 209 for storing data of channels paired with each other.
A to 209H. Registers 209A to 209D
Are registers for storing Adv series data, and registers 209E to 209H are registers for storing Conf series data. The register group 209 is used as a buffer for supplying data to the subsequent P / S register group 210 at a predetermined timing.

Channel serial /
The data supplied in a bit-parallel manner selects the register corresponding to the channel by the switch 231 and stores the data. The data stored in the registers 209A to 209H is stored in the register 21 of the P / S register group 210.
The signals are supplied to corresponding registers 0A to 210H, respectively, and are latched in bit parallel. Then, in each of the registers 210A to 210H, the latched data is shifted, and is converted into serial data in which two channels are integrated into one system and output as audio data.

It should be noted that the RC block 19 sends the register group 2
Since the path to 09 shares a plurality of channels by time division multiplexing, the number of wirings can be reduced. For example, in the case where audio data having a bit width of 24 bits per channel is handled by 16 channels, 16 (channels) × 24 (bits) = 384 wirings are required for parallel processing. On the other hand, in this embodiment, time division processing is performed for each channel, and data having a bit width of 24 bits per channel is transmitted in units of one word composed of 8 bits. I'm done with a book.

FIG. 36 is a time chart of the processing in the AIF block 20. In FIG. 36, particularly, a portion supplied from the register group 209 to the P / S register group 210 and subjected to parallel / serial conversion is mainly shown.

The audio data of a plurality of channels is time-division multiplexed and output from the RC block 19, and the data delayed by 1 FS by the delay circuit 201 is subjected to each audio processing by the audio processing section 220, and the timing shown in FIG. Is output from the audio processing unit 220. Samples for all output channels (16 channels) are processed within one FS cycle.

The order of time division multiplexing is as shown in FIG.
As shown in (1), the channels that are paired in the output have a time difference of 1 / 2FS. For example, Ch0 and Ch1 of the Adv sequence paired with each other
Indicates that the samples are separated by 1 / 2FS.

Each data output from the audio processing unit 220 is stored in each of the registers 209A to 209H of the register group 209 as described above. The storage of data in the registers 209A to 209H is as shown in FIG.
As shown in B, the processing is performed at time-division timing.
In FIG. 36B, the registers 209 are sequentially arranged from the top.
The storage timing of data from A to 209H is shown. As described above, there is a time difference between the timing at which data is stored in each of the registers 209A to 209H.

As shown in FIG. 36C, the data stored in the registers 209A to 209H are latched by the registers 210A to 210H of the P / S register group 210 every 1 / 2FS from the timing of the sample top signal. Note that in FIG. 36C, the registers 2
The timing of latching data from 10A to 210H is shown. 1/2 from the timing of the sample top signal
Adv output from the audio processing unit 220 during the FS and stored in the registers 209A to 209H, respectively.
Ch0, 2, 4 and 6 series data, and C
Data of Ch0, Ch2, Ch4, and Ch6 of the onf series are latched in registers 210A to 210H, respectively.

Here, the output data of eight systems are arranged in parallel. Thereafter, each of the registers 210A to 210A
By shifting 0H, parallel data is converted to serial data, and an output of serial audio data is obtained. From each of the registers 210A to 210H, serial audio is output in parallel.
This serial audio data is output in the first half of the 1FS cycle.

On the other hand, when the data stored in registers 209A to 209H is latched in registers 210A to 210H, the next data can be stored in registers 209A to 209H. 1/2 of the latter half of 1FS cycle from the timing of the sample top signal
Adv output from the audio processing unit 220 during the FS and stored in the registers 209A to 209H, respectively.
Ch1, 3, 5 and 7 data of the series and O
Data of Chs 1, 3, 5, and 7 of the nf series are latched in registers 210A to 210H, respectively. Each of the latched data is shifted in each register and converted into serial audio data in the same manner as described above. Each of the registers 210A to 210H outputs the converted serial audio data for 1FS.
It is arranged in the latter half of the cycle and output in parallel.

As shown in FIG. 36C, the AIF block 20 distributes the audio data of the paired channels in the first half and the second half of the 1FS cycle, and outputs the respective output systems in parallel. Thus, R
The audio data obtained by time-division multiplexing a plurality of channels in the C block 19 is processed in common by the AIF block 20 for each of the plurality of channels, separated from the time-division multiplex, and output for each output system.

In the above description, the present invention is applied to a digital V
Although described as applying to TR, this is not limited to this example. The present invention is also applicable to digital audio equipment that handles only audio data.

In the above description, processing is performed on data reproduced from a recording medium.
It is not limited to this example. That is, the present invention is applicable to other devices that handle digital audio data of a plurality of channels.

Further, the processing performed by the audio processing section 220 is not limited to the above-described processing. Further, the present invention can be applied not only to a reproducing system but also to a configuration of a recording system.

[0154]

As described above, according to the present invention, audio data of a plurality of channels is handled by time-division processing for each of a plurality of channels. Therefore, for example, mute processing, shuttle filter, data modification and tilt There is an effect that each audio processing for each of a plurality of channels, such as level control, can be shared by each channel.

Therefore, even when handling a plurality of channels, there is an effect that only one circuit is required for each processing.

Further, according to the embodiment of the present invention, since data of a plurality of channels is input in a time-division manner to an audio processing circuit which performs various processes on audio data, the number of wirings can be reduced. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration on a recording side according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a reproducing side according to an embodiment of the present invention.

FIG. 3 is a schematic diagram illustrating types of audio error correction blocks that can be supported by the recording / reproducing apparatus according to the embodiment;

FIG. 4 is a schematic diagram illustrating types of audio error correction blocks that can be supported by the recording and reproducing apparatus according to the embodiment;

FIG. 5 is a schematic diagram showing types of audio error correction blocks that can be supported by the recording and reproducing apparatus according to the embodiment;

FIG. 6 is a schematic diagram illustrating a structure of a sync block.

FIG. 7 is a schematic diagram showing bit assignment of ID and DID in a sync block.

FIG. 8 shows a frame (field) frequency of 29.97H.
FIG. 9 is a schematic diagram illustrating a layout of an error correction block for one channel and one field audio in the case of z, 59.94 Hz.

FIG. 9 shows a frame (field) frequency of 25 Hz / 5.
FIG. 4 is a schematic diagram illustrating a layout of an audio error correction block in the case of 0 Hz.

FIG. 10 is a schematic diagram showing a layout of an audio error correction block when the frame frequency is 23.976 Hz.

FIG. 11 is a schematic diagram illustrating an example of channel allocation on a footprint in a format SD1.

FIG. 12 is a schematic diagram illustrating an example of channel allocation on a footprint in a format SD2.

FIG. 13 is a schematic diagram illustrating an example of channel allocation on a footprint in a format SD3.

FIG. 14 is a schematic diagram illustrating an example of channel allocation on a footprint in a format SD4.

FIG. 15 is a schematic diagram illustrating audio code number allocation in each format.

FIG. 16 is a block diagram showing an example of a configuration of an audio decoder according to the present invention.

FIG. 17 is a schematic diagram for explaining address assignment of an SDRAM.

FIG. 18 is a schematic diagram illustrating address assignment of an SDRAM.

FIG. 19 is a schematic diagram illustrating address assignment of an SDRAM.

FIG. 20 is a schematic diagram for explaining processing in a channel deshuffling RAM.

FIG. 21 is a schematic diagram for explaining a method for obtaining a sector number within a track.

FIG. 22 is a schematic diagram illustrating an example of bit allocation of a sector number within a track and an SEG number supplied to a channel deshuffling RAM.

FIG. 23 is a schematic diagram for explaining processing in a sink deshuffling RAM.

FIG. 24 is a schematic diagram showing bit assignments of a sector number within a channel field, an azimuth number, a sync number within a sector, and an outer code number in each format.

FIG. 25 is a schematic diagram showing a more specific example of obtaining an outer code number.

FIG. 26 is a schematic diagram showing a more specific example of obtaining an outer code number.

FIG. 27 is a timing chart of audio processing in the AOT block.

FIG. 28 is a schematic diagram illustrating writing and reading of pass numbers.

FIG. 29 is a schematic diagram illustrating an example of an address assignment of an outer code RAM;

FIG. 30 is a schematic diagram illustrating an example of an address assignment of a rate conversion RAM;

FIG. 31 is a schematic diagram schematically showing a time division process of data transmission from an RC block to an AIF block.

FIG. 32 is a block diagram showing an example of a configuration of an AIF block according to the present invention.

FIG. 33 is a schematic diagram for schematically explaining each processing of data modification, simple mute, and shuttle filter.

FIG. 34 is a schematic diagram for explaining a tilt level control process.

FIG. 35 is a block diagram conceptually showing an example of the configuration of an AIF block according to the present invention.

FIG. 36 is a time chart showing processing in the AIF block.

[Explanation of symbols]

1 ... Decoder, 11 ... Deshuffling part, 1
3: SDRAM, 14: RAM for channel deshuffling, 15: RA for sink deshuffling
M, 16 ... AOT block, 17A, 17B ...
RAM for outer code, 18A to 18H: RAM for rate conversion, 19: RC block, 20: AI
.. F block, 133... Inner code decoder, 124.
.ID interpolation circuit, 151... Deshuffling circuit, 1
52: outer code decoder, 201: delay circuit, 202: selector control circuit, 203: hold register unit, 204: average value circuit, 205 ...
.Average value circuit, 206... Gradient level control circuit, 20
8 ... selector, 209 ... register group, 210-
..P / S register group, 220 ... Audio processing unit

Claims (5)

[Claims] 1. An audio signal processing device adapted to handle digital audio data of a plurality of channels, a time division multiplexing means for time division multiplexing and transmitting the audio data of a plurality of channels, Signal processing means for receiving the input audio data and performing predetermined processing on the input audio data for each channel, and holding data required for the predetermined processing by the signal processing means for each channel An audio signal processing device comprising: a data holding unit that outputs the audio data processed for each of the channels by the signal processing unit. 2. The audio signal processing device according to claim 1, wherein the data holding unit holds the audio data and information indicating an error in the audio data for each of the channels. Processing equipment. 3. The audio signal processing device according to claim 1, wherein the plurality of channels are configured by a plurality of pairs in which channels having a common output system are paired with each other, and the time division multiplexing unit includes: An audio signal processing apparatus, wherein each of the channels forming the pair is transmitted at intervals of a half of a period in which the plurality of channels are transmitted. 4. The audio signal processing device according to claim 1, wherein the output control means includes a plurality of buffer means corresponding to a plurality of output systems, and outputs the audio data output from the signal processing means. An audio signal processing device, wherein the audio signal is stored in the buffer means corresponding to the audio data output system among the plurality of buffer means. 5. A video / audio recording / reproducing apparatus which records digital video data and digital audio data of a plurality of channels together on a recording medium and reproduces the digital video data and the digital audio data of a plurality of channels from the recording medium. Recording means for performing error correction encoding using a product code on input video data and audio data of a plurality of channels, adding ID information and a synchronization signal to a recording medium, and The video data and the audio data of the plurality of channels recorded on the medium are reproduced, and the reproduced video data and the audio data of the plurality of channels are subjected to the error by the product code based on the synchronization signal and the ID information, respectively. Correction encoding decoding Reproducing means; time-division multiplexing means for transmitting the audio data of a plurality of channels reproduced by the reproducing means in a time-division multiplexing manner; and the audio data multiplexed by the time-division multiplexing means are inputted and inputted. Signal processing means for performing predetermined processing on the audio data for each channel, data holding means for holding data necessary for the predetermined processing by the signal processing means for each channel, and signal processing means Output control means for outputting the audio data processed for each of the channels.