JPH06232341A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the occupation areas of MIS capacitances and to lessen the absolute value of the parasitic capacitance of each terminal by a method wherein a plurality of the MIS capacitors are installed in the same low- concentration N-type epitaxial layer and the side of metal layers are used as terminals. CONSTITUTION:A semiconductor device is provided with a high-concentration N-type impurity diffused layer 3 provided in a low-concentration N-type epitaxial layer 5, an insulating film 2 at least provided on the upper part of the layer 3 and two metal layers 1, which are provided on the upper part of the film 2 and are selectively provided within the upper region of the layer 3. A parasitic junction capacitor C3 is connected to a parasitic resistor R1 between MIS capacitances C1 and C2, which are series-connected to each other, and a diode D is equivalently connected to the capacitor C3. The two MIS capacitors, terminals on the diffusion sides of which are made equipotential to each other, are installed in the same layer 5 and the occupation areas of the MIS capacitor can be reduced. Moreover, parasitic capacitances, which are attached to terminals of the layers 1, are equal and the absolute value of the parasitic capacitance of each terminal can be made small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a plurality of MISs (Metal Insulator Se).
The present invention relates to a semiconductor device including a capacitor.

[0002]

2. Description of the Related Art Conventionally, when it is necessary to connect a MIS capacitor between specific terminals and make the parasitic capacitances of the respective terminals equal to each other in terms of circuit characteristics, the MIS capacitors are connected in series and the direction of the terminals of the MIS capacitor is changed. It was connected in the opposite direction.

FIG. 5 is a sectional view showing an example of such a conventional semiconductor device, and FIG. 6 is a plan view of the device shown in FIG. Figure 5
Is a sectional view taken along the line AA 'in FIG.

5 and 6, the high-concentration N-type impurity diffusion layer 3 provided in the low-concentration N-type epitaxial layer 5 is formed.
And an insulating film 2 provided at least above the high-concentration N-type impurity diffusion layer 3, and selectively provided above the insulating film 2 and in an upper region of the high-concentration N-type impurity diffusion layer 3. A contact hole 7 is formed in the insulating film 2 and two MIS capacitors composed of the metal layer 1 connected to the high-concentration N-type impurity diffusion layer 3 are arranged. As shown in FIG. The metal layers 1 selectively provided on the above were connected to each other by the metal wiring layer 6, and the MIS capacitors were connected in series.

FIG. 7 is an equivalent circuit of the conventional example shown in FIGS. Parasitic junction capacitors C3 and C4 are connected to the series connection of the MIS capacitors C1 and C2 and the parasitic resistors R1 and R2 between the terminals, respectively. A diode D is equivalently connected to each of the capacitors C3 and C4.

[0006]

In the conventional semiconductor device described above, the MIS capacitors are connected in series, so that the occupied area of the MIS capacitors becomes large in order to make the capacitance value necessary for the circuit characteristics. There was a point.

An object of the present invention is to solve the above problems and to provide a semiconductor device capable of reducing the occupied area of the MIS capacitor by installing a plurality of MIS capacitors in the same low concentration N type epitaxial layer. To provide.

[0008]

A first semiconductor device according to the present invention has a high concentration one conductivity type impurity diffusion layer provided in a low concentration one conductivity type epitaxial layer, and a high concentration one conductivity type impurity diffusion layer. In a semiconductor device including a capacitor having an insulating film provided on a layer and a metal layer selectively provided on the insulating film and in an upper region of the high concentration one conductivity type impurity diffusion layer A plurality of the metal layers are electrically isolated from each other.

According to a second semiconductor device of the present invention, a high concentration one conductivity type impurity diffusion layer provided in a low concentration one conductivity type epitaxial layer and an upper portion of the high concentration one conductivity type impurity diffusion layer are provided. And a plurality of metal layers selectively provided in the upper region of the high-concentration one-conductivity-type impurity diffusion layer above the insulating film. It is characterized in that it is connected between the collectors of the transistors.

[0010]

The present invention will be described below with reference to the drawings. 1 is a sectional view showing a semiconductor device (line AA 'in FIG. 2) of the first embodiment of the present invention, and FIG. 2 is a plan view showing the first embodiment of the present invention.

In FIGS. 1 and 2, the high concentration N type impurity diffusion layer 3 provided in the low concentration N type epitaxial layer 5 is formed.
And an insulating film 2 provided at least above the high-concentration N-type impurity diffusion layer 3, and selectively provided above the insulating film 2 and in an upper region of the high-concentration N-type impurity diffusion layer 3. It has two metal layers 1.

FIG. 3 is an equivalent circuit diagram of the first embodiment of the present invention. In FIG. 3, the parasitic junction capacitance C3 is connected to the parasitic resistance R1 between the series connection of the MIS capacitors C1 and C2. The diode D is equivalently connected to the capacitor C3.

With such a structure, two MIS capacitors whose terminals on the diffusion side of MIS capacitors have the same potential are installed in the same low-concentration N-type epitaxial layer 5 and parasitic capacitances attached to the terminals of each metal layer. Thus, it is possible to provide a semiconductor device having the same absolute value and a small absolute value.

FIG. 4 is a circuit diagram showing a differential amplifier including the semiconductor device according to the first embodiment of the present invention. In the differential amplifier circuit of FIG. 4, the capacitive element C1 of this embodiment is used as a low pass filter for removing high frequency signals. In this case, it is necessary to equalize the parasitic capacitance values attached to the output terminals of the differential amplifier due to the circuit characteristics.

In FIG. 4, the present differential amplifier includes transistors Q1 to Q4, resistors R1, R2 and R3, the capacitive element C1 of this embodiment, a pair of input terminals, and a pair of output terminals. ing.

[0016]

As described above, in the semiconductor device of the present invention, the MIS capacitors are connected in series in order to connect the MIS capacitors between the specific terminals and make the parasitic capacitances of the terminals equal to each other in terms of circuit characteristics. In addition, when it is necessary to connect the terminals of the MIS capacitors in opposite directions, a plurality of MIS capacitors are installed in the same low-concentration N-type epitaxial layer, and the metal layer side is used as a terminal. This has the effects of reducing the occupied area of the MIS capacitance and reducing the absolute value of the parasitic capacitance of each terminal.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram of the semiconductor device according to the first exemplary embodiment of the present invention.

FIG. 4 is a circuit diagram showing a differential amplifier including a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a sectional view showing a conventional semiconductor device.

FIG. 6 is a plan view showing a conventional semiconductor device.

FIG. 7 is an equivalent circuit diagram of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Metal layer 2 Insulating film 3 High concentration N type impurity diffusion layer 4 P type impurity isolation region 5 Low concentration N type epitaxial layer 6 Metal wiring layer 7 Contact hole

Claims (2)

[Claims] 1. A high concentration one conductivity type impurity diffusion layer provided in a low concentration one conductivity type epitaxial layer, an insulating film provided on the high concentration one conductivity type impurity diffusion layer, and an upper portion of the insulating film. In a semiconductor device having a capacitor having a metal layer selectively provided in an upper region of the high concentration one conductivity type impurity diffusion layer, a plurality of metal layers are formed in an electrically isolated state. A semiconductor device characterized in that. 2. A high-concentration one-conductive type impurity diffusion layer provided in a low-concentration one-conductive type epitaxial layer, an insulating film provided on the high-concentration one-conductive type impurity diffusion layer, and an upper part of the insulating film. A capacitor having a plurality of metal layers selectively provided in an upper region of the high concentration one conductivity type impurity diffusion layer is connected between collectors of a pair of transistors forming a differential amplifier. A semiconductor device characterized by: