KR920010596B1 - Leteral pnp transistor using latch up of the npn transistor for promoting static electricity resisting - Google Patents

Leteral pnp transistor using latch up of the npn transistor for promoting static electricity resisting Download PDF

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KR920010596B1
KR920010596B1 KR1019890018743A KR890018743A KR920010596B1 KR 920010596 B1 KR920010596 B1 KR 920010596B1 KR 1019890018743 A KR1019890018743 A KR 1019890018743A KR 890018743 A KR890018743 A KR 890018743A KR 920010596 B1 KR920010596 B1 KR 920010596B1
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emitter
collector
transistor
pnp transistor
base
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KR1019890018743A
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KR910013586A (en
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이호진
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삼성전자 주식회사
김광호
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Priority to TW079110351A priority patent/TW198136B/zh
Priority to DE4040070A priority patent/DE4040070C2/en
Priority to JP2402505A priority patent/JP2597753B2/en
Priority to CN90109971A priority patent/CN1020027C/en
Publication of KR910013586A publication Critical patent/KR910013586A/en
Priority to US07/860,271 priority patent/US5237198A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0821—Combination of lateral and vertical transistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/735—Lateral transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/52—Circuit arrangements for protecting such amplifiers

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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Integrated Circuits (AREA)
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Abstract

The lateral PNP transistor for using the latch voltage of an NPN transistor to protect the transistor against the static electricity comprises an N-plus buried layer (11) and a n-minus epitaxial layer (12) formed on a P substrate (10), a P-plus isolation layer (16) for isolating between devices, an emitter (13) and a collector (14) formed by diffusing P impurities into the layer (12), a base (15) formed by diffusing n-plus impurities into the layer (12), an N-plus diffusion layer (20,21) formed into the emitter or collector, and emitter, collector and base electrodes (13',14',15'). The breakdown voltage of the PNP transistor is dependent upon the blocking voltage (collector to emitter) of the NPN transistor.

Description

NPN 트랜지스터의 래치전압을 이용한 정전내력향상 래터럴 PNP 트랜지스터Lateral Capacity Improvement Lateral PNP Transistor Using Latch Voltage of NPN Transistor

제1도는 종래의 레터럴 PNP 트랜지스터의 수평 및 수직구조도.1 is a horizontal and vertical structure diagram of a conventional lateral PNP transistor.

제2도는 본 발명의 제1실시예에 따른 레터널 PNP 트랜지스터의 수평 및 수직구조도.2 is a horizontal and vertical structure diagram of a letter-shaped PNP transistor according to a first embodiment of the present invention.

제3도는 본 발명의 또 다른 실시예에 따른 레터럴 PNP 트랜지스터의 수평 및 수직구조도.3 is a horizontal and vertical structure diagram of a lateral PNP transistor according to another embodiment of the present invention.

제4a도는 제2도의 등가회로, (b)는 제3도의 등가회로.FIG. 4a is an equivalent circuit of FIG. 2, and (b) is an equivalent circuit of FIG.

제5도는 일반적인 오피앰프의 입력단에 본 발명의 제4a도를 적용한 회로구성예.5 is a circuit configuration example in which FIG. 4a of the present invention is applied to an input terminal of a general op amp.

본 발명은 NPN 트랜지스터의 래치전압을 이용한 래터럴 PNP 트랜지스터에 관한 것으로, 특히 PNP 트랜지스터의 에미터 또는 콜렉터에 고농도의 n형 확산층을 형성함으로써 PNP 트랜지스터의 베이스에 정전기가 인가될 때에 콜렉터와 에미터 사이의 래치전압을 이용하여 정전기를 방전시켜 정전내력을 향상시킨 NPN 트랜지스터의 래치전압을 이용한 정전내력향상 래터럴 PNP 트랜지스터에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lateral PNP transistor using a latch voltage of an NPN transistor. In particular, a high concentration of n-type diffusion layer is formed on an emitter or a collector of a PNP transistor, so that when a static electricity is applied to the base of the PNP transistor, The present invention relates to a lateral PNP transistor using an latch voltage of an NPN transistor in which static electricity is discharged by using a latch voltage to improve electrostatic resistance.

종래의 래터럴 PNP 트랜지스터는 제1도에 도시한 바와 같이 P-기판상(10)에 n+매몰층(11), n-에피택셜층(12)을 차례로 적층한 후, 상기 n-에피택셜층(12)의 소정영역에 P형의 불순물을 확산시켜 분리층(16)을 형성하고, n에피텍셜층(12) 표면의 소정영역에 P형의 불순물을 확신시켜 에미터(13) 및 콜렉터(14)를 형성하며, 고농도의 n형 불순물을 확산시켜 베이스(15)를 형성한 후, 이들 각 단자는 통상의 콘택공정을 통하여 에미터전극(13´), 콜렉터전극(14´) 및 베이스전극(15´)이 형성된다.After sequentially stacked the epitaxial layer 12, the n - - conventional lateral PNP transistor is P as shown in FIG. 1 - n + buried layer (11), n in the substrate 10 the epitaxial layer P-type impurities are diffused into predetermined regions of (12) to form separation layer 16, and P-type impurities are assured in predetermined regions of n epitaxial layer 12 surface to emitter 13 and collector ( 14), and the high concentration of n-type impurities are diffused to form the base 15, and then each of these terminals is subjected to an emitter electrode 13 ', collector electrode 14', and base electrode through a conventional contact process. (15 ') is formed.

상기 구조를 갖는 종래 래터럴 PNP 트랜지스터의 베이스(15)에 정전기가 인가되면 베이스(15)와 콜렉터(14) 사이 또는 베이스(15)와 에미터(13) 사이에 방전로(path)가 형성되게 된다.When static electricity is applied to the base 15 of the conventional lateral PNP transistor having the above structure, a discharge path is formed between the base 15 and the collector 14 or between the base 15 and the emitter 13. .

한편, 방전로를 형성하는 항복전압이 높으면 낮은 정전기 전압에서도 소자가 파괴된다는 것은 주지의 사실이다. 그런데, 베이스(15)와 콜렉터(14)간의 항복전압(BVCBO)과 베이스(15)와 에미터(13)간에는 높은 항복전압(BVEBO)이 형성되므로 낮은 정전기 전압에서도 소자가 파괴되게 된다.On the other hand, it is well known that when the breakdown voltage forming the discharge path is high, the device is destroyed even at a low static voltage. However, since the breakdown voltage BV CBO between the base 15 and the collector 14 and the high breakdown voltage BV EBO are formed between the base 15 and the emitter 13, the device is destroyed even at a low electrostatic voltage.

종래에는 PNP 트랜지스터의 정전기 특성을 개선하기 위하여 SCR(Silicon Controlled Rectifier)을 이용하는 방법과 베이스가 개방된 에미터 공통 트랜지스터의 항복전압인 전압(BVCEO)을 이용하는 방법이 많이 이용되어지고 있다. 그러나 SCR을 이용한 정전기 개선 방법은 정전기 특성은 향상되지만 정전기 보호패턴에 의하여 정전용량(capacitance) 값이 증가하는 문제가 있다.Conventionally, a method using a silicon controlled rectifier (SCR) and a voltage (BV CEO ), which is a breakdown voltage of an emitter common transistor having a base open, have been widely used to improve the electrostatic characteristics of a PNP transistor. However, in the static electricity improving method using SCR, the static electricity characteristics are improved, but the capacitance value is increased due to the static electricity protection pattern.

따라서, 본 발명은 종래 PNP 트랜지스터가 갖는 제반문제점을 감안하여 제안된 것으로 정전기 방전로(path)가 형성될 때 낮은 전압에서 항복전압(Breakdown Voltage)이 형성되면 정전내력이 향상된다는 점에 착안하여 래터럴 PNP 트랜지스터의 베이스와 콜렉터간의 항복전압(BVCBO)과, 베이스 에미터간의 항복전압(BVEBO)을 PNP 트랜지스터의 에미터와 콜렉터간의 래치전압(LVCEO)으로 바꾸어 줌으로써 정전내력을 향상시킬 수 있는 래터럴 PNP 트랜지스터를 제공하는데 그 목적이 있다.Accordingly, the present invention has been proposed in view of the general problems of the conventional PNP transistor, and the lateral strength is improved when the breakdown voltage is formed at a low voltage when an electrostatic discharge path is formed. By changing the breakdown voltage (BV CBO ) between the base and the collector of the PNP transistor and the breakdown voltage (BV EBO ) between the base emitter and the latch voltage (LV CEO ) between the emitter and the collector of the PNP transistor, the electrostatic capacity can be improved. The purpose is to provide a lateral PNP transistor.

상기 목적을 달성하기 위한 본 발명은 종래의 래터럴 PNP 트랜지스터의 에미터나 콜렉터 영역내에 별도의 고농도 n형 확산층이 형성된 구조로 이루어짐을 특징으로 한다.The present invention for achieving the above object is characterized by consisting of a structure in which a separate high concentration n-type diffusion layer is formed in the emitter or collector region of the conventional lateral PNP transistor.

이하 도면을 참조하여 본원 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제2도는 본 발명에 의한 래터럴 PNP 트랜지스터의 제1실시예로 고농도의 n형 확산층을 콜렉터영역에 형성한 경우를 도시한 것으로, 상부도면을 수평구조도, 하부도면은 수직구조도를 각각 나타낸다.FIG. 2 shows a case where a high concentration n-type diffusion layer is formed in a collector region in the first embodiment of the lateral PNP transistor according to the present invention. The upper figure shows a horizontal structure diagram and the lower figure shows a vertical structure diagram.

종래의 PNP 트랜지스터와 동일하게, P-기판(10)상에 n+매몰층(11), n-에피택셜층(12)을 차례로 형성하고, 각 소자간 분리를 위한 p+분리층(16)을 에피택셜층(12)의 소정영역에 형성하고, n-에피택셜층(12)내에 P형의 불순물을 확산시켜 에미터(13) 및 콜렉터(14)를 형성하며, 고농도의 n형 불순물을 확산시켜 베이스(15)를 각각 형성한 다음 P형 콜렉터(14)의 소정영역에 고농도의 n형 불순물을 확산시켜 n+확산층(20)을 형성하되, 상기 P형 콜렉터(14)와 n+확산층(20)이 콜렉터전극(14´)을 통하여 동시에 접촉되도록 한다.As in the conventional PNP transistor, an n + buried layer 11 and an n - epitaxial layer 12 are sequentially formed on the P − substrate 10, and the p + isolation layer 16 for separation between elements is formed. Is formed in a predetermined region of the epitaxial layer 12, P-type impurities are diffused in the n - epitaxial layer 12 to form the emitter 13 and the collector 14, and a high concentration of n-type impurities is formed. The base 15 is diffused to form each, and then a high concentration of n-type impurities are formed in a predetermined region of the P-type collector 14, thereby forming an n + diffusion layer 20, wherein the P-type collector 14 and n + diffusion layer are formed. 20 are brought into contact at the same time through the collector electrode 14 '.

이와 같은 구조를 갖는 래터럴 PNP 트랜지스터는 고농도의 n+확산층(20)으로 인하여 PNP 트랜지스터 내에 또 다른 NPN 트랜지스터를 갖는 구조를 이루게 된다.The lateral PNP transistor having such a structure has a structure having another NPN transistor in the PNP transistor due to the high concentration of n + diffusion layer 20.

제3도는 본 발명의 또 다른 실시예에 고농도의 n형 확산층을 에미터영역내에 형성한 경우이다. 제1실시예의 경우와 동일하게 P-기판(10), n+매몰층(11), n-에피택셜층(12)을 차례로 형성하고 소자간 분리를 위한 P+분리층(16)을 형성하며 n-에피택셜층(12)내에 P형 불순물을 확산시켜 에미터(13) 및 콜렉터(14)를 형성하고, 고농도의 n형 불순물을 확산시켜 베이스(15)를 각각 형성하고 난 후, P형 에미터(13)의 소정영역에 고농도의 n형 불순물을 확산시켜 n+확산층(21)을 형성하되, 상기 P형 에미터(13)와, n+확산층(21)이 에미터전극(13´)을 통하여 동시에 접촉되도록 한다.3 shows a case where a high concentration of n-type diffusion layer is formed in the emitter region according to another embodiment of the present invention. In the same manner as in the first embodiment, the P − substrate 10, the n + buried layer 11, the n − epitaxial layer 12 are sequentially formed, and the P + separation layer 16 is formed to separate devices. P-type impurities are diffused into the n - epitaxial layer 12 to form the emitter 13 and the collector 14, and high concentrations of n-type impurities are diffused to form the base 15, respectively. The n + diffusion layer 21 is formed by diffusing a high concentration of n-type impurities in a predetermined region of the emitter 13, wherein the P-type emitter 13 and the n + diffusion layer 21 form an emitter electrode 13 ′. To be contacted at the same time.

제4a도는 트랜지스터의 콜렉터 영역에 n+확산층을 형성한 제2도의 등가회로도로써, 트랜지스터(Q11)의 베이스 콜렉터에, 베이스와 에미터가 공통으로 된 트랜지스터(Q12)의 콜렉터와 에미터가 접속된다. 이때 트랜지스터(Q11)는 에미터(13), 콜렉터(14) 및 베이스(15) 영역에 의한 것이며 P형의 콜렉터(14)와 고농도의 n형 확산층(20)이 트랜지스터(Q11)의 콜렉터(14)에 공통으로 접속된다.FIG. 4A is an equivalent circuit diagram of FIG. 2 in which an n + diffusion layer is formed in a collector region of a transistor, in which a collector and emitter of transistor Q 12 having a common base and an emitter are used as a base collector of transistor Q 11 . Connected. In this case, the transistor Q 11 is formed by the emitter 13, the collector 14, and the base 15 region, and the P-type collector 14 and the high concentration n-type diffusion layer 20 are the collectors of the transistor Q 11 . It is connected to 14 in common.

제4b도는 트랜지스터의 에미터 영역에 n+확산층을 형성한 제3도의 등가회로도로, 트랜지스터(Q21)는 베이스와 에미터에, 베이스와 에미터가 공통으로 된 트랜지스터(Q22)의 콜렉터와 에미터가 접속된다. 제4a도와 동일하게 트랜지스터(Q21)의 에미터(13), 콜렉터(14) 및 베이스(15)에 의한 것이고, P형의 에미터(13)와 고농도의 n형 확산층(21)이 트랜지스터(Q21)의 에미터(13)에 공통으로 접속된다.4B is an equivalent circuit diagram of FIG. 3 in which an n + diffusion layer is formed in an emitter region of a transistor, in which transistor Q 21 is a base and emitter, and a collector of transistor Q 22 having a common base and emitter; The emitter is connected. As in FIG. 4A, the emitter 13, the collector 14, and the base 15 of the transistor Q 21 are formed by the P-type emitter 13 and the high concentration n-type diffusion layer 21. Q 21 ) is commonly connected to the emitter 13.

제5도는 제4a도의 등가회로를 기본구성으로 하는 차동증폭기의 일예를 도시한 회로도로, 오피앰프 입력단에 쓰이는 회로에 콜렉터 또는 베이스 영역내에 고농도의 n형 확산층을 갖는 본 발명에 의한 레터럴 PNP 트랜지스터를 기본구성(A)으로 하여 차동증폭기로 형성한 경우이다.5 is a circuit diagram showing an example of a differential amplifier having the equivalent circuit of FIG. Is a case where a differential amplifier is formed with the basic configuration (A).

오피앰프의 입력회로로 쓰이는 차동증폭기에서 트랜지스터(Q2,Q3)를 차동증폭기의 기본 트랜지스터로 하고, 트랜지스터(Q2,Q3)의 콜렉터와 베이스에는, 베이스와 에미터가 공통으로 된 트랜지스터(Q4,Q5)의 에미터와 콜렉터를 각각 접속한다.In the differential amplifier used as the input circuit of the op amp, the transistors (Q 2 and Q 3 ) are used as the basic transistors of the differential amplifier, and the transistor and the emitter of the transistors (Q 2 and Q 3 ) have a common base and emitter. Connect the emitter and collector of (Q 4 , Q 5 ), respectively.

상기 트랜지스터(Q2,Q3)의 콜렉터에는 베이스가 공통인 트랜지스터(Q6,Q7)의 콜렉터가 각각 접속된다.The collectors of transistors Q 6 and Q 7 having a common base are connected to the collectors of the transistors Q 2 and Q 3 , respectively.

트랜지스터(Q3)의 출력은 트랜지스터(Q8)의 베이스에 인가되어 트랜지스터(Q8)의 출력이 오피앰프에 제공된다.The output of the transistor (Q 3) is the output of the is applied to the base of the transistor (Q 8) transistor (Q 8) is provided to the operational amplifier.

상기 트랜지스터(Q2,Q3)와, 트랜지스터(Q3,Q5)는 차동증폭기를 이루며 제2도의 구조를 기준으로 설명한다.The transistors Q 2 and Q 3 and the transistors Q 3 and Q 5 form a differential amplifier and will be described based on the structure of FIG. 2.

트랜지스터(Q1)는 바이어스전압과 저항(R1)에 의해 차동앰프에 전류를 공급하고, 저항(R4)은 입력회로의 부하로 작용한다. 제2도의 구조와 같은 래터럴 PNP 트랜지스터의 베이스(15)와 콜렉터(14)에 정(+)의 정전기가 인가될 경우 종래의 래터럴 PNP 트랜지스터는 베이스와 콜렉터 사이로 방전로가 형성되는 반면에 본 발명에 의한 래터럴 PNP 트랜지스터는 제4a도에서와 같의 NPN 트랜지스터(Q12)의 에미터와 콜렉터간의 래치전압(LVCEO)으로 방전로가 형성된다.The transistor Q 1 supplies a current to the differential amplifier by the bias voltage and the resistor R 1 , and the resistor R 4 serves as a load of the input circuit. When positive (+) static electricity is applied to the base 15 and the collector 14 of the lateral PNP transistor as shown in FIG. 2, the conventional lateral PNP transistor has a discharge path formed between the base and the collector. The lateral PNP transistor is formed with a discharge path by the latch voltage LV CEO between the emitter and the collector of the NPN transistor Q 12 as shown in FIG. 4A.

한편, 래터럴 PNP 트랜지스터의 베이스와 콜렉터간 항복전압(BVCBO)은 NPN 트랜지스터의 에미터와 콜렉터의 래치전압(LVCEO)에 비하여 훨씬 큰 값을 갖게 되므로, PNP 트랜지스터(Q11)의 베이스와 콜렉터간 항복전압(BVCBO)으로 방전로가 형성되는 것에 비하여 NPN 트랜지스터(Q12)의 에미터와 콜렉터간 래치전압(LVCEO)으로 방전로가 형성되는 것이 정전내력이 높게 된다.On the other hand, since the breakdown voltage (BV CBO ) between the base and the collector of the lateral PNP transistor has a much larger value than the latch voltage (LV CEO ) of the emitter and collector of the NPN transistor, the base and the collector of the PNP transistor Q 11 . The discharge path is formed by the latch voltage LV CEO between the emitter and the collector of the NPN transistor Q 12 as compared with the discharge path formed by the inter breakdown voltage BV CBO .

따라서, 회로동작은 래터럴 PNP 트랜지스터로 동작하되 정전기 내력은 향상되는 새로운 래터럴 PNP 트랜지스터를 제공할 수 있다.Accordingly, the circuit operation can be provided as a lateral PNP transistor, but can provide a new lateral PNP transistor in which the static electricity resistance is improved.

제3도 및 제4b도의 에미터(13) 영역에 n+확산층(21)을 형성한 경우도 이와 동일한 원리이다.The same principle applies to the case where the n + diffusion layer 21 is formed in the emitter 13 region of FIGS. 3 and 4b.

이상과 같이 본 발명에 의한 래터럴 PNP 트랜지스터는 새로운 NPN 트랜지스터를 추가하지 않고 콜렉터 또는 에미터 영역에 n+확산층을 각각 형성하되 이 n+확산층과 콜렉터 또는 에미터 영역이 각각의 전극단자를 통해 공통으로 접속됨으로써 PNP 트랜지스터내에 NPN 트랜지스터를 용이하게 구현하여 PNP 트랜지스터의 정전내력을 향상시킬 수 있다.As described above, the lateral PNP transistor according to the present invention forms n + diffusion layers in the collector or emitter region without adding new NPN transistors, but the n + diffusion layer and the collector or emitter region are common through the respective electrode terminals. By being connected, the NPN transistor can be easily implemented in the PNP transistor, thereby improving the electrostatic capacity of the PNP transistor.

Claims (2)

P형 기판(10)상에 고농도의 n형 매몰층(11), 저농도의 n형 에피택셜층(12)을 차례로 형성하고, 상기 에피택셜층(12)의 소정영역에 각 소자간 분리를 위한 P+분리층(16)과, 상기 에피택셜층(12) 표면의 소정영역에 P형의 불순물을 확산시켜 에미터(13) 및 콜렉터(14)를 형성하며, 고농도의 n형 불순물을 확산시켜 베이스(15)를 형성하고, 상기 P형의 에미터(13) 또는 콜렉터(14)중 어느 하나의 소정영역에 고농도의 n형 불순물을 확산시켜 n+확산층(20,21)을 형성한 후 에미터전극(13′), 콜렉터전극(14´) 및 베이스전극(15´)을 접속시켜 된 구조로 PNP 트랜지스터의 항복전압을 NPN 트랜지스터의 래치전압으로 대치하여 정전내력을 향상시킨 래터럴 PNP 트랜지스터.A high concentration n-type buried layer 11 and a low concentration n-type epitaxial layer 12 are sequentially formed on the P-type substrate 10, and the elements are separated in a predetermined region of the epitaxial layer 12. P-type impurities are diffused into a P + separation layer 16 and a predetermined region on the surface of the epitaxial layer 12 to form an emitter 13 and a collector 14, and a high concentration of n-type impurities is diffused. After forming the base 15 and diffusing a high concentration of n-type impurities in any one of the P-type emitter 13 or the collector 14 to form n + diffusion layers 20, 21 A lateral PNP transistor in which a breakdown voltage of a PNP transistor is replaced with a latch voltage of an NPN transistor to improve the electrostatic resistance by connecting the terminator 13 ', the collector electrode 14', and the base electrode 15 '. 제1항에 있어서, 상기 n+확산층(20,21)은 에미터전극(13′) 또는 콜렉터전극(14´)을 통하여 에미터(13), 콜렉터(14)와 각각 동시에 접촉된 것을 특징으로 하는 래터럴 PNP 트랜지스터.The n + diffusion layers 20 and 21 are in contact with the emitter 13 and the collector 14 simultaneously through the emitter electrode 13 'or the collector electrode 14'. Lateral PNP transistor.
KR1019890018743A 1989-12-16 1989-12-16 Leteral pnp transistor using latch up of the npn transistor for promoting static electricity resisting KR920010596B1 (en)

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KR1019890018743A KR920010596B1 (en) 1989-12-16 1989-12-16 Leteral pnp transistor using latch up of the npn transistor for promoting static electricity resisting
TW079110351A TW198136B (en) 1989-12-16 1990-12-08
DE4040070A DE4040070C2 (en) 1989-12-16 1990-12-14 PNP transistor with a protective element to protect against static electricity
JP2402505A JP2597753B2 (en) 1989-12-16 1990-12-14 Lateral PNP transistor with improved electrostatic withstand voltage using latch voltage of NPN transistor
CN90109971A CN1020027C (en) 1989-12-16 1990-12-15 Lateral PNP Transistor using latch voltage of NPN transistor
US07/860,271 US5237198A (en) 1989-12-16 1992-04-01 Lateral PNP transistor using a latch voltage of NPN transistor

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