JPH06232323A - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPH06232323A JPH06232323A JP5015537A JP1553793A JPH06232323A JP H06232323 A JPH06232323 A JP H06232323A JP 5015537 A JP5015537 A JP 5015537A JP 1553793 A JP1553793 A JP 1553793A JP H06232323 A JPH06232323 A JP H06232323A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- common
- lead frame
- film
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置用のリードフ
レームに関する。FIELD OF THE INVENTION The present invention relates to a lead frame for a semiconductor device.
【０００２】[0002]
【従来の技術】図５はいわゆるＬＯＣ（Lead On Chip）
タイプのリードフレームを示す。このＬＯＣタイプのリ
ードフレーム１０では、密に配線された信号リード１１
の先端側に共通の電源リード、接地リード等となる共通
リード１２が形成され、絶縁シート１３を介して信号リ
ード１１上に搭載された半導体素子１４との間で前記信
号リード１１、共通リード１２がそれぞれワイヤ１５、
ワイヤ１６にて電気的に接続される構造となっている。
このＬＯＣタイプのリードフレームによれば、信号リー
ドと混在して設けていた複数の電源リード、または接地
リードに共通リードを利用しているので、それだけ信号
リード１１を多ピン化できるというメリットがある。2. Description of the Related Art FIG. 5 shows a so-called LOC (Lead On Chip).
The type of lead frame is shown. In this LOC type lead frame 10, signal leads 11 that are closely wired
A common lead 12 serving as a common power supply lead, a ground lead, and the like is formed on the tip side of the signal lead 11, and the common lead 12 is provided between the signal lead 11 and the semiconductor element 14 mounted on the signal lead 11 via an insulating sheet 13. Are the wires 15,
The structure is such that they are electrically connected by wires 16.
According to this LOC type lead frame, the common lead is used for the plurality of power supply leads or the ground lead which are provided in a mixed manner with the signal lead, and therefore, there is an advantage that the signal lead 11 can have a large number of pins. .
【０００３】[0003]
【発明が解決しようとする課題】ところで、上記のよう
にＬＯＣタイプのリードフレームでは、その構造上必然
的に半導体素子１４と信号リード１１とを接続するワイ
ヤ１５が共通リード１２を跨いで接続される。この場合
に、ワイヤ１５と共通リード１２との接触を防止するた
め、ワイヤ１５のループをある程度大きくしなければな
らないが、ワイヤ１５のループを大きくすると隣接する
ワイヤ１５間でのショートが発生しやすく、また樹脂モ
ールドした際のモールド部が厚くなり、半導体装置全体
が大きくなってしまうという問題点がある。By the way, in the LOC type lead frame as described above, the wire 15 for connecting the semiconductor element 14 and the signal lead 11 is inevitably connected across the common lead 12 due to its structure. It In this case, in order to prevent the contact between the wire 15 and the common lead 12, the loop of the wire 15 has to be enlarged to some extent. However, if the loop of the wire 15 is enlarged, a short circuit between adjacent wires 15 easily occurs. In addition, there is a problem that the molded portion becomes thicker when it is resin-molded and the entire semiconductor device becomes larger.
【０００４】そこで、本発明は上記問題点を解決すべく
なされたものであり、その目的とするところは、隣接す
るワイヤ間のショートが防止でき、また半導体装置とし
た際の装置全体の小型化が可能となるリードフレームを
提供するにある。Therefore, the present invention has been made to solve the above problems, and an object thereof is to prevent a short circuit between adjacent wires and to reduce the size of the entire semiconductor device. To provide a lead frame that enables
【０００５】[0005]
【課題を解決するための手段】本発明は上記目的を達成
するため次の構成を備える。すなわち、ＬＯＣタイプあ
るいはＣＯＬタイプのリードフレームのように、信号リ
ードの先端側に電源ライン、接地ライン等の共通リード
が配置され、搭載される半導体素子と前記信号リードと
が前記共通リードを跨いでワイヤにより接続されるリー
ドフレームにおいて、少なくとも前記半導体素子との接
続部位を除く前記共通リード上に前記ワイヤとの短絡防
止用の絶縁皮膜が形成されていることを特徴としてい
る。前記絶縁皮膜は、Al、Si、Ti、Zr、Taの酸化皮膜も
しくは窒化皮膜、またはポリイミド、エポキシ樹脂等の
絶縁性耐熱性高分子膜から選択すると好適である。The present invention has the following constitution in order to achieve the above object. That is, like a LOC type or COL type lead frame, common leads such as a power supply line and a ground line are arranged on the tip side of the signal leads, and the mounted semiconductor element and the signal leads straddle the common leads. In a lead frame connected by a wire, an insulating film for preventing a short circuit with the wire is formed on the common lead except at least a connection portion with the semiconductor element. The insulating film is preferably selected from an oxide film or a nitride film of Al, Si, Ti, Zr or Ta, or an insulating heat resistant polymer film such as polyimide or epoxy resin.
【０００６】[0006]
【作用】本発明に係るリードフレームによれば、少なく
とも共通リードの半導体素子との接続部位を除く部位に
絶縁皮膜を形成したので、共通リードと半導体素子との
間の電気的接続にはなんら支承がなく、また共通リード
を跨ぐワイヤとの間のショートを好適に防止でき、さら
には該ワイヤのループをそれほど大きくしなくてもよい
から、隣接するワイヤ間でのショートも防止でき、さら
には樹脂封止した際のモールド部が厚くならず、半導体
装置全体の小型化が図れる。According to the lead frame of the present invention, since the insulating film is formed at least on the part of the common lead other than the connection part with the semiconductor element, no support is provided for the electrical connection between the common lead and the semiconductor element. In addition, a short circuit between the wires straddling the common lead can be preferably prevented, and since the loop of the wire does not need to be so large, a short circuit between adjacent wires can also be prevented, and further, the resin can be prevented. The molded portion does not become thick when sealed, and the overall size of the semiconductor device can be reduced.
【０００７】[0007]
【実施例】以下、本発明の好適な実施例を添付図面に基
づいて詳細に説明する。図１はＬＯＣタイプのリードフ
レームを示し、前記と同一部材は同一符合をもって示
す。本発明では共通リード１２上に半導体素子１４との
ワイヤボンディング部を除いて絶縁皮膜１８を形成する
のである。絶縁皮膜１８は、Al、Si、Ti、Zr、Taの酸化
皮膜もしくは窒化皮膜、またはポリイミド、エポキシ樹
脂等の絶縁性耐熱高分子膜が好適である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 shows a LOC type lead frame, and the same members as those described above are designated by the same reference numerals. In the present invention, the insulating film 18 is formed on the common lead 12 except for the wire bonding portion with the semiconductor element 14. The insulating film 18 is preferably an oxide film or a nitride film of Al, Si, Ti, Zr, Ta, or an insulating heat-resistant polymer film such as polyimide or epoxy resin.
【０００８】Al、Si、Ti、Zr、もしくはTaの酸化皮膜は
次のようにして形成するのがよい。 陽極酸化法 Ｃｕ材、鉄−ニッケル合金材等からなるリードフレーム
の共通リード１２上にTa膜をスパッタあるいは蒸着によ
り形成する。Ta膜は3000Å程度の厚さでよい。共通リー
ド１２の半導体素子とのワイヤによる接続部位およびTa
膜のない部位にレジストを塗布し、陽極酸化処理を行
う。これにより半導体素子との接続部位を除く共通リー
ド１２上にTa2O5 の酸化膜が形成される。なお信号リー
ド１１の半導体素子との接続部位（インナーリード）に
あらかじめ銀めっき皮膜などを形成しておくこともでき
る。 熱酸化法 共通リード１２上に上記と同様にしてTa膜を形成し、必
要部以外の膜を除去した後、炉中で加熱処理し、Ta2O5
の酸化膜を形成する。Al、Si、Ti、Zrの酸化皮膜も上記
、と同様にして形成できる。The Al, Si, Ti, Zr, or Ta oxide film is preferably formed as follows. Anodizing Method A Ta film is formed on the common lead 12 of the lead frame made of Cu material, iron-nickel alloy material or the like by sputtering or vapor deposition. The Ta film may have a thickness of about 3000Å. Connection part of the common lead 12 with the semiconductor element by a wire and Ta
A resist is applied to the part without the film and anodization is performed. As a result, an oxide film of Ta 2 O 5 is formed on the common lead 12 excluding the connection part with the semiconductor element. It is also possible to previously form a silver plating film or the like on the connection portion (inner lead) of the signal lead 11 with the semiconductor element. Thermal Oxidation Method A Ta film is formed on the common lead 12 in the same manner as above, and after removing the film other than the necessary part, heat treatment is performed in a furnace to form Ta 2 O 5
Forming an oxide film. An oxide film of Al, Si, Ti, Zr can be formed in the same manner as above.
【０００９】Al、Si、Zr、Ti、Taの酸化皮膜もしくは窒
化皮膜は、リードフレームに所定のマスクをして、反応
性スパッタ、反応性蒸着、イオンプレーティングなどの
気相法により形成することもできる。膜厚は2000Å程度
でもよい。The oxide film or nitride film of Al, Si, Zr, Ti, Ta should be formed by a vapor phase method such as reactive sputtering, reactive vapor deposition, ion plating, etc. with a predetermined mask on the lead frame. You can also The film thickness may be about 2000Å.
【００１０】ポリイミド、エポキシ樹脂等の絶縁性耐熱
高分子膜は、これら樹脂をスクリーン印刷等により所定
のパターンに塗布し、キュアーすることにより容易に形
成できる。The insulating heat-resistant polymer film of polyimide, epoxy resin or the like can be easily formed by coating these resins in a predetermined pattern by screen printing or the like and curing.
【００１１】共通リード１２上にAlの酸化膜を形成する
際、同時に信号リード１１の先端にAl皮膜を形成するよ
うにすると好適である。この場合のリードフレームの形
成法としては、金属帯材の中央部分にAl箔をクラッドし
たAlクラッド材、あるいは該中央部分に蒸着などでAl皮
膜を形成した金属帯材を用いてプレス加工によりリード
フレームの形状加工をし、前記と同様にしてレジストに
より不必要部分を被覆して陽極酸化を行って、共通リー
ド１２上のAl皮膜の必要部分のみを酸化させ、共通リー
ド１２上にはAlの酸化皮膜１８を、信号リード１１上に
はAl皮膜１９を形成したリードフレームを得ることがで
きる（図２）。このように信号リード１１の先端にAl皮
膜１９が形成されることで、信号リード１１と半導体素
子を接続するワイヤ１５がAl線のときのボンディングを
容易に行うことができる。また上記のようにAl皮膜があ
らかじめ形成された金属帯材をプレス加工によりリード
フレームの形状加工をすると、図３に示すように共通リ
ード１２の肩部にダレが生じ、Al皮膜が共通リード１２
の側面まである程度付着する。したがって上記のごとく
酸化処理をすることで、側面の肩部までAlの酸化皮膜１
８が形成されたリードフレームが得られ、ワイヤ１５と
共通リード１２との間のショートを効果的に防止でき
る。When the Al oxide film is formed on the common lead 12, it is preferable to simultaneously form the Al film on the tip of the signal lead 11. In this case, the lead frame is formed by press working using an Al clad material in which an Al foil is clad in the central portion of the metal strip material, or a metal strip material in which an Al film is formed on the central portion by vapor deposition or the like. The frame is shaped, and unnecessary portions are covered with resist in the same manner as described above and anodization is performed to oxidize only the necessary portions of the Al film on the common leads 12 and Al on the common leads 12 is removed. A lead frame having the oxide film 18 and the Al film 19 on the signal lead 11 can be obtained (FIG. 2). By forming the Al film 19 on the tip of the signal lead 11 in this way, bonding can be easily performed when the wire 15 connecting the signal lead 11 and the semiconductor element is an Al wire. When the metal strip material on which the Al coating is previously formed as described above is subjected to press working to shape the lead frame, sagging occurs on the shoulder portion of the common lead 12 as shown in FIG.
Adhere to some extent to the side of. Therefore, by performing the oxidation treatment as described above, the Al oxide film 1 up to the side shoulders
A lead frame in which 8 is formed can be obtained, and a short circuit between the wire 15 and the common lead 12 can be effectively prevented.
【００１２】なお、リードフレームの形状の加工を行っ
た後に、スパッタあるいは蒸着等で共通リード１２およ
び信号リード１１の先端にAl皮膜を形成し、上記と同様
にして共通リード１２のAl皮膜の必要部分のみを酸化処
理するようにしてもよい。After processing the shape of the lead frame, an Al film is formed on the tips of the common lead 12 and the signal lead 11 by sputtering or vapor deposition, and the Al film of the common lead 12 is required in the same manner as above. You may make it oxidize only a part.
【００１３】図４はリードフレームの他の実施例を示
す。本実施例ではＣＯＬ（Chip On Lead）タイプのリー
ドフレームを示す。ＣＯＬタイプのリードフレームで
は、信号リード１１上に絶縁シート１３を介して半導体
素子１４が搭載されるようになっている。本実施例で
は、信号リード１１とは別個に枠状の電源リード、接地
リード等の共通リード１２を形成し、共通リード１２を
絶縁シート１３上に貼着して固定するようにしている。
共通リード１２の周縁からは舌片（図示せず）が延出さ
れ、該舌片が信号リード１１間に形成された電源ライ
ン、接地ライン等に接続されている。そして信号リード
１１と半導体素子１４とはワイヤ１５により接続され、
共通リード１２と半導体素子１４とがワイヤ１６により
接続される。この本実施例においても、前記と同様な方
法により共通リード１２上のワイヤボンディング部位以
外の部位に絶縁皮膜１８が形成されている。これにより
ワイヤ１５と共通リード１２との間のショートを防止で
きる。FIG. 4 shows another embodiment of the lead frame. In this embodiment, a COL (Chip On Lead) type lead frame is shown. In the COL type lead frame, the semiconductor element 14 is mounted on the signal lead 11 via the insulating sheet 13. In this embodiment, a common lead 12 such as a frame-shaped power supply lead and a ground lead is formed separately from the signal lead 11, and the common lead 12 is attached and fixed on the insulating sheet 13.
A tongue piece (not shown) extends from the peripheral edge of the common lead 12, and the tongue piece is connected to a power line, a ground line, etc. formed between the signal leads 11. The signal lead 11 and the semiconductor element 14 are connected by a wire 15,
The common lead 12 and the semiconductor element 14 are connected by the wire 16. Also in this embodiment, the insulating film 18 is formed on the common lead 12 at a portion other than the wire bonding portion by the same method as described above. This can prevent a short circuit between the wire 15 and the common lead 12.
【００１４】以上の各実施例においては、共通リード１
２として電源リード、接地リードのいずれかを設けた例
を示したが、双方を設けたものでもよい。またＬＯＣ、
ＣＯＬ以外のリードフレームであって、リードを跨いで
ワイヤが接続されるタイプのもの全てに適用できること
はもちろんである。In each of the above embodiments, the common lead 1
Although the example in which either the power supply lead or the ground lead is provided is shown as 2, the both may be provided. LOC,
It is needless to say that the present invention can be applied to all lead frames other than COL, in which wires are connected across leads.
【００１５】[0015]
【発明の効果】本発明に係るリードフレームによれば、
少なくとも共通リードの半導体素子との接続部位を除く
部位に絶縁皮膜を形成したので、共通リードと半導体素
子との間の電気的接続にはなんら支承がなく、また共通
リードとこれを跨ぐワイヤとの間のショートを好適に防
止でき、さらには該ワイヤのループをそれほど大きくし
なくてもよいから、隣接するワイヤ間でのショートも防
止でき、さらには樹脂封止した際のモールド部が厚くな
らず、装置の小型化が図れる。According to the lead frame of the present invention,
Since the insulating film is formed on at least the part of the common lead other than the connection part with the semiconductor element, there is no bearing for the electrical connection between the common lead and the semiconductor element, and the common lead and the wire that crosses this are not supported. The short circuit between the wires can be preferably prevented, and further, the loop of the wire does not have to be so large. Therefore, the short circuit between the adjacent wires can be also prevented, and further, the mold portion when resin-sealed does not become thick. The size of the device can be reduced.
【図１】第１の実施例を示した断面図である。FIG. 1 is a sectional view showing a first embodiment.
【図２】他の実施例を示した断面図である。FIG. 2 is a sectional view showing another embodiment.
【図３】図２における共通リードの拡大断面図である。FIG. 3 is an enlarged cross-sectional view of the common lead in FIG.
【図４】さらに他の実施例を示す断面図である。FIG. 4 is a sectional view showing still another embodiment.
【図５】従来のＬＯＣタイプのリードフレームを示す断
面図である。FIG. 5 is a cross-sectional view showing a conventional LOC type lead frame.
１０ リードフレーム １１ 信号リード １２ 共通リード １３ 絶縁シート １４ 半導体素子 １５、１６ ワイヤ １８ 絶縁皮膜 １９ Al皮膜 10 Lead Frame 11 Signal Lead 12 Common Lead 13 Insulation Sheet 14 Semiconductor Element 15, 16 Wire 18 Insulation Film 19 Al Film
Claims (2)
ードフレームのように、信号リードの先端側に電源ライ
ン、接地ライン等の共通リードが配置され、搭載される
半導体素子と前記信号リードとが前記共通リードを跨い
でワイヤにより接続されるリードフレームにおいて、 少なくとも前記半導体素子との接続部位を除く前記共通
リード上に前記ワイヤとの短絡防止用の絶縁皮膜が形成
されていることを特徴とするリードフレーム。1. Like a LOC type or COL type lead frame, a common lead such as a power supply line and a ground line is arranged on the tip side of the signal lead, and the mounted semiconductor element and the signal lead are the common lead. In a lead frame which is connected by a wire across the lead frame, an insulating film for preventing a short circuit with the wire is formed on at least the common lead except a connection portion with the semiconductor element.
酸化皮膜もしくは窒化皮膜、またはポリイミド、エポキ
シ樹脂等の絶縁性耐熱性高分子膜であることを特徴とす
る請求項1 記載のリードフレーム。2. The insulating film is an oxide film or nitride film of Al, Si, Ti, Zr, Ta, or an insulating heat-resistant polymer film of polyimide, epoxy resin, or the like. Lead frame as described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5015537A JPH06232323A (en) | 1993-02-02 | 1993-02-02 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5015537A JPH06232323A (en) | 1993-02-02 | 1993-02-02 | Lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06232323A true JPH06232323A (en) | 1994-08-19 |
Family
ID=11891558
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5015537A Pending JPH06232323A (en) | 1993-02-02 | 1993-02-02 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06232323A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08124957A (en) * | 1994-10-28 | 1996-05-17 | Nec Corp | Semiconductor integrated circuit |
-
1993
- 1993-02-02 JP JP5015537A patent/JPH06232323A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08124957A (en) * | 1994-10-28 | 1996-05-17 | Nec Corp | Semiconductor integrated circuit |
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