JPH06232096A - 誘電体平坦化における局部負荷効果の除去 - Google Patents

誘電体平坦化における局部負荷効果の除去

Info

Publication number
JPH06232096A
JPH06232096A JP5330132A JP33013293A JPH06232096A JP H06232096 A JPH06232096 A JP H06232096A JP 5330132 A JP5330132 A JP 5330132A JP 33013293 A JP33013293 A JP 33013293A JP H06232096 A JPH06232096 A JP H06232096A
Authority
JP
Japan
Prior art keywords
dielectric layer
dielectric
plasma
polymer
etch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP5330132A
Other languages
English (en)
Japanese (ja)
Inventor
Dayo Alugbin
アルグビン ダヨー
Avinoam Kornblit
コーンブリット アヴィノン
Edward Paul Martin Jr
ポール マーチン，ジュニヤ エドワード
Kolawole R Olasupo
ラーマン オラスポ コラウォール
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of JPH06232096A publication Critical patent/JPH06232096A/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
    • H10P95/062—Planarisation of inorganic insulating materials involving a dielectric removal step
    • H10P95/064—Planarisation of inorganic insulating materials involving a dielectric removal step the removal being chemical etching

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
JP5330132A 1992-12-31 1993-12-27 誘電体平坦化における局部負荷効果の除去 Withdrawn JPH06232096A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US99932792A 1992-12-31 1992-12-31
US999327 1992-12-31

Publications (1)

Publication Number Publication Date
JPH06232096A true JPH06232096A (ja) 1994-08-19

Family

ID=25546198

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5330132A Withdrawn JPH06232096A (ja) 1992-12-31 1993-12-27 誘電体平坦化における局部負荷効果の除去

Country Status (3)

Country Link
EP (1) EP0607684A3 (enExample)
JP (1) JPH06232096A (enExample)
TW (1) TW243544B (enExample)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4511430A (en) * 1984-01-30 1985-04-16 International Business Machines Corporation Control of etch rate ratio of SiO2 /photoresist for quartz planarization etch back process
US4545852A (en) * 1984-06-20 1985-10-08 Hewlett-Packard Company Planarization of dielectric films on integrated circuits
DE68922474T2 (de) * 1988-12-09 1996-01-11 Philips Electronics Nv Verfahren zum Herstellen einer integrierten Schaltung einschliesslich Schritte zum Herstellen einer Verbindung zwischen zwei Schichten.
JP3092185B2 (ja) * 1990-07-30 2000-09-25 セイコーエプソン株式会社 半導体装置の製造方法
US5378318A (en) * 1992-06-05 1995-01-03 Vlsi Technology, Inc. Planarization

Also Published As

Publication number Publication date
TW243544B (enExample) 1995-03-21
EP0607684A2 (en) 1994-07-27
EP0607684A3 (en) 1995-03-15

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Legal Events

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A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20010306