JPH06231009A - Monitoring device - Google Patents

Abstract

PURPOSE:To provide a monitoring device capable of recognizing the malfunction of a CPU due to a cause other than a transitory one correctly. CONSTITUTION:A CPU monitoring device 11 is equipped with a bus request number of times counter 31 which counts the number of times of bus requests of respective CPU set as the target of monitoring, and applies interruption to the CPU with a count value within a time set by an interval timer 32 less than a value set by a lower limitation setting register 33. A result of interruption is registered on a response register 37. and a control circuit 34 discriminates the CPU as an abnormal one when no normal response is received within fixed time. A discrimination result is outputted to an error display signal line 21 and an error notification signal line 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monitoring system used in a computer system having a plurality of central processing units to monitor the operation of these central processing units.

[0002]

2. Description of the Related Art In a computer system using a central processing unit (hereinafter simply referred to as CPU), the CPU may run away for some reason. Watchdog timers have traditionally been used to monitor CPU runaway and return the system to a normal state when this is detected.

The watch dog timer is disclosed in detail in, for example, Japanese Patent Publication No. 4-19577. That is, in this monitoring method, a signal is generated periodically by the CPU counting clock pulses. Then, when a situation occurs in which the signal generated thereby is interrupted for a predetermined time longer than this cycle, it is determined that a malfunction of the CPU such as runaway has occurred, and appropriate measures are taken. It has become. For example, when this judgment is made, a reset signal is output to reset the CPU to restore normal operation.

By the way, there are various causes of CPU malfunction. One of the typical causes of the transient noise is the occurrence of instantaneous external noise. In addition to this, there are hardware failures and software and other failures. An example of the former is a CPU
Supply of DC power to the
Thermal runaway due to poor cooling of semiconductor elements can be mentioned. An example of the latter is a software defect (bug)
There is a case where there is an error, or a case where an error occurs in the input data and the program itself detects an abnormality and enters an operation halt state.

[0005]

The temporary cause of the malfunction of the CPU can be restored to normal by resetting the CPU using the watch dog timer. . However, if a halt occurs due to a hardware failure or software, the system cannot be restored normally. That is, in this case, even if the watch dog timer detects an abnormality and resets the CPU repeatedly, the CPU will malfunction again in the same situation. Therefore, in such a case, the system cannot be improved even by using the watch dog timer.

Not only that, since the watch dog timer itself operates normally and the CPU is reset, the system itself may have the recognition that the inconvenient situation is not improved even by this. There wasn't. Therefore, even if the system has a mechanism for notifying a higher level system when some kind of trouble occurs, it is not possible to notify this trouble at this stage.

Further, in such a conventional monitoring device, the watch dog timer periodically inputs an interrupt signal to the CPU and checks whether or not there is a response to the signal within a predetermined time. If so, it was decided that the normal operation was performed. Therefore, even when the CPU is operating normally without any problem, it is necessary for the CPU to respond to interrupts that occur periodically, which leads to a substantial decrease in processing capability. is what happened.

Therefore, an object of the present invention is to provide a monitoring device capable of correctly recognizing a malfunction of a CPU caused by a cause other than a transient.

Another object of the present invention is to provide a monitoring device capable of correctly recognizing a malfunction of a CPU and notifying the malfunction to a host device.

Still another object of the present invention is to provide C during normal operation.
It is an object of the present invention to provide a monitoring device capable of monitoring the PU without imposing an excessive burden on the PU.

[0011]

According to a first aspect of the present invention, (a) a frequency measuring means for measuring the frequency of use of a bus by a CPU for a fixed time, and (b) a measurement value of the frequency measuring means in advance. Comparison means to compare with the specified tolerance range, and (c)
When the comparison unit determines that the frequency does not fall within the predetermined allowable range, the monitoring device is provided with an abnormality detection unit that detects an abnormality of the CPU.

That is, in the invention described in claim 1, the CPU
Measures the frequency of using the bus for a certain period of time, and if it is out of a predetermined allowable range, it is determined that some failure has occurred in the CPU and the abnormality of the CPU is detected.

In a second aspect of the present invention, (a) a frequency measuring means for measuring the frequency of use of the bus by the CPU for a fixed time, and (b) a measurement value of the frequency measuring means is compared with a predetermined allowable range. And (c) an interrupt that sends an interrupt signal for outputting a predetermined response to the CPU when the comparison means determines that the frequency does not fall within the predetermined allowable range. (D) signal transmission means, and (d) the CPU within a predetermined time after this interrupt signal is transmitted.
The monitoring device is provided with an abnormality detecting means for detecting an abnormality of the CPU except when the CPU makes a normal response.

That is, according to the second aspect of the present invention, the frequency at which the CPU uses the bus for a certain period of time is measured, and if it is outside the predetermined allowable range, some failure occurs in the CPU. In the meantime, the CPU is interrupted, and if an abnormal response is made or no response is made within a predetermined time, the abnormality of the CPU is detected.

According to the third aspect of the present invention, (a) frequency measuring means for individually measuring the frequency of each of a plurality of CPUs sharing a bus using the bus at a fixed time; and (b) each of the frequency measuring means. A comparing means for comparing the measured value for each CPU with a predetermined allowable range; and (c) outputting a predetermined response to the CPU determined to have a frequency that does not fall within the predetermined allowable range by the comparing means. An interrupt signal transmitting means for transmitting an interrupt signal for the purpose of: (d) Except when the CPU makes a normal response within a predetermined time after the interrupt signal is transmitted, the abnormality of the CPU is detected. The monitoring device is provided with abnormality detecting means for detecting and (e) detection result outputting means for outputting the detection result of the abnormality detecting means to the outside.

That is, the invention according to claim 3 deals with the case where a plurality of CPUs sharing a bus are to be monitored, and in this case, frequency measuring means is prepared for each of these CPUs. Then, each measured frequency is compared with the permissible range, and CPUs that are suspected to be abnormal are interrupted and checked. If any of the CPUs is determined to be abnormal, the detection result is output to the outside. For example, the status of each CPU can be displayed on the display unit and the result can be reported to the host device.

According to the fourth aspect of the present invention, (a) frequency measuring means for individually measuring the frequency of each of a plurality of CPUs sharing a bus using the bus at a fixed time; and (b) each of the frequency measuring means. A comparing means for comparing the measured value for each CPU with a predetermined allowable range; and (c) outputting a predetermined response to the CPU determined to have a frequency that does not fall within the predetermined allowable range by the comparing means. An interrupt signal transmitting means for transmitting an interrupt signal for the purpose of: (d) Except when the CPU makes a normal response within a predetermined time after the interrupt signal is transmitted, the abnormality of the CPU is detected. Abnormality detection means for detecting, (e) bus arbitration means for arbitrating the bus use requests of the plurality of CPUs described above, and (f) when a CPU in which an abnormality is detected by the abnormality detection means makes a bus use request A bus request mask means for masking so as not to reach the stop means is provided in the monitoring device.

That is, the invention according to claim 4 also deals with the case where a plurality of CPUs sharing a bus are to be monitored as in the invention according to claim 3. In the case of the invention described in claim 4, a bus arbitration means for adjusting contention when these CPUs request the use of the bus is provided, and C
CPU is estimated to be abnormal by measuring the frequency for each PU
For the CPU that is finally determined to be abnormal, the bus use request to the bus arbitration unit is masked to prevent the malfunction from occurring.

[0019]

EXAMPLES The present invention will be described in detail below with reference to examples.

FIG. 1 is a monitoring device according to an embodiment of the present invention.
Represents the configuration of a computer system using
It In this system, the CPU monitoring device 11 is a system bus
0th to 3rd CPUs 13 via 12₀~ 13₃And this
Connection with shared memory 14 and input / output control circuit 15
Has been done. The input / output control circuit 15 is not shown
Force device is connected. CPU monitoring device
11 and the 0th to 3rd CPU 13₀~ 13₃Between C
These are individually interrupted from the PU monitoring device 11 side.
Interrupt signal line (INT) 17 for₀~ 17₃And each C
PU13₀~ 13 ₃Requires the use of system bus 12
Bus request line (BR) 18 used when₀~ 18₃When,
The CPU monitoring device 11 has these CPUs 13₀~ 13₃of
Used to allow the use of the system bus 12 for one
Bus use permission line 19₀~ 19₃Are arranged.

Further, one end of an error display signal line 21 and an error notification signal line 22 is connected to the CPU monitoring device 11. The error display signal line 21 is connected to the 0th to 3rd CPUs 13
_{0-13 3} outputs a signal indicating the occurrence of an error, the other end is connected to the error display 23. The error notification signal line 22 is connected to the 0th to 3rd CPUs 13
_0-13 is ₃ for notifying this to the host apparatus when an error occurs, in the present embodiment and the other end is connected to a system management processor (not shown) as a notification destination.

FIG. 2 shows a functional configuration of the CPU monitoring device. The CPU monitoring device 11 includes a bus request number counter 31 that counts the number of bus requests of the _{0th to} 3rd CPUs 13 _{0 to} 13 ₃ shown in FIG. These bus request counts are determined by the interval timer 32.
Is counted within the time set by, and compared with the lower limit value set in the lower limit value setting register 33. As a result, the CPU whose count value is less than the lower limit value
When there is 13, the control circuit 34 sends an interrupt signal to the interrupt signal line 17 connected to the corresponding CPU 13. The response timer 35 is a timer for measuring the response time from the CPU 13 at this time.

In this embodiment, the lower limit value setting register 3
A common lower limit value is set as the lower limit value for each of the CPUs 13 _{0 to} 13 _{3 in} the CPU _3. However, a different lower limit value is set for each of the CPUs 13 _{0 to} 13 ₃ in consideration of the frequency of bus access. Good. In this case, the lower limit value may be registered in the lower limit value setting register 33 for each CPU 13 based on the decoding result of the decoder 36 connected to the address bus 12A.

The CPU monitoring device 11 has a corresponding CPU 1
When there is a response to the interrupt from 3, the decoder 36 decodes the responding CPU 13 and the data bus 1
The data appearing in 2 is registered in the response register 37 so that the control circuit 34 determines whether or not there is a normal response. When it is determined that an error has occurred, the error display signal is output to the error display signal line 21 and the error notification signal is output to the error notification signal line 22.

In addition to this, the CPU monitoring device 11 is provided with a bus arbitration circuit 38 so that arbitration is performed when the system bus 12 (FIG. 1) is used. The input side of the bus arbitration circuit 38, two-input AND gate 3 respectively corresponding to the bus request line 18 _{0-18 3}
9 _{0-39 3} are arranged. Each of the AND gates 39 _{0 to} 39 ₃ receives the bus request signal at one input terminal thereof, and the mask signals 41 _{0 to} 41 ₃ from the control circuit 34 at the other input terminal thereof. There is. These mask signals 41 _{0 to} 41 ₃ are used when the CPU 13 in which an error has occurred generates a bus request signal.
This is to invalidate this.

This is because even if a hardware failure occurs totally temporarily and no problem occurs in the subsequent circuit operation, interruption of the program execution due to this failure causes the CPU 13 to be interrupted by another CPU 13. This is because there is a case where the processing synchronization of is not always taken. Therefore, in a computer system in which one CPU does not cause any inconvenience with another CPU even if the CPU recovers its operation and starts executing a program, it is necessary to always mask the bus request signal. It is natural that there is no.

Next, the circuit operation of the CPU monitoring device shown in FIG. 2 will be specifically described. The lower limit setting register 33 is supplied and set with the lower limit setting data through the data bus D in the system bus 12 shown in FIG. 1 at the stage of initial setting of this device. A clock signal common to the entire system is supplied to the interval timer 32 and the response timer 35 via the clock signal line 51.
The interval timer 32 corresponds to each CPU of the computer system.
13 _{0-13 3} receives a supply of the reset signal 52 from the control circuit 34 at the time of starting the operation, thereafter, and performs the count-up of the clock signal via a clock signal line 51. Then, each time a predetermined count value is reached, a count-up signal 53 is output and the count is again counted up from zero. That is, the interval timer 32 supplies the count-up signal 53 to the control circuit 34 at a predetermined cycle.

When one cycle of the count-up signal 53
The bus request counter 31 is provided for each CPU 13 at intervals.₀~ 13
₃Counts the number of bus requests for. That is, the bus is required
The job counter 31 is for each CPU 13₀~ 13₃Against
Counter 55₀~ 55 ₃Equipped with each
Corresponding bus request line 18₀~ 18₃Connected with.
Then, the interval timer 32 outputs a count-up signal.
Number of these counted bus requests each time 53 is output
Count value information 56₀~ 56₃As control circuit 34
While supplying, immediately after this, the reset signal from the control circuit 34.
Each counter 55 receives the supply of No. 57.₀~ 55
₃The count value of is reset to zero.
In this way, the bus request counter 31
CPU 13₀~ 13₃Bus requests per unit time
The frequency of execution is output as a count value.

Mask signal 4 output from the control circuit 34
1₀~ 41₃Is each CPU 13₀~ 13₃Is detected
In the initial state, it is at H (high) level
It Under this situation, each bus request line 18₀~ 1
8₃To CPU13₀~ 13₃H level indicating bus request from
When a signal is sent from the
39₀~ 39₃Supply to the bus arbitration circuit 38 through
Will be done. As shown in Fig. 1, this computer system
Each CPU13 in the stem₀~ 13₃Is the system bus 12
Are shared. Therefore, the bus arbitration circuit 38 is CP
U13₀~ 13 ₃System bus 1
Use this for any one when you request the use of 2.
To arbitrate the right to use the bus
It This arbitration result is stored in the bus arbitration circuit 38.
Use permission line 19₀~ 19₃Corresponding CPU13₀
~ 13₃It will be sent to.

The control circuit 34 compares the number of bus requests per unit time for each of the CPUs 13 _{0 to} 13 ₃ obtained from the bus request counter 31 with the lower limit value set in the lower limit setting register 33. It is supposed to do. This lower limit value is the interval timer 3 when the CPUs 13 _{0 to} 13 ₃ are assumed to be in a normal operating condition.
2 is set to a value slightly lower than the statistically minimum number of times of requesting a bus within the time of one cycle set. That is, if these CPUs 13 _{0 to} 13 ₃ are operating normally, the number of times of access to the system bus 12 will be larger than the lower limit value in many cases.

On the other hand, if any of the CPUs 13 _{0 to} 13 ₃ fails and execution of the program is stopped, the number of bus requests to the system bus 12 does not increase, and the counter corresponding to the CPU 13 is stopped. 55
The count value of is lower than the lower limit value. Of course, even if the count value of a certain CPU 13 is lower than this lower limit value, it cannot be immediately determined that a failure has occurred in that CPU 13. That cpu
This is because it is fully possible that 13 does not need to access the system bus 12 in a certain time zone.

Therefore, the control circuit 34 controls the CPUs 13 _{0 to} 13
Perform the confirmation work for those that have become lower than the lower limit of the _three . This is done by sending an interrupt signal to the line corresponding to the CPU 13 of which the count value has become lower than the lower limit value among the interrupt signal lines 17 _{0 to} 17 ₃ connected to the control circuit 34. Be seen. The interrupt signal is directly input to the corresponding interrupt terminal INT of the CPU 13 through the interrupt signal line 17, and causes the CPU 13 to perform the interrupt process. If the CPU 13 is normal, a normal response signal is sent to the system bus 12 within the response time set by the response timer 35 as a result of the interrupt processing.

The response timer 35 outputs the reset signal 61 at the timing when the above-mentioned interrupt signal is sent to the interrupt signal line 17 in order to set such a response time.
It is supplied from and the count value is reset to zero. Then, from this time point, the clock signal is counted up through the clock signal line 51, and when the predetermined number of clocks corresponding to the response time is counted up, the count-up signal 62 is sent to the control circuit 34.

On the other hand, the response register 37 is the data bus 12
Data from D and C from which the decoder 36 responded
The type of PU 13 is discriminated. For this reason, the decoder 36 is supplied with address information from the address bus 12A constituting the system bus 12.

The response register 37 is provided for each CPU 13₀~ 1
Three₃4 registers 64 corresponding to ₀~ 64₃Equipped with
There is. These registers 64₀~ 64₃Is the interrupt signal
A response to this is registered for each CPU.
In this, an error bit (E) indicating the occurrence of an error
And a response bit (R) indicating the presence or absence of a response are included.
It

At the timing when the above-mentioned interrupt signal is sent to the CPU 13 in which a failure may occur, the control circuit 34 causes the corresponding register 64 in the response register 37.
The response bit (R) is set to the signal "1" by the response bit set signal 66. Then, before the count-up signal 62 is output from the response timer 35, the corresponding C
When the response data (normally "0") is written from the PU, the response bit of the corresponding register 37 is the signal "1".
Changes to the signal "0". On the other hand, when there is no response within the time, the response bit of the register 37 remains the signal "1". Further, even if the response itself arrives before the count-up signal 62 is output, the error bit (E) in the response data changes from the signal "0" to the signal "1" due to the error detection of the CPU 13. There are cases.

The control circuit 34 reads the error bit (E) and the response bit (R) in the corresponding register 64 when the count-up signal 62 is output from the response timer 35. Then, if the error bit (E) is changed to the signal "1" or the response bit is the signal "1", it is determined that the CPU 13 has some trouble. In this case, the control circuit 34 outputs an error display signal indicating which of the CPUs 13 _{0 to} 13 ₃ has a failure to the error display signal line 21 and outputs an error notification signal to the error notification signal line 22.
Will be output to.

At the same time, the control circuit 34 switches the logic level of the mask signal 41 corresponding to the faulty CPU 13 from the H level to the L (low) level. As a result, the AND gate 39 switched to the L level does not pass the bus request signal appearing on the bus request line 18, and even if a bus request is issued from the faulty CPU 13, this is caused by the bus arbitration circuit 38. Will not be reached. That is, even if the faulty CPU 13 requests the system bus 12, this request is rejected.

When the error display signal is output to the error display signal line 21, the error display device 23 as shown in the figure.
Information for identifying the CPU 13 that has failed is displayed. In this example, the lamp corresponding to the CPU 13 diagnosed as abnormal blinks, and the operator can take an appropriate action. The error signal output to the error notification signal line 22 is notified to the system management processor as described above, and necessary measures such as the work shared by the corresponding CPU 13 being shared by another CPU 13 are taken. Become.

FIG. 3 shows how the control circuit monitors and controls each CPU. The control circuit 34
3 has a built-in CPU (not shown), and similarly executes a program stored in a ROM (read only memory) (not shown) to perform the control as shown in FIG. A random access memory (not shown) for temporarily storing various data when the program is executed is also prepared in the control circuit 34 as a working memory.

The control circuit 34 monitors whether or not the count-up signal 53 is output from the interval timer 32 (step S101). Count up signal 5
When 3 is output (Y), the numerical value N stored in the predetermined area of the working memory is initially set to "0" (step S102). Then, first, it is determined whether or not the count value of the 0th counter 55 ₀ is smaller than the lower limit value set in the lower limit setting register 33 (step S103). If not smaller (N), it is checked whether or not the value N has reached "3" (step S104). In this case, since the value N is "1" (N), the value N is incremented by "1" (step S05). Then, returning to step S103, the same comparison operation is performed for the next first counter 55 ₁ .

In this way, each counter 55 _{0 to} 55 ₃
Are sequentially compared with each other, and it is checked whether or not the corresponding CPUs 13 _{0 to} 13 ₃ are accessing the system bus 12 as often as they are normally performed. At this stage, for example, it is assumed that the count value of the first counter 55 ₁ is smaller than the lower limit value. In this case (step S103; Y), the first CPU 13
_An interrupt signal is output for ₁ (step S106).

At the same time, the response timer 35 starts counting up the clock signal through the clock signal line 51 in order to measure the response time limit (step S10).
7). If there is a response from the first CPU 13 ₁ before the count-up signal 62 is output from the response timer 35 (steps S109; N, S108; Y), it is determined whether the content of the response register 37 is a normal response. Check (step S110). Then, if the response is normal (Y), the first CPU 13 ₁ is normal, and thus the process proceeds to step S104 to proceed to the inspection stage for the next CPU 13 ₂ .

On the other hand, if the first CPU 13 ₁ does not respond normally in step S110,
That is, the error bit (E) in the _first register 64 ₁
Is changed to “1” (step S11
0; N), the first mask signal 41 ₁ is switched from H level to L level, the first CPU 13 ₁ of the bus request line 1
When the bus request signal appears at 8 _1, it blocks (masks) the arrival of the bus request signal at the bus arbitration circuit 38. Further, since it has been found that the first CPU 13 ₁ has a failure, an error display signal is output to the error display signal line 21 and an error notification signal line 22
An error signal is output to (step S111). Then, the process returns to step S104 to start the check operation for the next CPU 13 ₂ .

In this way, the check work for each of the CPUs 13 _{0 to} 13 ₃ progresses in sequence, and for the CPU 13 whose count value falls below the lower limit value during this, it is checked whether or not they normally operate by the interrupt process. A check will be made. Then, when the checking operation for the third CPU 13 ₃ is completed, the value N in step S104 is "3", so that to terminate the entire checking operation without counting up the value (END). Of course, there are more Cs on the system bus 12.
When the PUs 13 are connected, it goes without saying that the check work is repeated up to the value N according to the number.

Modification

FIG. 4 shows the contents of the condition setting register used for explaining a modified example of the monitoring apparatus of the present invention. In this modified example, instead of the lower limit setting register 33 of the previous embodiment, the CP to be monitored
A condition setting register 71 is arranged for each U. The condition setting register 71 has a 16-bit configuration. The most significant 1 bit "C" constitutes a condition bit 72, and the remaining 15 bits represent a condition value 73.

When the condition bit 72 is the signal "0", it determines that the CPU is abnormal when it is less than the value indicated by the condition value 73, and the interrupt processing as described in the previous embodiment. I am going to do. Also, the condition bit 72
Is a signal "1", the CPU is determined to be abnormal when the value indicated by the condition value 73 is exceeded, and the interrupt processing as described in the previous embodiment is performed.

In other words, in this modification, a numerical value that is a criterion for abnormality estimation with respect to the number of times the bus is accessed within a fixed time is freely set for each CPU to be monitored, and when it is larger than the criterion value. The condition bit 72 can set whether to presume abnormal or to presume abnormal when it is small. This allows more detailed monitoring of each CPU.

In the embodiment described above, a plurality of CPs are used.
Although the present invention has been described by taking a computer system in which U is connected to a common bus as an example, it goes without saying that the present invention can also be applied to a monitoring device that monitors a single CPU. Further, in the embodiment and the modified example, when a bus use request is made in a certain period of time, the number is counted and compared with a predetermined value. However, another method such as a ratio of the bus use request frequency is used. It is also possible to compare the value with a predetermined reference value or reference range.

Further, in the embodiment and the modified example, when a certain CPU is inferred to be abnormal as a result of such comparison work, the CPU is further interrupted to make a response,
I decided to judge whether it is operating normally.
However, omitting the latter reconfirmation work, the CP
It goes without saying that it is possible to judge U as abnormal.

In particular, when it is possible to determine to what extent the CPU needs to access the bus in a certain time zone, the lower limit setting register 33 (FIG. 2) or the condition setting register 71 in each time zone can be determined. By frequently rewriting the values, it is possible to determine whether the CPU is abnormal or not with sufficient accuracy.

[0053]

As described above, according to the first aspect of the invention, the frequency at which the CPU uses the bus is measured, and if it is an abnormal value, it is determined that the CPU is abnormal. . Therefore, it is possible to determine whether the CPU is normal or not without imposing any load on the CPU.

According to the invention described in claim 2, CP
Whether the CPU has an abnormality by measuring the frequency at which the bus uses the bus and if it is an abnormal value, further interrupt the CPU to determine whether a normal response is made. I decided to make a final decision on whether to make an accurate decision. Moreover, the interruption to the CPU is limited to the case where an abnormality is suspected, so that there is an advantage that the CPU is not excessively burdened with the monitoring.

Further, according to the third aspect of the invention, a plurality of CPUs sharing a bus are targeted for monitoring, and these C
It is possible to determine the presence or absence of an abnormality without imposing an excessive load on the PU. In addition, when an abnormality is detected, the result is output to the outside. Therefore, for example, by outputting the result to the display, the operator can be informed of which CPU is abnormal. In addition, by notifying the host device, it is possible to take measures so as not to hinder the cooperative work of the plurality of CPUs.

According to the invention described in claim 4, the bus usage frequency is measured for each of the plurality of CPUs, and the CPUs that are suspected to be abnormal are confirmed by interruption, and finally the abnormality is detected. With regard to the CPU determined to be the above, the use request of the bus to the bus arbitration means is masked, so that the malfunction of the entire system can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a computer system using a monitoring device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a functional configuration of a CPU monitoring device in this embodiment.

FIG. 3 is a flowchart showing a state of supervisory control of each CPU by a control circuit.

FIG. 4 is an explanatory diagram showing contents of a condition setting register in a modified example of the present invention.

[Explanation of symbols]

11 ... CPU monitoring device (monitoring device), 12 ... System bus, 13 _{0 to} 13 ₃ ... CPU, 14 ... Shared memory, 17
... interruption signal line, 18 ... bus request line, 19 ... bus use permission line, 21 ... error display signal line, 22 ... error notification signal line, 23 ... error display device, 31 ... bus request counter,
32 ... Interval timer, 33 ... Lower limit setting register,
34 ... Control circuit, 35 ... Response timer, 37 ... Response register, 38 ... Bus arbitration circuit, 39 ... AND gate, 55 ...
Counter, 64 ... Register, 71 ... Condition setting register,
72 ... Condition bit, 73 ... Condition value

Claims (4)

[Claims] 1. A frequency measuring means for measuring a frequency at which a central processing unit uses a bus for a fixed time, a comparing means for comparing a measured value of the frequency measuring means with a predetermined allowable range, and a comparing means for preliminarily using the comparing means. A monitoring device comprising: an abnormality detecting unit that detects an abnormality of the central processing unit when it is determined that the frequency does not fall within a predetermined allowable range. 2. A frequency measuring means for measuring the frequency of use of the bus by the central processing unit for a certain period of time, a comparing means for comparing the measured value of the frequency measuring means with a predetermined allowable range, and the comparing means beforehand. When it is determined that the frequency does not fall within the defined allowable range, an interrupt signal transmitting means for transmitting an interrupt signal for outputting a predetermined response to the central processing unit, and this interrupt signal are transmitted. A monitoring device comprising: an abnormality detecting means for detecting an abnormality of the central processing unit except when the central processing unit makes a normal response within a predetermined time after the operation. 3. A frequency measuring means for individually measuring the frequency of each of a plurality of central processing units sharing a bus using the bus at a fixed time, and a measurement value for each central processing unit by the frequency measuring means is predetermined. Comparing means for comparing with the allowable range, and an interrupt signal for outputting a predetermined response to the central processing unit, which is determined by the comparing means to have a frequency that does not belong to the predetermined allowable range. An interrupt signal transmitting means, and an abnormality detecting means for detecting an abnormality of the central processing unit unless the central processing unit makes a normal response within a predetermined time after the interruption signal is transmitted, A monitoring device comprising: a detection result output means for outputting the detection result of the abnormality detection means to the outside. 4. A frequency measuring means for individually measuring the frequency of use of a bus by each of a plurality of central processing units sharing a bus, and a measurement value for each central processing unit by the frequency measuring means is predetermined. Comparing means for comparing with the allowable range, and an interrupt signal for outputting a predetermined response to the central processing unit, which is determined by the comparing means to have a frequency that does not belong to the predetermined allowable range. An interruption signal sending means, an abnormality detecting means for detecting an abnormality of the central processing unit except when the central processing unit makes a normal response within a predetermined time after the interruption signal is sent, Bus arbitration means for arbitrating bus usage requests of a plurality of central processing units, and when the central processing unit in which the abnormality is detected by the abnormality detection means makes a bus usage request, this reaches the bus arbitration means. Monitoring apparatus characterized by comprising a bus request mask means for masking so as not.