CN115236497A - Method for diagnosing clock and timer of SOC (System on chip) - Google Patents

Abstract

The invention discloses a diagnosis method of a clock and a timer of an on-chip SOC, relating to the field of fault diagnosis; the clock diagnosis method comprises the following steps: receiving a preset diagnosis signal; detecting whether the duration of a high level signal of the preset diagnostic signal is the first duration and/or whether the duration of a low level signal of the preset diagnostic signal is the second duration based on a local clock signal; and if so, sending a first detection result signal for indicating that the local clock is normal to the detection unit, otherwise, sending a second detection result signal for indicating that the local clock is abnormal to the detection unit. According to the method and the device, the clock and the timer of the SOC on the chip are respectively subjected to abnormity detection, the problem that abnormity diagnosis of the clock and the timer in the prior art is not accurate enough is solved, and the abnormity diagnosis accuracy of the clock and the timer can be improved on the premise of not increasing extra hardware.

Description

Method for diagnosing clock and timer of SOC (System on chip)

Technical Field

The invention relates to the field of fault diagnosis, in particular to a method for diagnosing a clock and a timer of an on-chip SOC.

Background

The invention relates to the Field of functional safety of industrial control, in an industrial control system, a common controller hardware architecture consists of an MCU (micro controller Unit), an FPGA (Field Programmable Gate Array), wherein the MCU is used for realizing control logic, and the FPGA is used for realizing interfaces such as communication and safety related diagnosis. The functional safety system is used as an important ring in an industrial control system and used for guaranteeing the safety of production, and if the signal accessed into the functional safety system in the production process is abnormal, the functional safety system immediately acts to stop the production of the system and gives an alarm. If the control is disabled due to an abnormality in the functional safety system itself, there is a possibility that the system cannot operate normally when an abnormal situation occurs in the production, and thus, it is necessary to diagnose safety-related functions such as a clock and a timer, which may cause a failure.

In the prior art, a scheme is to additionally access a clock for diagnosis, periodically obtain clock values of a normal clock and a diagnostic clock, calculate a difference value of 2 clocks at a specified time interval in the period, and judge whether the clocks are abnormal by comparing the difference values of the 2 clocks, but the scheme additionally adds a clock source to diagnose whether the clocks are abnormal, and the newly added clock source is often only used for diagnosis, which not only increases fault points, but also increases hardware cost. In the clock diagnosis, if the diagnosed clock is abnormal, the clock is also determined to be abnormal according to the scheme, so that the normal operation is influenced.

The other scheme is that a time window based on an external clock is generated, the number of internal clock cycles is calculated in the time window, whether the external clock is abnormal or not is judged by comparing whether the number of cycles is larger than an upper limit value or smaller than a lower limit value, but the scheme uses the internal clock to diagnose the external clock. Because the temperature drift of the internal clock is large, the precision is not as high as that of the external clock, the upper limit and the lower limit threshold range of the internal period number in a window generated by the external clock are large, the scheme can only diagnose whether the external clock works normally, and cannot diagnose whether the frequency of the external crystal oscillator generates deviation.

Therefore, a method for diagnosing the clock and the timer of the on-chip SOC of the functional safety system needs to be designed, whether the current clock is abnormal or not can be accurately diagnosed without adding an additional clock circuit, the timer is diagnosed while the clock is diagnosed, and the execution period of the periodic task performed by the timer is stable and reliable.

Disclosure of Invention

The embodiment of the application provides a diagnosis method of a clock and a timer of an on-chip SOC (system on chip), which is used for at least solving the problem that the abnormity diagnosis of the clock and the timer is not accurate enough in the related technology.

In a first aspect, an embodiment of the present application provides a clock diagnosis method for an on-chip SOC, including:

receiving a preset diagnosis signal, wherein the preset diagnosis signal comprises a high level signal with a first duration and a low level signal with a second duration;

detecting whether the duration of a high level signal of the preset diagnosis signal is the first duration and/or whether the duration of a low level signal of the preset diagnosis signal is the second duration based on a local clock signal;

and if so, sending a first detection result signal for indicating that the local clock is normal to the detection unit, otherwise, sending a second detection result signal for indicating that the local clock is abnormal to the detection unit.

In some embodiments, before detecting whether the duration of the high level signal of the preset diagnostic signal is the first duration and/or detecting whether the duration of the low level signal of the preset diagnostic signal is the second duration based on the local clock signal, the method further comprises:

and acquiring the first duration and the second duration.

In some of these embodiments, obtaining the first duration and the second duration comprises:

reading a value of a first preset register, wherein the value of the first preset register is written in by the detection unit;

and determining the first duration and the second duration according to the value of the first preset register.

In some of these embodiments, the method further comprises:

reading a value of a second preset register, wherein the value of the second preset register is written in by the detection unit;

and determining whether to execute an abnormality diagnosis method according to the value of the second preset register.

In some of these embodiments, the first duration is equal to the second duration.

In a second aspect, an embodiment of the present application provides a method for diagnosing a timer of an on-chip SOC, including:

detecting whether the interval time between two adjacent interrupts of a preset timer is a preset period or not based on a local clock of the timer to be diagnosed, wherein the interval time between the interrupts of the preset timer is the preset period;

if so, determining that the timer to be diagnosed works normally; otherwise, determining that the timer to be diagnosed works abnormally.

In some embodiments, the count value of the timer to be diagnosed is saved in a count register; the method for detecting whether the interval time between two adjacent interrupts of the preset timer is a preset period or not comprises the following steps of based on the local clock of the timer to be diagnosed:

reading a first count value stored in a count register of the timer to be diagnosed when the preset timer is interrupted for the Nth time;

reading a second count value stored in a count register of the timer to be diagnosed when the preset timer is interrupted for the (N + 1) th time;

and determining the interval time of two adjacent interrupts of the preset timer according to the difference value between the second count value and the first count value, and judging whether the interval time is the preset period.

In some of these embodiments, in the event that it is determined that the timer to be diagnosed is operating abnormally, the method further comprises:

counting the times of the abnormal working of the timer to be diagnosed;

and executing an exception handling program of the timer to be diagnosed under the condition that the working exception times of the timer to be diagnosed meet set conditions.

Compared with the related art, the diagnosis method of the clock and the timer of the SOC provided by the embodiment of the application detects the clock and the timer of the SOC respectively without adding an additional hardware detection loop, thereby reducing the hardware cost and the fault points; whether the SOC on the chip is abnormal or not is comprehensively judged according to the detection result, and the clock and the timer are diagnosed, so that the diagnosis coverage rate of the SOC on the chip is improved; the problem of the clock of SOC and the abnormal diagnosis of timer among the prior art is not accurate enough is solved, SOC abnormal diagnosis accuracy and reliability have been promoted on the chip, guarantee production safety that SOC can be stable has been guaranteed on the chip.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the application.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:

fig. 1 is a block diagram of a hardware configuration of a terminal of a diagnostic method of a clock and a timer of an on-chip SOC according to the present invention;

FIG. 2 is a flow chart of a clock diagnostic method for an SOC provided by the present invention;

FIG. 3 is a flow chart of a method for diagnosing a timer of an SOC provided in the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided in the present application without any creative effort belong to the protection scope of the present application.

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the specification. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is to be expressly and implicitly understood by one of ordinary skill in the art that the embodiments described herein may be combined with other embodiments without conflict.

Unless defined otherwise, technical or scientific terms referred to herein shall have the ordinary meaning as understood by those of ordinary skill in the art to which this application belongs. Reference to "a," "an," "the," and like terms in this application do not denote a limitation of quantity, but rather denote the singular or plural. The use of the terms "including," "comprising," "having," and any variations thereof herein, is meant to cover a non-exclusive inclusion; for example, a process, method, system, article, or apparatus that comprises a list of steps or modules (elements) is not limited to the listed steps or elements, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. Reference to "connected," "coupled," and the like in this application is not intended to be limited to physical or mechanical connections, but rather can include electrical connections, whether direct or indirect. The term "plurality" as used herein means two or more. "and/or" describes the association relationship of the associated object, indicating that there may be three relationships, for example, "a and/or B" may indicate: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. References to "first," "second," "third," etc. in this application are only to distinguish between similar items and do not denote a particular ordering for the items.

The method embodiment provided by the embodiment can be particularly applied to the field of functional safety related to industrial control, is realized based on an on-chip SOC, and can be executed in a terminal, a computer or a similar operation device. Taking an example of the terminal running on the terminal, fig. 1 is a block diagram of a hardware structure of the terminal of the diagnostic method for the clock and the timer of the SOC on the chip provided by the present invention, as shown in fig. 1, the terminal may include one or more processors, and the processors include but are not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA, etc., and it can be understood by those skilled in the art that the structure shown in fig. 1 is only an illustration and is not a limitation to the structure of the terminal. For example, the terminal may have a different configuration than that shown in fig. 1, such as a combination of a microprocessor MCU and a complex programmable logic device CPLD.

As shown in fig. 1, the processor includes a microprocessor MCU and a programmable logic device FPGA, the microprocessor MCU includes a preset timer, a to-be-diagnosed timer, a timer diagnosis unit, and a detection unit, the programmable logic device FPGA includes a clock diagnosis unit, and the processor is divided into a clock detection module 1 and a timer detection module 2 according to functions.

In the clock detection module 1, a detection unit comprises a clock to be detected, a first preset register and a second preset register, and a clock diagnosis unit comprises a local clock; the SOC is configured with a detection period based on the stability requirement and the system resource sufficiency degree and stored in a second preset register, and the detection unit determines whether to execute an abnormal diagnosis method by reading the detection period in the second preset register; the abnormality diagnosis method comprises the steps that a detection unit reads the duration of a high level signal and the duration of a low level signal in preset diagnosis signals, records the duration of the high level signal as a first duration and writes the duration of the high level signal into a first preset register, and records the duration of the low level signal as a second duration and writes the duration of the low level signal into the first preset register; the clock diagnosis unit is used for detecting a preset diagnosis signal sent by a clock to be detected and sending a detection result to the detection unit; the clock diagnosis unit obtains a first duration and a second duration by reading the value of the first preset register; the clock diagnosis unit is provided with a local clock, the clock diagnosis unit detects the duration of a high level signal and the duration of a low level signal of a preset diagnosis signal sent by the clock to be diagnosed based on a local clock signal, if the duration of the high level signal of the preset diagnosis signal detected based on the local clock signal is a first duration and the duration of the low level signal is a second duration, the local clock is normal, the clock diagnosis unit sends a first detection result signal for indicating that the local clock is normal to the detection unit, if the duration of the high level signal of the preset diagnosis signal detected based on the local clock signal is not the first duration or the duration of the low level signal is not the second duration, the local clock is abnormal, the clock diagnosis unit sends a second detection result signal for indicating that the local clock is abnormal to the detection unit, and when the clock diagnosis unit receives the second detection result signal, the clock diagnosis unit immediately executes a clock abnormality processing program to remind a worker of maintaining the clock detection module.

In the timer detection module 2, the to-be-diagnosed timer comprises a counting register and a local clock, and the timer diagnosis unit comprises a counting value cache unit; the method comprises the following steps that a preset timer continuously enters interruption according to a preset period preset by a system, and a waiting diagnosis timer is used for detecting whether the interval time between two adjacent times of entering interruption of the preset timer is the preset period or not; a counting register in the timer to be diagnosed records the running time of the preset timer, and when the preset timer enters interruption for the Nth time, the timer to be diagnosed reads a first counting value in the counting register and stores the first counting value to a counting value cache unit; when the N +1 th time of the preset timer enters interruption, the waiting diagnosis timer reads a second count value in the count register and stores the second count value to the count value cache unit; calculating the difference value between the second count value and the first count value to obtain the interval time of two adjacent interrupts of the preset timer based on the local clock, and judging whether the interval time is the preset period of the preset timer, wherein if the interval time is the preset period of the preset timer, the timer to be diagnosed works normally, and otherwise, the timer to be diagnosed works abnormally; recording the second count value as a first count value and storing the first count value in a count value cache unit for the next interrupt detection of the preset timer; counting the working abnormal times of the timer to be diagnosed under the condition that the timer to be diagnosed is judged to be abnormal; and executing a timer exception handling program under the condition that the timer exception times are judged to meet the set conditions.

The present embodiment provides a diagnostic method of a clock and a timer of an on-chip SOC. Fig. 2 is a flowchart of a clock diagnosis method for an on-chip SOC according to the present invention, where the diagnosis method is used for diagnosing a clock abnormality of the on-chip SOC, and the flowchart includes the following steps:

step S101: receiving a preset diagnosis signal, wherein the preset diagnosis signal comprises a high level signal with a first duration and a low level signal with a second duration.

In step S101, a clock diagnosis unit receives a preset diagnosis signal sent by a clock to be detected, where the preset diagnosis signal is a rectangular wave signal, the preset diagnosis signal includes a high level signal and a low level signal, the detection unit reads a duration of the high level signal and records the duration as a first duration, reads a duration of the low level signal and records the duration as a second duration, and stores the first duration and the second duration in a first preset register.

Step S102: a first duration and a second duration are obtained.

In step S102, the clock diagnosis unit determines a first duration and a second duration by reading a value of a first preset register.

The rectangular wave signal is widely applied to a digital switch circuit, the rectangular wave signal has only two states, namely a high level signal or a low level signal, the output states of the high level signal and the low level signal are alternately changed at certain time intervals, namely, the output states are periodically changed, and the first duration time is equal to the second duration time.

Step S103: and detecting whether the duration of a high level signal of the preset diagnosis signal is a first duration and/or whether the duration of a low level signal of the preset diagnosis signal is a second duration based on the local clock signal.

In step S103, the first duration and the second duration are set with allowable error ranges based on the system accuracy requirement.

Detecting whether the duration of the high level signal of the preset diagnostic signal is the first duration specifically is: the clock diagnosis unit records the high level duration of a preset diagnosis signal; when the preset diagnosis signal is converted from a high-level signal to a low-level signal, obtaining the duration time of the high-level signal, and judging whether the duration time of the high-level signal is within the allowable error range of the first duration time.

Detecting whether the duration of the low level signal of the preset diagnostic signal is the second duration specifically comprises: the clock diagnosis unit records the low level duration of a preset diagnosis signal; and when the preset diagnosis signal is converted from a low-level signal to a high-level signal, obtaining the duration time of the low-level signal, and judging whether the duration time of the low-level signal is within the allowable error range of the second duration time.

Step S104: and if so, sending a first detection result signal for indicating that the local clock is normal to the detection unit, otherwise, sending a second detection result signal for indicating that the local clock is abnormal to the detection unit.

In step S104, after detection, if the high level signal of the preset diagnosis signal is within the allowable error range of the first duration, and meanwhile, the low level signal of the preset diagnosis signal is within the allowable error range of the second duration, it indicates that the local clock is working normally, and at this time, the first detection result signal indicating that the local clock is normal is sent to the detection unit; when the high-level signal of the preset diagnosis signal is not in the allowable error range of the first duration, or the low-level signal of the preset diagnosis signal is not in the allowable error range of the second duration, the local clock is abnormal in operation, and at this time, a second detection result signal representing the local clock is abnormal is sent to the detection unit.

And after receiving the second detection result signal, the detection unit confirms that the local clock is abnormal, immediately executes a clock abnormality processing program, triggers a system to alarm, and reminds a worker to immediately maintain the SOC on the chip so as to prevent the monitoring effect of the SOC on the industrial control system from being invalid due to abnormal operation of the SOC on the chip, and further prevent the potential hazards in the production process from being discovered in time and processed correspondingly.

In the above step, it is determined whether to execute the abnormality diagnosis method by reading a value of a second preset register, where the value of the second preset register is written by the detection unit, and the value of the second preset register is a detection period configured based on a stability requirement of the SOC on the chip and a sufficient degree of system resources.

Through the steps, the problem that the clock abnormity diagnosis in the SOC is not accurate enough is solved, and the accuracy of the SOC abnormity diagnosis is improved on the premise of not increasing extra hardware.

In one application of the above embodiment, the predetermined diagnostic signal is at a frequency of 100 Hz; presetting a high level signal duration in the diagnostic signal, i.e. a first duration of time

Bringing the frequency of a preset diagnosis signal into T1=5ms, adding an allowable error range to the time reference, and calculating to obtain a normal range of the first duration of 4.95ms-5.05ms by taking 1% as an example; detecting whether the duration of a high-level signal of a preset diagnosis signal is within a normal range of 4.95ms-5.05ms of a first duration based on a local clock signal; presetting the duration of a low-level signal in the diagnostic signal, i.e. the second duration

Bringing the frequency of a preset diagnosis signal into T2=5ms, adding an allowable error range to the time reference, and calculating to obtain a normal range of the second duration time to be 4.95ms-5.05ms by taking 1% as an example; and detecting whether the duration of a low level signal of the preset diagnosis signal is a second duration, if the high level duration and the low level time of the preset diagnosis signal are both in a normal range, sending a first detection result signal for indicating that the local clock is normal to the detection unit, and otherwise, sending a second detection result signal for indicating that the local clock is abnormal to the detection unit.

When the local clock signal is at the frequency of 98Hz, detecting that the duration time of the high level and the duration time of the low level are both 5.10ms and exceed the normal range, and sending a first detection result signal for indicating that the local clock is normal to a detection unit; when the local clock signal is at a frequency of 102Hz, detecting that the high level duration and the low level duration are both 4.90ms and also exceed the normal range, and sending a first detection result signal for indicating that the local clock is normal to the detection unit.

Fig. 3 is a flowchart of a timer diagnosis method of an on-chip SOC according to the present invention, the diagnosis method is used for diagnosing a timer abnormality of the on-chip SOC, and the flowchart includes the following steps:

step S201: detecting whether the interval time between two adjacent interrupt entries of a preset timer is a preset period or not based on a local clock of the timer to be diagnosed, wherein the interval time between the two interrupt entries of the preset timer is the preset period.

In step S201, a preset timer continuously enters into an interrupt according to a preset period preset by the system, a waiting-to-be-diagnosed timer is used for detecting whether an interval time between two adjacent interrupts entering of the preset timer is the preset period, and the preset period is provided with an allowable error range based on a system precision requirement; a counting register in the timer to be diagnosed records the running time of the preset timer, and when the preset timer is interrupted for the Nth time, the timer to be diagnosed reads a first counting value in the counting register and stores the first counting value to a counting value cache unit; when the N +1 th time of the preset timer enters the interruption, the timer to be diagnosed reads a second count value in the count register and stores the second count value to the count value cache unit; and calculating the difference value between the second count value and the first count value to obtain the interval time of the two adjacent interrupts of the preset timer based on the local clock, and judging whether the interval time is within the allowable error range of the preset period of the preset timer.

Step S202: if so, determining that the timer to be diagnosed works normally; otherwise, determining that the timer to be diagnosed works abnormally.

In step S202, when the detected interval time is within the allowable error range of the preset period, it indicates that the timer to be diagnosed is working normally, and at this time, a first diagnostic result signal indicating that the timer to be diagnosed is normal is sent to the diagnostic unit; when the interval time is not within the allowable error range of the preset period, the working of the timer to be diagnosed is abnormal, and at the moment, a second diagnosis result signal which represents the abnormality of the timer to be diagnosed is sent to the diagnosis unit; and recording the second count value as the first count value and storing the first count value in a count value cache unit for the next interrupt detection of the preset timer.

Step S203: and counting the times of the abnormal working of the timer to be diagnosed under the condition of determining the abnormal working of the timer to be diagnosed.

In step S203, after receiving the second diagnosis result signal, the timer diagnosis unit determines that the timer to be diagnosed is abnormal, records an abnormal log of the timer to be diagnosed and the abnormal times of the timer to be diagnosed, and accumulates errors of the timer to be diagnosed; counting the working abnormal times of the timer to be diagnosed under the condition that the timer to be diagnosed is judged to be abnormal; when the number of times of timer abnormality is judged to satisfy the set condition to be diagnosed, the timer abnormality processing program is executed in step S204: and executing an exception handling program of the timer to be diagnosed under the condition that the number of times of the timer to be diagnosed working abnormally meets the set condition.

In step S204, the setting condition may be that the number of times of abnormality of the timer to be diagnosed reaches N times, specifically, the number of times may be set based on the requirement of system accuracy; the setting condition can also be that a preset allowable error range of the timer to be diagnosed is set based on system precision, when the accumulated error exceeds the preset allowable error range, an abnormal timer processing program is immediately executed, and the system is automatically reset, so that the abnormal SOC operation on the chip caused by the abnormal timer is prevented, the monitoring effect of the abnormal timer on the industrial control system is further prevented from being failed, and the hidden danger in the production process cannot be timely discovered and correspondingly processed.

Through the steps, the problem that the timer abnormity diagnosis of the SOC on chip is not accurate enough is solved, and the accuracy of the SOC abnormity diagnosis on the chip is improved on the premise of not increasing extra hardware.

In one application of the foregoing embodiment, the interrupt period of the preset timer is configured to be 100ms, the waiting timer counting period is configured to be 5s, and the range of the counting register value is 0-50000. During the operation, 10 times of interrupt operation data of the preset timer are intercepted, as shown in the following table.

The allowable error range is 1% as an example, the range of the counting register of the timer to be diagnosed is 0-50000, the interrupt time of the preset timer is 100ms, the difference value of the counting register of the timer to be diagnosed is 1000, and the normal range is 990-1010. The above application examples are only illustrative, and in an actual application scenario, the method embodiment of the present invention may have different application data.

Those of skill in the art will understand that the logic and or steps represented in the flowcharts or otherwise described herein, such as an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions.

It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following technologies, which are well known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

All possible combinations of the technical features in the above embodiments may not be described for the sake of brevity, but should be considered as being within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.

The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the disclosure herein is not limited to the particular combination of features described above, but also encompasses other combinations of features described above or their equivalents without departing from the spirit of the disclosure. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims (8)

1. A clock diagnostic method for an on-chip SOC, comprising:

receiving a preset diagnosis signal, wherein the preset diagnosis signal comprises a high level signal with a first duration and a low level signal with a second duration;

detecting whether the duration of a high level signal of the preset diagnosis signal is the first duration and/or whether the duration of a low level signal of the preset diagnosis signal is the second duration based on a local clock signal;

and if so, sending a first detection result signal for indicating that the local clock is normal to the detection unit, otherwise, sending a second detection result signal for indicating that the local clock is abnormal to the detection unit.

2. The clock diagnostic method of an on-chip SOC of claim 1, wherein before detecting whether a duration of a high level signal of the preset diagnostic signal is the first duration and/or a duration of a low level signal of the preset diagnostic signal is the second duration based on a local clock signal, the method further comprises:

and acquiring the first duration and the second duration.

3. The clock diagnostic method of an on-chip SOC of claim 2, wherein obtaining the first duration and the second duration comprises:

reading a value of a first preset register, wherein the value of the first preset register is written in by the detection unit;

and determining the first duration and the second duration according to the value of the first preset register.

4. The clock diagnostic method of an on-chip SOC of any one of claims 1-3, further comprising:

reading a value of a second preset register, wherein the value of the second preset register is written in by the detection unit;

and determining whether to execute a clock diagnosis method of the SOC according to the value of the second preset register.

5. The clock diagnostic method of an on-chip SOC of any one of claims 1-3, wherein the first duration is equal to the second duration.

6. A timer diagnostic method for an SOC on a chip, comprising:

detecting whether the interval time between two adjacent interrupts of a preset timer is a preset period or not based on a local clock of the timer to be diagnosed, wherein the interval time between the interrupts of the preset timer is the preset period;

if so, determining that the timer to be diagnosed works normally; otherwise, determining that the timer to be diagnosed works abnormally.

7. The timer diagnosis method of SOC according to claim 6, wherein the count value of the timer to be diagnosed is saved in a count register; the method for detecting whether the interval time between two adjacent interrupt entries of the preset timer is a preset period or not based on the local clock of the timer to be diagnosed comprises the following steps:

reading a first count value stored in a count register of the timer to be diagnosed when the preset timer is interrupted for the Nth time;

reading a second count value stored in a count register of the timer to be diagnosed when the preset timer is interrupted for the (N + 1) th time;

and determining the interval time of two adjacent interrupt entering of the preset timer according to the difference value of the second counting value and the first counting value, and judging whether the interval time is the preset period.

8. The timer diagnosis method of an SOC on a chip according to claim 6, wherein in a case where it is determined that the timer to be diagnosed is abnormally operated, the method further comprises:

counting the times of the abnormal working of the timer to be diagnosed;

and executing an exception handling program of the timer to be diagnosed under the condition that the working exception times of the timer to be diagnosed meet set conditions.

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