JPH06224874A - Transmission/reception timing synchronism control circuit - Google Patents

Abstract

PURPOSE:To eliminate the influence of jitter caused by reception side noise generated in the case of synchronizing transmission/reception timing with the timing of the opposite side station or high-order network of burst transmission/ reception, to make the circuit into an IC and to reduce power consumption at the time of TDMA mobile communication for performing communication through a base station. CONSTITUTION:This circuit is provided with a clock generating circuit 1 for generating a clock at the N-fold frequency of a processing clock to generate the transmission/reception timing, a frequency dividing phase control circuit 2 for outputting a frequency divided phase phi for which one of totally N pieces of outputs dividing the frequency and delaying it just for a 1/N cycle later is selected, transmission/reception timing generation circuit 6 for outputting a desired transmission/reception timing output TO and a gate timing signal GT. Then, phase difference between reception frame timing FT and a frame clock FC from a frequency dividing circuit 3 is detected and stored, and the frequency divided phase phi corresponding to a phase difference output 5 is selected when the GT is turned on.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is necessary in a communication system for performing burst communication with each other by a time division multiplexing method or the like when synchronizing the speed of transmission / reception timing of its own station with a partner station or network. The present invention relates to improvement of a timing synchronization control circuit.

[0002]

2. Description of the Related Art In the case of transmitting and receiving continuous information by burst communication such as time division multiplexing, burst information obtained by compressing the continuous transmission information, which is continuous information on the transmitting side, on the time axis and the burst information are transmitted. Both of the continuous reception information received and expanded to the original continuous information on the time axis need to be synchronized in terms of speed. FIG. 5 shows an example of the timing relationship between the above continuous transmission information, burst information, and continuous reception information. FIG. 5 shows a case of a 4-channel time division multiplexing system in which 4 slots are formed per frame. Continuous transmission information of 1 frame length is compressed into burst information of 1 slot and continuous reception of 1 frame length is received again. It shows how the information is expanded. In the figure, the middle burst information is generally a so-called overhead signal such as a preamble for extracting the burst reception timing necessary for the receiving side and a synchronization signal (shaded portion in the figure) for identifying the burst information portion. Will be added. In addition, a card space, which is a non-signal section for allowing a deviation in processing delay and a deviation in transmission delay of a communication terminal occupying the slot, is required between the slots.

As an example of realizing the timing relationship shown in FIG. 5, the case of generating a transmission / reception timing synchronized with a reception signal from a partner station will be taken up. FIG. 6 shows a conventional configuration example of the timing synchronization control circuit used in this case. In the figure, 41 is a voltage controlled oscillator (VCO), which outputs an oscillating wave having a frequency controlled by a control voltage input. 42 is a frequency dividing circuit for dividing the output of the (VCO) 41 up to the frequency of the symbol timing of burst communication, and 43 is a phase for performing a phase comparison between the symbol timing input ST given from the receiving system and the output of the frequency dividing circuit 42. A comparator, 44 is a loop filter that removes harmonic components from the output of the phase comparator 43, and is usually composed of a first-order or second-order low-pass filter (LPF), the output of which is the control voltage of the VCO 41. It is fed back to the input. Reference numeral 45 denotes a transmission / reception timing generation circuit, which uses the output of the VCO 41 as a clock source to generate various desired transmission / reception timing outputs TO necessary for the frame configuration shown in FIG. 5 and output them to the outside.

In the above structure, the VCO 41, the frequency dividing circuit 42, the phase comparator 43, and the loop filter 44 are PLL.
(Phase Locked Loop), and a transmission / reception timing output TO that is phase-synchronized with the symbol timing input ST given from the receiving system can be obtained. At this time, the output frequency of the VCO 41 is set to K times the frequency of ST, where K is the frequency division number of the frequency dividing circuit 42.

[0005]

However, in the above-mentioned conventional configuration, since the VCO output which is successively phase-synchronized with the symbol timing input ST is used as the transmission / reception timing generation source, the jitter of the ST is affected by the noise in the receiving system. When it becomes large, it has a considerable influence on the timing generation of the transmission system. The influence of the jitter can be changed by the loop band width of the PLL determined by the loop filter 44, the frequency division number K, the gain of the VCO 41, etc.
Generally, when the loop bandwidth is narrowed to suppress the influence of jitter to a low level, the response speed of synchronization pull-in becomes slow and it takes time to establish synchronization of the system. Also, the loop filter 4
In general, the VCO 41 and the like are not suitable for IC, and there is a problem that the miniaturization of the entire circuit is limited.

A method of simply replacing the PLL part of the configuration of FIG. 6 with a digital PLL is also conceivable. However, since the configuration is such that phase synchronization is executed in real time by sampling for each of the waveforms, it affects timing generation during transmission and reception. This cannot be avoided, and the above-mentioned problem of jitter cannot be solved at all. This similarly poses a problem when the transmission / reception timing of the own station is synchronized with the timing of the upper network. In general, the clock synchronization system in digital networks has a very high accuracy of the reference clock source, but as the number of stages of the subordinate synchronous loop increases, the accuracy of the loop far from the reference clock is temporarily increased due to phenomena such as wandering. Is known to go down. Therefore, in the conventional configuration, the timing accuracy of the transmission system of burst communication may not satisfy the standard. An object of the present invention is to provide a transmission / reception timing synchronization control circuit that can avoid the influence of jitter, which is a problem in the conventional configuration, and that can be easily integrated into an IC.

[0007]

A transmission / reception timing synchronization control circuit outputs a clock having a frequency N times a processing clock frequency required for transmission / reception timing generation in order to synchronize transmission / reception timing with a burst reception input signal as a synchronization reference. And a clock generation circuit for generating the clock, and (N-1) frequency division phases φ ₁ , φ ₂ , ... Which are obtained by dividing the clock output and delaying the reference phases φ ₀ and φ ₀ from each other by 1 / N period. φ _N−1 is output, a phase offset generation circuit that outputs a phase offset Δφ obtained by integrating a phase difference output ε given from the outside, and a phase offset Δφ are input.
Each value [Delta] [phi = 0, 1, 2 of the phi, ... N-1, respectively phi ₀ corresponds _{to, φ 1, ... φ N-} 1 was switched selected N's alternative, and outputs as a frequency division phase output phi A frequency dividing phase control circuit including a switching circuit, a frequency dividing circuit for dividing an output of the frequency dividing phase control circuit to obtain a frame timing clock having the same cycle as one frame defined in communication, A phase comparator that detects a phase difference between the frame timing clock and the frame timing input of the burst reception input signal, and temporarily stores the output of the phase comparator, and temporarily stores it when an externally provided gate timing signal is in the ON state. The value obtained as the phase difference output ε to the frequency dividing phase control circuit and resetting the temporary memory value to 0 when the gate timing signal changes to the off state; and the frequency dividing phase control. The desired transmission and reception timing output using the output φ of the road, is characterized in that a transmission and reception timing generation circuit for generating said gate timing signal supplied to the temporary storage circuit.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Structure) FIG. 1 is a block diagram showing an example of the structure of the present invention. In the figure, 1 is a clock N having a frequency N times the processing clock frequency f _CLK required for transmission / reception timing generation.
This is a clock generation circuit that generates f _CLK .

Reference numeral 2 denotes a phase control frequency dividing circuit, which divides the clock Nf _CLK by N in accordance with an integrated amount Δφ of the phase difference output ε given from the outside to obtain a frequency division output phase Δφ ₀ of Δφ.
The output phase φ that is phase-offset by only is output. A frequency dividing circuit 3 divides the output of the frequency dividing phase control circuit 2 to obtain a frame timing clock FC having the same cycle as the frame.
Is a phase comparator for detecting the phase difference between the FC and the frame timing input FT of the received burst signal given as a frame timing reference from the outside. This circuit may use a circuit that binarizes the phase difference such as a D type flip-flop, and the frequency division output of the frequency divider 3 is F.
A circuit that multi-values the phase difference may be used in the configuration of latching at the timing of T.

A temporary storage circuit 5 temporarily stores the phase comparison output, and when the externally applied gate timing signal GT is in the ON state, the temporary storage value is used as the phase difference output ε for frequency division phase control. It has a function of outputting to the circuit 2 and resetting the temporary storage value to 0 when the GT changes to the off state. Such a function can be easily realized by using a register including a flip-flop. Reference numeral 6 denotes a transmission / reception timing generation circuit, which generates various desired transmission / reception timing outputs TO necessary for frame configuration in the communication line and the gate timing signal GT by using the output of the frequency division phase control circuit 2.

[0011]

The operation of the present invention based on the configuration example of FIG. 1 will be described below with reference to FIG. FIG. 2 is a time chart of an operation example when the configuration of the present invention is applied to time division multiplexing burst communication. In the figure, the uppermost stage is the received signal, and shows the case where the number of time division multiplexing is 4, as in the case of FIG. At this time, one frame is composed of four burst signals, that is, four slots of (1), (2), (3), and (4), and each slot includes burst information, a preamble, and a synchronization signal. Overhead is added and a guard space is provided between burst signals. Also,
In the figure, FT represents a frame timing input, FC represents a frame timing clock, and GT represents an operation of a gate timing signal.

Now, assuming that the slot assigned to the own station is (1), the detection result becomes the frame timing FT every time the synchronization signal of the slot (1) (hatched portion in the figure) is received. It is input to the phase comparator 4. The other input of the phase comparator 4 is a frame timing clock FC obtained by dividing the output φ of the frequency division phase control circuit 2 by the frequency division circuit 3, and FT and F at each time point A and B in the figure.
The phase difference of C is determined. In the example of the figure, the reference signal F
With respect to T, the state in which the phase of FC is “delayed” at time A and “advanced” at time B is fixed. The phase difference at this time is stored as ΔN in the temporary storage circuit 5, and is supplied to the frequency division phase control circuit 2 when the gate timing signal GT is turned on at each time point a and b in the figure. In the frequency division phase control circuit 2, when “delay” (Δφ is negative) at time A and “advance” (Δφ is positive) at time B are determined, the output φ of the frequency division phase positive circuit 2 is , Δφ are set appropriately in front of the switching circuit 23, so that | Δ at the time point a
Since it is possible to perform the operation of advancing the phase by φ | and delaying it at the point b, it is understood that the negative feedback control of the phase synchronization is executed.

What should be noted is the timing of executing the negative feedback control. The ON state of GT is given in the guard space after the slot (slot (1)) of the received signal is finished. By giving the GT timing in this way, it is possible to perform synchronization without affecting the transmission / reception timing generation during transmission / reception.
That is, the conventional analog PLL or digital PLL
It is possible to realize phase synchronization by intermittent off-line processing which is completely different from real-time phase synchronization in the configuration using.

Next, details of the frequency division phase control circuit 2, which is one of the constituent elements of the present invention shown in FIG. 1, will be described.
FIG. 3 shows an example of the configuration of the frequency division phase control circuit 2, and FIG. 4 is an explanatory diagram of its operation. In FIG. 3, 21 is Nf _CLK
Is divided by N, and a free-run reference division phase φ ₀ and (N-1) division phases φ ₁ , φ ₂ , ..., φ _{N-1 obtained} by delaying φ ₀ by 1 / N cycle. It is an N frequency division counter that outputs and, and can be easily realized by using a circulation counter such as a ring counter or a Johnson counter. Reference numeral 22 is a phase offset generation circuit that inputs ε and outputs a phase offset Δφ that is integrated. ε is a comparison result of the reference phase (FT) and the feedback phase (FC). For example, in the case of binary determination of lead and lag, ε = + 1 and −1 may be used, or ε = + 0.
It may be 1, -0.1. Phase offset generation circuit 22
Sequentially integrates this to update the currently output phase offset Δφ. 23 inputs the phase offset Δφ, and selects and switches φ ₀ , φ ₁ , ... φ _N-1 by N alternatives corresponding to each value of Δφ Δφ = 0, 1, 2, ... N-1. It is a switching circuit that outputs the output.

FIG. 4 is a time chart showing the mutual phase relationship of the _N frequency division phases φ ₀ , φ ₁ , ... φ _N-1 of the N frequency division counter 21. As shown in the figure, the frequency division phases adjacent to each other have a relationship of being shifted by 1 / N period (2π / N radian). Therefore, the output φ of the switching circuit 22 is

[ _Equation 1] φ = [φ ₀ + Δφ] _modN (1) (where [•] _modN is an operation modulo N), and the phase offset Δφ when φ _i is selected
Is as shown. It can be seen that the output phase φ obtained by phase offsetting the phase φ ₀ of the divided output divided by N by Δφ can be obtained by using this Δφ as the control amount.

The above example of FIG. 2 is for the case where the own station generates the transmission / reception timing synchronized with the received signal from the partner station, but as another example, the same is true when it is synchronized with the timing of the higher level network. Therefore, at this time, the frame timing input FT of FIG. 2 is given from the network to its own station. In this case, in the configuration of the present invention, even if the timing accuracy of the network temporarily decreases,
During transmission / reception of the burst signal, the synchronous system operates not in the negative feedback closed loop configuration but in the open loop configuration completely dependent on the frequency accuracy of the clock generation circuit 1 of the local station, so that it is easy to satisfy the standard for burst communication. is there.

[0017]

As described above in detail, according to the present invention, it is possible to generate a transmission / reception timing which does not depend on noise or timing accuracy of the other station with respect to the other station or a host network. In realizing,
There are advantages that IC, low power consumption, and miniaturization are easy.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of the present invention.

FIG. 2 is a time chart explaining the operation of the present invention.

FIG. 3 is a partial detailed view of the present invention.

FIG. 4 is a time chart explaining a partial operation of the present invention.

FIG. 5 is a structural example diagram of a TDMA frame to which the present invention is applied.

FIG. 6 is a diagram illustrating a conventional configuration example.

[Explanation of symbols]

 1 clock generation circuit 2 frequency division phase control circuit 3 frequency division circuit 4 phase comparator 5 temporary storage circuit 6 transmission / reception timing generation circuit 21 N frequency division counter 22 phase offset generation circuit 23 switching circuit 41 VCO 42 frequency division circuit 43 phase comparator 44 Loop Filter 45 Transmission / Reception Timing Generation Circuit

Claims (1)

[Claims] 1. A clock generation circuit for generating a clock output having a frequency N times as high as a processing clock frequency required for transmission / reception timing generation in order to synchronize transmission / reception timing with a burst reception input signal as a synchronization reference, and the clock output. (N-1) divided phases φ obtained by delaying the reference phases φ ₀ and φ ₀ from each other by 1 / N period.
₁ , φ ₂ , ... φ _N-1 , a N frequency dividing counter, a phase offset generating circuit that outputs a phase offset Δφ obtained by integrating a phase difference output ε given from the outside, and a phase offset Δφ are input. Each value of Δφ = 0, 1, 2, ... N
Corresponding to -1, φ ₀ , φ ₁ , ... φ _N-1 are selectively switched by N alternatives, and a frequency division phase control circuit configured by a switching circuit for outputting as a frequency division phase output φ, A frequency dividing circuit for dividing the output of the frequency dividing phase control circuit to obtain a frame timing clock having the same period as one frame defined on communication, and a frame timing clock and a frame timing input of the burst reception input signal. A phase comparator for detecting a phase difference, and an output of the phase comparator is temporarily stored, and when the externally applied gate timing signal is in the ON state, the temporarily stored value is used as the phase difference output ε for the frequency division phase control. A temporary storage circuit that outputs the signal to the circuit and resets the temporary storage value to 0 when the gate timing signal changes to an off state; A receiving timing output, transmission and reception timing synchronization control circuit and a transmitting and receiving timing generation circuit for generating said gate timing signal supplied to the temporary storage circuit.