JPH06223512A - Data reproducing device - Google Patents

Abstract

PURPOSE:To exactly correct an error and to enhance error correcting performance by changing error correction processing with identification data assigned to excess bits of data as a reference. CONSTITUTION:By assigning the excess bits an interleave block code, the identification data of the interleave block in a byte unit consisting of a unit of error correction processing in addition to the identification data of the interleave block in a prescribed data unit consisting of a frame address are assigned. In an input/output circuit 3, output data of an error correction processing circuit 5 is latched 11 via a prescribed memory circuit, and after audio data is interleave-processed, the data is restored to its original data and is outputted via an interpolation circuit 12. Moreover, in the circuit 3, a result of a comparator circuit 13 is supplied to a flag processing circuit 14, and in the circuit 14, the interpolation circuit 12 is changed in operation with the comparison result and an error correction processing result C1/C2 outputted via a data bus BUS as a reference.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Field of Industrial Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems (FIGS. 1 and 5) Operation (FIGS. 1 and 5) Embodiments (1) Configuration of Embodiments (FIGS. 1 to 1) (FIG. 6) (2) Effect of the embodiment (3) Other embodiment Effect of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproducing device,
For example, it can be applied to a digital audio tape recorder.

[0003]

2. Description of the Related Art Conventionally, in a digital audio tape recorder, audio data can be surely reproduced by performing error correction processing using a block-completed error correction code.

That is, in this type of digital audio tape recorder, audio data sequentially input at a predetermined bit rate is blocked in an interleave cycle of 30 [msec]. Further, in the digital audio tape recorder, the block audio data is interleaved and then sequentially assigned to a pair of recording tracks for recording.

At this time, in the digital audio tape recorder, an error correction code (that is, C1 and C2 code) in the product code format is added to the audio data and recorded. As a result, in the digital audio tape recorder, it is possible to correct the error in units of this interleave period, and it is possible to surely reproduce the audio data even when a dropout or the like occurs.

[0006]

By the way, in this kind of audio equipment, there is an equipment designed to process 24-bit audio data. In this kind of digital audio tape recorder, 24
If the bit audio data can be recorded / reproduced, the usability can be further improved and the application field can be expanded.

In this case, for example, a method of operating a digital audio tape recorder at a speed twice as high as a normal speed to divide the audio data having a large bit rate and recording / reproducing it can be considered. That is, in the 24-bit audio data, the 12-bit audio data is formed by the right and left channels.
Bit audio data is divided into upper 6 bits and lower 6 bits so that 12 bits of audio data are continuous.

On the other hand, in a digital audio tape recorder, 12 bit audio data divided by setting the operating speed to be doubled by recording / reproducing 16 bit audio data is normally used for this 16 bit audio data. Be assigned to. By doing so, it is considered that audio data having a high bit rate can be recorded / reproduced with a simple configuration in which the operation speed of the digital audio tape recorder is increased.

However, in the case of recording and reproducing audio data having a high bit rate in this way, the error correction capability is such that only the same correction capability as that of a normal digital audio tape recorder can be obtained. That is, if the error correction capability can be improved by recording and reproducing audio data having a high bit rate, the usability of this type of digital audio tape recorder can be further improved.

In this case, if the divided 12-bit audio data is assigned to the 16-bit audio data and recording / reproducing is effectively used to improve the error correction capability, the error correction capability can be improved accordingly. It is considered that the configuration can improve the error correction capability.

The present invention has been made in consideration of the above points, and proposes a data reproducing apparatus capable of improving error correction capability by effectively utilizing surplus bits in recording / reproducing data having different bit rates. Is what you are trying to do.

[0012]

In order to solve such a problem, according to the present invention, in the data reproducing apparatus 1 for reproducing the record data recorded on a predetermined recording medium, the record data is obtained by dividing the data D1 to be processed. Converted into processed data D2 of a predetermined bit, and the processed data D2 is interleaved in a predetermined cycle, and then recorded with block-completed error correction codes C1 and C2 in units of each interleave cycle, and the data D1 to be processed is recorded. Divided and processed data D2
When converting to, the identification data for identifying the interleave period is assigned to the surplus bit and recorded.
Is a demodulation circuit 6 that demodulates the recorded data and outputs demodulation data D3, and error correction processing circuits 5 and 6 that perform error correction processing on the demodulation data D3 based on the error correction codes C1 and C2.
And a data processing circuit 3 that restores the output data of the error correction processing circuits 5 and 6 to the data D1 to be processed. The correction process is switched to perform the error correction process on the demodulated data D3.

[0013]

If the error correction processing is switched based on the identification data assigned to the surplus bit and the demodulation data D3 is subjected to the error correction processing, the error correction capability can be improved accordingly.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

(1) Configuration of the Embodiment In FIG. 1, reference numeral 1 denotes a magnetic recording / reproducing apparatus as a whole, and in an analog digital conversion circuit (A / D) 2, audio signals sequentially input are 24-bit audio data D1. Is converted into a continuous digital audio signal.

In the input / output circuit 3, the audio data D1 is supplied to the data processing circuit 4, where it is converted into 16-bit audio data. That is, in the data processing circuit 4, the 24-bit audio data D formed by the right and left channel 12-bit audio data.
For 1 (FIG. 2 (A)), the audio data of the right and left channels are divided into the upper bit and the lower bit, respectively, and thereby the 6-bit audio data is generated.

Further, in the data processing circuit 4, a 2-bit interleave block code is added to the higher order of the 6-bit audio data to generate 8-bit audio data (FIG. 2B). As a result, the data processing circuit 4 outputs the 8-bit audio data in units of 2 symbols.
Converts 24-bit audio data D1 input at a predetermined transfer rate to 16-bit audio data D2,
The data is output to the data bus BUS at a transfer speed twice as high as the input.

At this time, in the data processing circuit 4, the audio data is processed in synchronization with a predetermined reference signal, so that it becomes 15 [mse] which is 1/2 of the interleave cycle of a normal digital audio tape recorder.
c) 16-bit audio data is interleaved and output in a cycle. Further, in the data processing circuit 4, the value of the interleave block code is sequentially and cyclically switched in synchronism with this processing cycle. Therefore, in this embodiment, at the time of reproduction, this interleave block code is used as a reference, It is possible to judge which interleaved block the reproduced audio data belongs to.

Thus, in this embodiment, four kinds of interleaved blocks can be discriminated by using the 2-bit surplus bit of the audio data D2.

The error correction processing circuit (ECC) 5 adds a parity code for error correction to the sequentially input audio data D2 and outputs it. At this time, the error correction processing circuit 5
In (1), according to the format of a normal digital audio tape recorder, an error correction code in a product code format is added at a processing speed twice as high as that of a normal digital audio tape recorder. Further, when the error correction code is generated, the error correction processing circuit 5 processes the audio data in synchronization with the processing cycle of the data processing circuit 4.

On the other hand, in the modulation / demodulation circuit 6,
The audio data and error correction code output from the error correction processing circuit 5 are input together with predetermined subcode data, and these data are modulated by a modulation method suitable for recording on a magnetic tape.

In the magnetic recording / reproducing apparatus 1, during recording,
The magnetic tape running system is driven at a speed twice that of an ordinary digital audio tape recorder, and the output signal of the modulation / demodulation circuit 6 is output to the magnetic head through a predetermined amplifier circuit. As a result, in the magnetic recording / reproducing apparatus 1, the audio data is recorded by sequentially forming the recording tracks according to the standardized format of the digital audio tape recorder.

On the other hand, during reproduction, the magnetic recording / reproducing apparatus 1
, The magnetic tape running system is driven at the same speed as that at the time of recording, and the reproduction signal S2 obtained through the magnetic head is sequentially obtained.
Is demodulated by the modulation / demodulation circuit 6. At this time, the modulation / demodulation circuit 6
Is an error detection process using the C1 code for the reproduced audio data (that is, a C1 error detection process).
Then, the detection results are combined.

The frame address detection circuit 7 separates the subcode data from the reproduced data demodulated by the modulation / demodulation circuit 6 and detects the frame address from the subcode data. That is, in a digital audio tape recorder, one frame of audio data having an interleave period is recorded in a pair of recording tracks, and a frame address is assigned as identification data of this frame.

This frame address is arranged such that addresses from value 0 to value F are sequentially and cyclically assigned, so that in this kind of digital audio tape recorder, the interleave block is discriminated in a predetermined data unit. It is designed to get you.

Therefore, in this embodiment, by assigning an interleave block code to the surplus bit, in addition to the identification data of the interleave block of a predetermined data unit which is a frame address, the interleave is performed in a byte unit which is a unit of error correction processing. The block identification data has been assigned.

When the frame address detection circuit 7 detects a frame address which is determined to be a correct frame address in the C1 error detection result of the sequentially demodulated audio data, the frame address detection circuit 7 sequentially outputs the frame address to the frame address counter 8. In the frame address counter 8, the counter is cleared in the interleave cycle to count the frame addresses n-1, n, n + 1 having the same value, respectively.

The frame address setting circuit 9 detects the frame address n having the largest count value from the count result of the frame address counter 8, and the detection result n is erroneous at a predetermined timing via the delay circuit (D) 10. It outputs to the correction processing circuit 5 and the input / output circuit 3. In the error correction processing circuit 5, the operation is switched during reproduction, and the audio data D3 demodulated by the modulation / demodulation circuit 6 is subjected to error correction processing.

At this time, in the error correction processing circuit 5,
The error correction process is performed on the audio data based on the interleaved block code added to the audio data, and thus the surplus bits of the audio data are effectively used to improve the reliability of the error correction process. There is.

That is, as shown in FIG. 3, the demodulated audio data D3 operates at a speed twice as fast as that of a normal digital audio tape recorder, so that the demodulated audio data D3 has an interleave cycle of 15 [msec] (see FIG. 3).
(A)), sequential interleaved block code (Fig. 3
The values of (B) and (C) are switched.

Here, in the digital audio tape recorder, 4 and 6 parity codes are assigned as C1 and C2 codes, respectively, so that when audio data of the same interleaved block is subjected to error correction processing, the maximum is possible. It has the ability to correct 4 and 6 errors respectively.

However, in this type of magnetic recording / reproducing apparatus, the original audio data may be left unerased when overwriting and recording. There is also a case where audio data is reproduced by off-track.

In such a case, as shown in FIG. 4, in the unerased audio data and the off-track reproduced audio data (audio data in the hatched area), the error detection process using the C1 code is performed. , It is determined that the audio data is correct, and a flag FOK that is the determination result is output.

In this case, C having the same interleave period
When one error detection detects 6 errors (represented by numbers 1 to 6 in FIG. 4) and the error flag FNG is output, the unerased audio data is corrected as C2 erasure as correct audio data. . That is, in this case, the error correction process is erroneously executed.

Therefore, in the conventional digital audio tape recorder, the error correction capability is reduced and the audio data is subjected to the error correction process, whereby the error correction can be effectively avoided.

On the other hand, in the error correction processing circuit 5, the audio data is processed on the basis of the interleaved block code to detect audio data having different interleaved blocks, and the eraser correction process is omitted for this audio data. Therefore, erroneous correction can be effectively avoided without reducing the error correction capability of the C1 and C2 codes.

That is, in the error correction processing circuit 5,
As shown in FIG. 5, this error correction processing is executed by executing a microprogrammed processing procedure in interleave block units. First, the processing shifts from step SP1 to step SP2, and the modulation and demodulation circuit 6 starts. The C1 error detection flag output is fetched.

Subsequently, in the error correction processing circuit 5, at step SP3, when the audio data is fetched with the frame address n as a reference, the following step SP4.
It is determined whether or not there is audio data which is determined to have no error and whose interleave block code is different from other audio data.

If an affirmative result is obtained here, it is considered that the unerased or untracked audio data is reproduced in this case, so that the error correction processing circuit 5
At step SP5, the C2 error correction processing (that is, C1 erasure correction) based on the C1 error detection result is set to the prohibited state, and the error correction processing is executed at the subsequent step SP6. As a result, the error correction processing circuit 5 carries out error detection and correction processing using only the C2 code.

On the other hand, if a negative result is obtained in step SP4, this means that when only the audio data of the same interleaved block is reproduced, the audio data reproduced after being left unerased or offtrack is judged to be erroneous. In this case, the error correction processing circuit 5 directly moves to step SP6,
Perform normal error correction processing. In the error correction processing circuit 5, the C2 error is corrected on the basis of the C1 error detection result in the normal error correction processing, and the error correction processing is performed with the error correction ability of the error correction code.

Thus, by adding the interleave block code for each audio data by using the surplus bit of the audio data, the audio data can be subjected to the error correction processing based on this interleave block code, which is remarkably higher than the conventional one. The error correction ability can be improved. As a result, in the error correction processing circuit 5, when the error correction processing is executed for the interleaved block, the process moves from step SP6 to step SP2,
Error correction processing is executed for the subsequent interleaved blocks.

In the input / output circuit 3, the output data of the error correction processing circuit 5 is sequentially fetched into the latch circuit (R) 11 via a predetermined memory circuit to de-interleave the audio data, and then the original data. The 24-bit audio data is restored and output through the interpolation circuit 12. At this time, in the input / output circuit 3, the delay circuit 1
The comparison circuit 13 compares the frame address n output from 0 with the interleave block code assigned to each audio data to determine whether the frame address n is a correct interleave block code.

Further, the input / output circuit 3 outputs the comparison result of the comparison circuit 13 to the flag processing circuit 14, and the flag detection circuit 14 outputs the comparison result and the error correction processing result output via the data bus BUS. C1 / C2
The operation of the interpolation circuit 12 is switched on the basis of.

That is, the input / output circuit 3 can correctly determine whether or not the error correction processing can be performed by the error correction processing using the C1 and C2 codes based on the error correction processing result C1 / C2. The audio data that cannot be processed is interpolated by the interpolating circuit 12 and output. On the other hand, even if no error is detected, the audio data reproduced after being left unerased or offtrack is
Since it is not the original audio data, in the input / output circuit 2, the comparison circuit 13 detects this audio data and the interpolation circuit 12 performs interpolation processing.

In particular, as shown in FIG. 5, in this kind of digital audio tape recorder, during variable speed reproduction, audio data is reproduced by diagonally crossing a plurality of recording tracks to reproduce a plurality of interleaves in one interleave cycle. The block will be played. As a result, as in this embodiment, the audio data of the interleaved block code corresponding to the most correctly reproduced frame address is directly output (see FIG. 3).
(D)) By interpolating and outputting audio data of other interleaved block codes, it is possible to reduce sound quality deterioration during variable speed reproduction.

Thus, in the magnetic recording / reproducing apparatus 1,
The audio data reproduced in this way is output via a digital analog conversion circuit (D / A) 15.

(2) Effects of the Embodiments According to the above configuration, when the 24-bit audio data is divided and converted into 16-bit audio data, and the audio data is recorded at twice the normal operating speed. To
An interleaved block code for identifying an interleaved block is assigned to the surplus bit of the audio data for recording, and at the time of reproduction, the error correction process is switched based on this interleaved block code to sufficiently correct the C1 and C2 codes. Even if the error is exerted and the error is corrected, the error correction can be prevented in advance, so that the surplus bit can be effectively used to improve the error correction capability.

(3) Other Embodiments In the above embodiment, the error correction processing is switched on the basis of the interleave block code so that the correction capability of the C1 and C2 codes is sufficiently exerted to correct the error. I mentioned the case of preventing erroneous correction in advance,
The present invention is not limited to this, and may be applied to, for example, the case of 5 erasure correction, and the process of confirming whether the data can be correctly processed after the correction may be omitted.

Further, in the above-mentioned embodiment, the case where the input / output circuit determines whether the interleave block is correct and performs the interpolation process is described. However, the present invention is not limited to this, and the error correction is performed based on the interleave block code. Alternatively, only the audio data corresponding to the frame address may be selectively output from the processing circuit, and the input / output circuit may interpolate the audio data.

Further, in the above embodiment, the case where the magnetic tape running system and the signal processing circuit are operated at a speed twice as high as the normal operation speed to record the audio data having a large bit rate has been described. The invention is not limited to this, and when operating the magnetic tape running system and the signal processing circuit at a predetermined speed higher than the normal operating speed to record audio data, the invention is further operated at the normal operating speed and bit rate. The present invention can be widely applied to the recording of data with a large sampling frequency and a low sampling frequency, and further to the recording of various data other than audio data.

Furthermore, in the above-mentioned embodiments, the case where the present invention is applied to a digital audio tape recorder to record and reproduce audio data has been described. However, the present invention is not limited to this, and various recording media can be processed. The present invention can be widely applied to the case where the data to be processed is divided and recorded when the data is recorded.

[0052]

As described above, according to the present invention, when reproducing data recorded by dividing the data of a predetermined bit and adding a block completion type error correction code, the surplus bit of this data is previously recorded. Assign identification data for each block,
By switching the error correction processing based on this identification data, it is possible to make full use of the correction capability of the error correction code to reliably perform error correction, and thus the surplus bit when recording / reproducing data with different bit rates is effective. It is possible to obtain a data reproducing device capable of improving the error correction capability by utilizing the above.

[Brief description of drawings]

FIG. 1 is a block diagram showing a magnetic recording / reproducing apparatus according to an embodiment of the present invention.

FIG. 2 is a schematic diagram used to explain the audio data.

FIG. 3 is a signal waveform diagram for explaining the operation.

FIG. 4 is a schematic diagram used for explaining processing of unerased audio data.

FIG. 5 is a flowchart for explaining the operation of the error correction processing circuit.

FIG. 6 is a schematic diagram for explaining the operation of the input / output circuit.

[Explanation of symbols]

1 ... Magnetic recording / reproducing device, 3 ... Input / output circuit, 4 ... Data processing circuit, 5 ... Error correction processing circuit, 6 ... Modulation and demodulation circuit, 7 ... Frame address detection circuit, 8 ... Frame address Counter, 9 ... Frame address setting circuit, 10 ... Delay circuit, 12 ... Interpolation circuit, 13 ... Comparison circuit, 14 ... Flag processing circuit.

Claims (1)

[Claims] 1. A data reproducing apparatus for reproducing recorded data recorded on a predetermined recording medium, wherein the recorded data is divided into data to be processed and converted into processed data of a predetermined bit, and the processed data is processed at a predetermined cycle. After interleaving processing with, the data is recorded together with a block-completed error correction code in units of each interleaving cycle, and when the data to be processed is divided and converted into the processing data, the interleaving cycle is identified as an extra bit. The data reproducing apparatus allocates and records identification data, and the data reproducing apparatus demodulates the recorded data and outputs demodulated data, and an error correction processing circuit that performs error correction processing on the demodulated data based on the error correction code. And a data processing circuit for restoring the output data of the error correction processing circuit to the data to be processed, The error correction processing circuit switches the error correction processing on the basis of the identification data assigned to the surplus bit to perform error correction processing on the demodulated data.