JPH06222961A - Watchdog timer - Google Patents

Abstract

PURPOSE:To provide the watchdog time(WDT) which can detect both of the case when being triggered before a set value and the case when the set value elapses after being triggered as abnormality. CONSTITUTION:When a trigger signal TRIG showing the execution start of a program is inputted, counting is started from a count value CNT '0' and a counter 2 outputting a count value CNT at each time point outputs an abnormality signal OUT when the trigger signal TRIG is inputted while the count value CNT is less than a set value T1 and when the count value CNT reaches a set value T2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a watchdog timer for detecting runaway of a computer.

[0002]

2. Description of the Related Art A watchdog timer is used as a means for stopping runaway of a program in a system using a microprocessor (hereinafter abbreviated as MPU). The watchdog timer is reset by a trigger signal every time the MPU starts executing a program, and measures a predetermined time. When the MPU goes into a runaway state and the program execution time becomes abnormally long, the watchdog timer finishes counting and a timer-out signal is output. Based on this timer-out signal, the MPU
The abnormal operation of is detected.

[0003]

Generally, an MPU is generally used.
In a system that uses, in addition to the abnormal operation in which the execution time of the program becomes abnormally long as described above, the processing that should be executed originally is not executed and the execution of the program ends in a short time. Can occur. However, the above-described conventional watchdog timer cannot detect the abnormal operation of the latter, and thus the operation of the system is not completely protected.

The present invention has been made in view of the above circumstances, and detects an abnormality in both cases of being triggered before the set value and when the set value has passed since the last trigger. The purpose is to provide a watchdog timer that can.

[0005]

In order to solve the above problems, according to the present invention, a trigger signal indicating the start of execution of a program is input to start time counting from "0". Timing means for outputting a time value at a time point, and a second setting in which the trigger signal is input when the time value is less than or equal to a first set value and the time value is greater than the first set value. And an abnormality detection means for outputting an abnormality signal when the value is reached.

[0006]

According to the present invention, because of the above configuration, it is possible to detect an abnormality both in the case where the set value is triggered before the set value and when the set value has elapsed since the last trigger.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. A: Configuration of Embodiment FIG. 1 is a block diagram showing the configuration of a watchdog timer according to this embodiment. This watchdog timer is MP
It is a timer that outputs an abnormal signal when the execution of the program by U is completed within the set value T1 or when it is not completed even after exceeding the set value T2 (> T1). In FIG. 1, reference numeral 1 denotes an oscillator, which has a predetermined cycle (for example, 1 millisecond).
Then, the pulse signal S1 is sequentially output.

3 and 6 are setting devices. First, the setting device 3
Sets the set value T1, and outputs the set value T1 to the magnitude comparator 4. Next, 6 is for setting a set value T2, and this set value T2 is set in a counter 2 which will be described later.
Output to.

The counter 2 is reset by a trigger signal TRIG generated during execution of a program by an MPU (not shown) and counts a pulse signal S1 supplied from the oscillator 1. The count value CNT of the counter 2 is output to the magnitude comparator 4. Further, when the value of the count value CNT reaches the set value T2 of the setter 6, the counter 2 stops the counting operation and outputs the signal S2 having the value "1" to the OR gate 7.
Output to.

The magnitude comparator 4 has a count value C of the counter 2.
The magnitudes of NT and the set value T1 supplied from the setter 3 are compared. Then, as a result of the comparison, the count value C
When the relationship of NT ≦ setting value T1 is satisfied, the signal S4 having a value of “1” is output to the AND gate 5, and when the relationship of count value CNT> setting value T1 is satisfied, the value is “0”. The signal S4 is output to the AND gate 5.

The AND gate 5 outputs the signal S5 having the value "1" to the OR gate 7 when both the signal S4 and the trigger signal TRIG become "1". That is, the AND gate 5 is for detecting that the value of the trigger signal TRIG becomes "1" before the counter 2 reaches the set value T1. The OR gate 7 has signals S5 and S
When at least one of the two becomes "1", the abnormal signal OUT having a value of "1" is output.

B: Operation of the Embodiment The operation of this embodiment will be described with reference to FIGS. 1 and 2. In FIG. 2, t0 indicates the time when the trigger signal TRIG is generated, t1 indicates the time when the time corresponding to the set value T1 has elapsed from time t0, and t3 indicates the time when the time corresponding to the set value T2 has elapsed from the time t0. . First, when the trigger signal TRIG is output at time t0, this trigger signal TIG
The counter 2 is reset by the RIG, and thereafter, the count value CNT of the counter 2 sequentially increases from "0" as indicated by the straight line L1.

The value of the signal S4 is "1" since the count value CNT satisfies the relationship "count value CNT≤set value T1" between time t0 and time t1. Therefore, when the trigger signal TRIG is output from the time t0 to the time t1, the output value of the AND gate 5 becomes "1". As a result, the value of the signal S5 becomes "1", and the OR gate 7 outputs the abnormal signal OUT having the value "1". In this way, the count value CNT of the counter 2
Even if the trigger signal TRIG becomes "1" before reaches the set value T1, it is detected as an abnormality.

As described above, it is assumed that the counting is started from the time t0 and the time t2 is reached without detecting the trigger signal TRIG. Then, from time t2 to time t
When the trigger signal TRIG is output during the period of 3, the count value CNT of the counter 2 is “count value CN
Since the relation of T <set value T2 is satisfied, the signal S2 having a value of "0" is output. On the other hand, the size comparator 4
The count value CNT is "count value CNT> set value T1".
Signal S4 whose value is "0" because the relationship
Is output. Therefore, the output value of the AND gate 5, that is, the signal S5 becomes "0". As a result, the output value of the OR gate 7 is "0", that is, the signal OUT is "0".
become. As described above, when the trigger signal TRIG is detected before the count value CNT of the counter 2 reaches the set value T2, it is considered that the normal operation is performed.

Next, it is assumed that counting is started from time t0 in the same manner as described above, and time t3 is reached without detecting the trigger signal TRIG. Then, since the count value CNT of the counter 2 reaches the set value T2, the signal S2 becomes "1". Therefore, from OR gate 7, the value is "1".
The abnormal signal OUT is output. In this way, if the trigger signal TRIG does not become "1" even when the count value CNT of the counter 2 reaches the set value T2, it is considered to be abnormal.

[0016]

As described above, according to the present invention, the timekeeping value is started from "0" by the input of the trigger signal indicating the start of execution of the program, and the timekeeping value at each time point is output. And a second timer having a time value greater than the first set value when the trigger signal is input when the time value is less than or equal to the first set value.
Since an abnormality detection unit that outputs an abnormal signal when the set value of is reached, is detected as an abnormality both in the case of being triggered before the set time and when the set time has elapsed since the trigger. can do.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration in an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between time t and a count value CNT in one embodiment of the present invention.

[Explanation of symbols]

 1 Oscillator (time measuring means) 2 Counter (time measuring means) 3 Setting device (time measuring means) 4 Large / small comparator (abnormality detecting means) 5 AND gate (abnormality detecting means) 6 Setting device (time measuring means) 7 OR gate (abnormality detecting means) T1, T2 set value.

Claims (1)

[Claims] 1. A clocking means (1, 1) for starting clocking from a clock value "0" by inputting a trigger signal indicating the start of program execution and outputting the clock value at each time point.
2, 3, 6), and when the trigger signal is input when the time count value is equal to or lower than the first set value (T1) and the second set value in which the time count value is larger than the first set value. A watchdog timer, comprising: abnormality detection means (4, 5, 7) that outputs an abnormality signal when the value (T2) is reached.