JPH0622221A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To attain high S/N for the solid-state image pickup element by setting a switch at a post-stage of an emitter terminal of a transistor(TR) of a sensor stage to be OFF for a forward bias storage period of the sensor TR. CONSTITUTION:A switch circuit QSW is arranged and connected between an emitter terminal of a photo transistor(TR) QH and a common terminal of MOS TRs QN1, QN2. The switch circuit QSW is turned off excepting when the TR QN1 is turned on and the TR QN2 is turned on, that is, but when reset signals phiT, phiERS turn respectively off the TRs QN1, QN2. That is, only one switch QSW is connected in parallel with an emitter terminal of the photo TR QH and the switch QSW is turned off for the storage period to minimize the emitter parasitic capacitance Cp during the storage period. Thus, the charging charge qp is minimized, the voltage drop VR at the base is minimized and inter-element dispersion DELTAVR of the VR is minimized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device such as a forward bias image sensor (BASIS).

[0002]

2. Description of the Related Art A basic circuit diagram of a conventional forward bias storage type BASIS and a driving timing diagram thereof are shown in FIGS. 1 and 2, respectively. The basic circuit is a bipolar type phototransistor Q _H , a pMOS transistor Q _P connected to its base, an nMOS transistor Q _N1 connected to the emitter of Q _H , a storage capacitor C _T, and an emitter of the transistor Q _H. NMOS transistor Q _N2 connecting the storage capacitor C _T with the storage capacitor C _T
And an nMOS transistor Q connected to the storage capacitor C _T
It is composed of _N3 and. Further, C _P is a transistor Q _H
Is the parasitic capacitance of the emitter of.

A timing chart of the basic operation and typical voltage waveforms of the base and emitter of the transistor Q _H are shown in FIG. Here, a sequence of basic operations, that is, a reset operation of the storage capacitor C _T , a clamp reset, a transient reset, a forward bias storage operation, and a read operation are shown. In the reset operation of C _T , the pulse signal Φ _CR causes the capacitance C _T to be at the ground potential through Q _N3 of the nMOS. The clamp reset operation, the base potential of the bipolar phototransistors Q _H through pMOS of Q _p by the signal [Phi _BRS is clamped to V _BB. At this time, the emitter of the phototransistor Q _H is kept in a floating state. In the subsequent transient reset operation (duration of t _F ), the emitter of the phototransistor Q _H is clamped to the emitter reset voltage V _ER through the nMOS transistor Q _N1 .
During this operation, the base of the phototransistor Q _H is in a floating state, so that the base voltage V _B of the phototransistor Q _H converges to a certain voltage V _Bi at the end of the transient reset period. Such a child is shown in FIG.

A combination of the clamp reset operation and the transient reset operation is called a hybrid reset operation. The forward bias accumulation operation starts at the same time as the end of this transient reset. Accumulation operation (illumin
ate) (period t _s in FIG. 2), the base and emitter of the phototransistor Q _H are floating and the base-emitter is shallowly forward biased. At the first stage of this accumulation operation, the emitter voltage rises rapidly as shown in FIG. This is because the phototransistor Q _H charges the minute parasitic capacitance C _P in a short time. As a result, the base voltage also sharply rises due to positive feedback through the capacitance between the base and the emitter. During the accumulation operation period, the base and emitter voltages of the phototransistor Q _H gradually increase as shown in FIG. 2 even in the absence of light, that is, in the dark state. This is because the shallow forward biased phototransistor Q _H continues to charge the parasitic capacitance C _p. When light is incident on the phototransistor Q _H , the base voltage increases linearly as shown in FIG. 2, and the emitter voltage also increases according to the base voltage.

During a read operation (t_RPeriod), phototra
Register Q_HEmitter and storage capacitance C_T Is the nMOS tiger
Register Q_N2Connected through. During read operation
The time base and emitter voltages of the are shown in Figure 2.
There is. Very short time in the initial stage of read operation
Among them, the emitter voltage is the storage capacitance C_TImmediately after reset potential
A sudden drop to ground potential. This descent time is R_on・
C_P Given in. Where R_onIs an nMOS transistor
Q_N2On-resistance of the emitter parasitic capacitance C of the emitter _P Is accumulated
Capacity C_T The descent time is very short compared to
It will be a good time. This sudden drop in emitter voltage
・ Base voltage by capacitive coupling through capacitance between emitters
To drop. However, the phototransistor is sufficient
Forward bias is applied to the base-emitter junction
The emitter voltage drops suddenly as described above.
Storage capacity C below_TFast enough with sufficient emitter current
To charge.

As a result, the signal voltage generated on the base of the phototransistor during the previous storage period is read to the storage capacitor C _T. At this time, the signal charge q _B generated based just before being read, the generated signal voltages V _S, when the base capacitance and _{C B, q B = C B} · V S
......................................... (1) given, on the other hand, occurred on the capacitance C _T after reading The electric charge q _CT is q _CT = (C _T + C _p ) · V _S
......................................... (2) is given. Therefore, the charge amplification factor β before and after reading is given by q _CT / q _B , and its value is q _CT / q _B = (C _T + C _P ) / C _B
............... (3) That is, the charge amplification corresponding to the capacitance ratio of (C _T + C _P ) and C _B is performed.

[0007]

However, such a conventional circuit has the following problems.
As shown in FIG. 2, during the storage (STORAGE) operation,
Since the base and emitter of the transistor Q _H are both floating, and the base-emitter is forward-biased shallowly, the operating point of the phototransistor gradually increases toward the low current region side even with the increase of the accumulation time even in the dark state. Changes to.

When the voltage charged in the parasitic capacitance C _P during such an accumulation period is VP, the charge amount q _P is q _P = C _P · V _P
............................... (4)

At this time, at the base of the phototransistor Q _H , the charge q _R corresponding to q _P / h _FE is lost due to the recombination effect. h _FE is the amplification factor of the phototransistor. Therefore, the voltage V _R lost at the base of the transistor Q _H
V _R = q _R / C _B = (q _P / h _FE ) · (1 /
C _B ) .................... (5)

[0010] Generally, in h _FE vs. i _c characteristics of the phototransistor decreases the collector current i _c is, enough to be a low current region, h _FE is reduced, and the degree of the decrease can greatly fluctuate for each element Are known. Therefore, during the accumulation period, V _R gradually increases, and the variation ΔV _R of V _R among the elements also increases. The occurrence of such a variation ΔV _R between the elements is treated as fixed pattern noise (FRN) in the solid-state imaging device, and becomes a very important problem that deteriorates S / N.

As a method for solving such a problem,
For example, the phototransistor h_FEPair i _cCharacteristics of T current region
(I_cUp to 100 nA)_FEIs flat and plain
It is considered to reduce the variation between children
However, this requires optimization of the device structure and manufacturing process.
Is necessary, and it is difficult to make significant improvements in a short period of time. Therefore
As another method, in equation (5), the parasitic capacitance C_PCharge to
Charge q_PIt is possible to make itself small. This
Here parasitic capacitance C_PIs a phototransistor Q_HTo the emitter of
MOS transistor (Q_N1, Q_N2, Q_N3)
of The main cause is all drain junction capacitance.

[0012]

Therefore, according to the present invention, in a forward bias storage type solid-state image pickup device, only one switch is arranged and connected after the emitter terminal of the transistor of the sensor stage. The switch is in an off state during the forward bias accumulation period of the sensor transistor.

[0013]

According to the above structure, the parasitic capacitance C _P during the accumulation period of the emitter of the sensor stage transistor can be minimized. As a result, it is possible to minimize the electric charge q _P, to minimize voltage drop V _R at the base, to minimize inter-element variation [Delta] V _R of the end V _R.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 3 shows this embodiment.
In the figure, the same reference numerals as in FIG. 1 denote the same elements. Phototransistor Q _H emitter terminal and Q _N1
And a common terminal between Q _N2 and one switch circuit Q _SW
Are arranged and connected. This switch Q _SW is not when Q _N1 is on and when Q _N2 is on, that is,
When the reset signals Φ _T and Φ _ERS turn off Q _N1 and Q _N2 , respectively, they are turned off. The embodiment of FIG.
Since it is intended to perform the same operation so as to maintain compatibility with the circuit of the conventional example shown in FIG. 1, its operation timing diagram is exactly the same as that of FIG.

Thus, according to the image pickup apparatus of this embodiment,
The emitter terminal of the phototransistor Q _H has only one switch Q _SW arranged in parallel and connected, and is turned off during the accumulation period to minimize the emitter parasitic capacitance C _P during the accumulation period. can do. As a result, it is possible to minimize the electric charge q _P, to minimize voltage drop V _R at the base, to minimize inter-element variation [Delta] V _R of the end V _R.

Therefore, fixed pattern noise can be reduced without changing the element structure or process, and a high S / N solid-state image pickup device can be provided. In the embodiment of FIG. 3, two MOS transistors Q _N1 and Q _N2 are connected after Q _SW , but the present invention is only parallel to the emitter terminal of the sensor transistor in the solid-state image sensor. Since there is a feature that only one switch is arranged and connected, there may be any number of transistors after the sensor transistor.

[0017]

According to the forward bias storage type solid-state image pickup device of the present invention described above, only one switch is arranged and connected after the emitter terminal of the transistor of the sensor stage, and the switch is Since the sensor transistor is in the OFF state during the forward bias accumulation period, the parasitic capacitance C _P during the accumulation period of the emitter of the sensor stage transistor can be minimized. As a result, the charge charge q _P is minimized, the voltage drop V _R at the base is minimized, and eventually V _R
It is possible to minimize the variation ΔV _R between elements. Specifically, for example, fixed pattern noise generated during the forward bias accumulation period can be reduced without changing the element structure or process of the phototransistor, and the S / N ratio of the solid-state imaging device can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a conventional solid-state imaging device.

FIG. 2 is a diagram showing waveforms of respective parts in the image pickup apparatus of FIG.

FIG. 3 is a block diagram of an image pickup apparatus according to an embodiment of the present invention.

Claims (2)

[Claims] 1. A forward bias storage type solid-state imaging device, wherein a switch is arranged and connected after an emitter terminal of a transistor of a sensor stage, and the switch is in an off state during a forward bias storage period of the sensor transistor. A characteristic solid-state imaging device. 2. The solid-state imaging device according to claim 1, wherein the first-stage transistor of the sensor stage is a bipolar type.