JPH06216856A - Timing extracting circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunctions of circuits of the following stages by providing the hysteresis characteristic to a comparator connected to a filter and fixing the output signal at a specific voltage level when the input signal of the comparator has a reference voltage level. CONSTITUTION:A signal including a timing component of frequency fo is supplied to an input terminal 1, and a filter 2 connected to the terminal 1 defines the frequency fo as its pass band. Meanwhile the negative phase input terminal of a comparator 3 is connected to the filter 2, and a 1st resistance 6 of resistance value R1 is connected between the output terminal and the positive phase input terminal of the comparator 3. Then a 2nd resistance 7 of resistance value R2 is connected between the positive phase input terminal of the comparator 3 and a reference voltage source 4 respectively. Then the hysteresis characteristic is given to the comparator 3. Thus the output signal of the comparator 3 is fixed at Eo+ Vb or Eo+ Vb when the input signal of the comparator 3 is set at the voltage value Eo of the source 4 by a sine wave of frequency fo with which an input signal Vin vibiates by an amplitude of + or - Ub centering on the value Eo of the source 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing component extraction circuit for an optical receiver.

[0002]

BACKGROUND OF THE INVENTION FIG. 3, a configuration of a conventional timing extracting circuit, an input terminal, 2 is passed through a frequency f _O band 1 is the signal including timing component of frequency f _O in the figure is input When the negative-phase input terminal voltage is lower than the positive-phase input terminal voltage, the output voltage of _Eo
-ΔV _b , and when the negative-phase input terminal voltage is higher than the positive-phase input terminal voltage, the output voltage becomes E _O + ΔV _b Comparator, 4 is a reference voltage source of voltage value E _O , 5 is the timing of frequency f _O An output terminal from which a signal is output.

Next, the operation will be described. Signal including timing component of frequency f _O that is input to the input terminal 1, the filter 2, the passband frequency f _O,
Frequency only the signal components of f _O is input to the comparator 3.
Now, let the input signal to the comparator 3 be v _in and the output signal be v _out . The input signal v _in is a sine wave with a frequency f _O that oscillates around the voltage value E _o of the reference voltage source 4 with an amplitude of ± Δv _b ,
In the case of a signal interruption, if the voltage value has a characteristic of E _O , the output signal v _out is a square wave of frequency f _O that oscillates around the voltage value E _O with an amplitude of ± ΔV _b when a signal exists. so,
In the case of a signal interruption, the value is either E _O + ΔV _b or E _O −ΔV _b , but the state cannot be predicted. In addition, the voltage value E
_If only a small amount of extraneous noise is superimposed on _O , the output signal v
_Out oscillates between two values of E _O + ΔV _b and E _O −ΔV _b . The above characteristics are shown in FIG.

[0004]

Since the conventional timing extraction circuit is constructed as described above, when there is no signal, that is, when v _in is E _O V, the output v _out2 is E _O + ΔV _b.
However, there is a problem in that the two values of E _{o and} ΔV _b become uncertain, and the circuit in the subsequent stage connected to this timing extraction circuit malfunctions.

The present invention has been made in order to solve the above problems, and when there is no signal, that is, v _in is E _o.
The purpose is to obtain a timing extraction circuit in which the circuit output is determined to be either E _O + ΔV _b or E _O −ΔV _b when V.

[0006]

In the timing extraction circuit according to the present invention, a comparator connected to a filter has a hysteresis characteristic, and when the comparator input signal is E _O V, the output signal is E _O + ΔV _b. Or E _O −ΔV _b .

[0007]

In the timing extracting circuit according to the present invention, since the circuit output is determined to be either E _O + ΔV _b or E _O −ΔV _b when there is no signal, the circuit in the subsequent stage does not malfunction.

[0008]

Embodiment 1 An embodiment of the present invention will be described below with reference to the drawings. Figure 1
6 is a first resistor having a resistance value R1 connected between the output terminal of the comparator 3 and the positive phase input terminal, and 7 is the comparator 3
Is a second resistor having a resistance value R2 connected between the positive-phase input terminal of and the reference voltage source 4.

Next, the operation will be described. Input terminal 1,
The operation of the filter 2 is similar to that of the conventional embodiment. The comparator 3 uses the positive feedback loop formed by the first resistor 6 and the second resistor 7 to form the positive-phase input terminal voltage V _{th of the} comparator 3.
Depending on the output state of the comparator 3,

[0010]

[Equation 1]

[0011]

[Equation 2]

The input signal v _in is the voltage value E _{O of the} reference voltage source 4.
Is a sine wave with a frequency f _O that oscillates with an amplitude of ± Δv _b around, and the voltage value becomes E _O in the case of a signal interruption, and Δv _b satisfies the following equation:

[0013]

[Equation 3]

When a signal is present, the output signal v _out is a square wave with a frequency f _O that oscillates around the voltage value E _O with an amplitude of ± ΔV _b. Confirm the state of. In addition, the voltage value E _O is ± R2 · V _b /
(R1 + R2) If the following is satisfied, the output signal v _out does not vibrate even when external noise is superimposed, and is stable at a constant value. The above characteristics are shown in FIG.

[0015]

As described above, according to the present invention, since the comparator is provided with the hysteresis characteristic, it operates so that the output maintains a constant value even when there is no signal or a little noise is input.
There is an effect that the circuit in the subsequent stage does not malfunction.

[Brief description of drawings]

FIG. 1 is a block diagram showing a timing extraction circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing input / output characteristics in the timing extraction circuit according to the embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional timing extraction circuit.

FIG. 4 is a diagram showing input / output characteristics in a conventional timing extraction circuit.

[Explanation of symbols]

 1 Input Terminal 2 Filter 3 Comparator 4 Reference Voltage Source 5 Output Terminal 6 First Resistor 7 Second Resistor

Claims (1)

[Claims] An input terminal 1. A frequency signal including the timing component of f _O is inputted, a filter for a connected frequency f _O passband to the input terminal, to the filter, its negative phase input A comparator to which a terminal is connected, a first resistor connecting the output end of the comparator and a positive phase input terminal of the comparator, a reference voltage source, a positive phase input terminal of the comparator, A timing extraction circuit comprising: a second resistor that connects to a reference voltage source; and an output terminal that outputs a timing signal having a frequency f _O.