JPH0621655A - Manufacture of ceramic circuit board - Google Patents

Manufacture of ceramic circuit board

Info

Publication number
JPH0621655A
JPH0621655A JP17400292A JP17400292A JPH0621655A JP H0621655 A JPH0621655 A JP H0621655A JP 17400292 A JP17400292 A JP 17400292A JP 17400292 A JP17400292 A JP 17400292A JP H0621655 A JPH0621655 A JP H0621655A
Authority
JP
Japan
Prior art keywords
powder
circuit board
ceramic circuit
via hole
conductive powder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP17400292A
Other languages
Japanese (ja)
Inventor
Hiroki Someta
博樹 染田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17400292A priority Critical patent/JPH0621655A/en
Publication of JPH0621655A publication Critical patent/JPH0621655A/en
Withdrawn legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PURPOSE:To improve packing density and reduce the electric resistance of an interlayer conductor path or to prevent corrosion of it, through the blocking penetration of chemical solvent, etc., in post-process, by liquid-phase-baking conductive powder for improving packing density of it, in manufacture of a multilayer ceramic circuit board used far electronic equipments such as a computer, etc. CONSTITUTION:In the manufacturing method of a ceramic circuit board in which a via hole 2 is opened on a green sheet 1, formed by adding ceramic powder with a plastic agent, solvent, etc., and after that, the via hole 2 is packed with conductive powder, for baking, the conductive powder to be packed into the via hole 2 is mixed with at least one kind of metal powder which melts during baking, and thus obtained conductive powder 3 is liquid-phase- baked. However, at least a part of the metal powder that melts during baking can be replaced with alloy powder or glass powder.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、セラミック回路基板、
特に、コンピュータ等の電子機器に用いられる多層セラ
ミック回路基板の製造方法に関する。
BACKGROUND OF THE INVENTION The present invention relates to a ceramic circuit board,
In particular, the present invention relates to a method for manufacturing a multilayer ceramic circuit board used in electronic devices such as computers.

【0002】[0002]

【従来の技術】最近、コンピュータ等の電子機器の動作
が高速化されるに伴い、これらの回路を構成するセラミ
ック回路基板のバイアホール中に充填され、このセラミ
ック回路基板の表面に形成される配線層間を接続する層
間導体路を低抵抗化することが望まれている。
2. Description of the Related Art Recently, as electronic devices such as computers have become faster in operation, wirings filled in via holes of ceramic circuit boards constituting these circuits and formed on the surface of the ceramic circuit boards. It is desired to reduce the resistance of the interlayer conductor path connecting the layers.

【0003】従来から、低抵抗材料としては銅が多用さ
れており、セラミック回路基板のバイアホール中に充填
した銅粉末を焼結することによって一体化して、セラミ
ック回路基板の表面に形成された配線層の層間導体路を
形成している。従来の方法では、銅粉末の粒径あるいは
形状を変えて、銅粉末同士の接触面積を増大させること
によって、充填密度を向上させて層間導体路の低抵抗化
を図っていた。
Conventionally, copper is often used as a low resistance material, and wiring formed on the surface of a ceramic circuit board is integrated by sintering copper powder filled in via holes of the ceramic circuit board. Forming the inter-layer conductor tracks of the layers. In the conventional method, the particle size or shape of the copper powder is changed to increase the contact area between the copper powders, thereby improving the packing density and reducing the resistance of the interlayer conductor path.

【0004】[0004]

【発明が解決しようとする課題】ところが、この従来の
方法では粉末の焼結が固相焼結であるため、充填密度の
向上には限界があり、焼結後の層間導体路内に空隙が残
り、低抵抗化できないという問題があった。
However, since the sintering of the powder is solid-phase sintering in this conventional method, there is a limit to the improvement of the packing density, and voids are formed in the interlayer conductor paths after sintering. The remaining problem was that the resistance could not be lowered.

【0005】また、この層間導体路内の空隙に、後の工
程、例えば、セラミック回路基板表面を研磨する工程で
使用する化学溶剤等が浸透し易くなり、導体が経時的に
腐食して電気抵抗を増大したり、さらには断線するとい
った問題も生じていた。
Further, a chemical solvent or the like used in a later step, for example, a step of polishing the surface of the ceramic circuit board, easily penetrates into the voids in the interlayer conductor path, and the conductor corrodes with time, resulting in electrical resistance. There was also a problem of increasing the number of wires and even breaking the wire.

【0006】本発明においては、導電性粉末を液相焼結
することによって、層間導体路の充填密度を向上させ、
層間導体路の電気抵抗を低減し、あるいは、後工程にお
ける化学溶剤等の浸透を妨げて層間導体路の腐食を防止
することを目的とする。
In the present invention, the packing density of the inter-layer conductor paths is improved by liquid-sintering the conductive powder,
The purpose of the present invention is to reduce the electric resistance of the interlayer conductor path or prevent corrosion of the interlayer conductor path by preventing the permeation of a chemical solvent or the like in the subsequent step.

【0007】[0007]

【課題を解決するための手段】本発明にかかるセラミッ
ク回路基板の製造方法においては、上記の問題を解決す
るために、セラミック粉末に可塑剤、溶剤等を添加して
形成したグリーンシートにバイアホールを穿設し、該バ
イアホールに導電性粉末を充填して焼成するセラミック
回路基板の製造方法において、該バイアホールに充填す
る導電性粉末に焼成中に溶融する金属粉末を一種以上混
合して該導電性粉末を液相焼結する工程を採用した。
In the method for manufacturing a ceramic circuit board according to the present invention, in order to solve the above problems, a via hole is formed in a green sheet formed by adding a plasticizer, a solvent and the like to ceramic powder. In the method for manufacturing a ceramic circuit board, in which the via hole is filled with conductive powder and fired, the conductive powder filled in the via hole is mixed with one or more metal powders that are melted during firing. The step of liquid phase sintering the conductive powder was adopted.

【0008】この場合、焼成中に溶融する金属粉末の少
なくとも一部を、焼成中に溶融する金属合金粉末に置き
換えることができる。
In this case, at least a part of the metal powder that melts during firing can be replaced with the metal alloy powder that melts during firing.

【0009】この場合、焼成中に溶融する金属粉末の少
なくとも一部を、焼成中に溶融する一種以上のガラス粉
末に置き換えることができる。
In this case, at least part of the metal powder that melts during firing can be replaced with one or more glass powders that melt during firing.

【0010】これらの場合、バイアホールに導電性粉末
を充填し、その表面に配線層を形成したグリーンシート
を複数層積層した後に焼成して、多層回路基板を形成す
ることができる。
In these cases, a multilayer circuit board can be formed by filling a via hole with conductive powder, laminating a plurality of green sheets having wiring layers formed on the surface thereof, and firing the green sheets.

【0011】これらの場合、導電性粉末に混合する、焼
成中に溶融する金属粉末あるいはガラス粉末の混合割合
を24Vol%以下に抑えることが望ましい。
In these cases, it is desirable to keep the mixing ratio of the metal powder or the glass powder, which is mixed with the conductive powder and melted during firing, to 24 Vol% or less.

【0012】[0012]

【作用】本発明により、導電性粉末、例えば銅粉末に焼
成中に溶融する金属粉末またはガラス粉末を混合するこ
とによって、導電性粉末の焼結を液相焼結にして、層間
導体路の充填密度の向上を図ることができる。
According to the present invention, conductive powder, for example, copper powder, is mixed with metal powder or glass powder which is melted during firing to transform the conductive powder into liquid phase sintering to fill interlayer conductor paths. It is possible to improve the density.

【0013】液相焼結とは、焼結過程で一部分液相が存
在する状態で焼結を行うことであり、この場合、残留固
相粒子の間隙に液相が浸透する過程で著しい収縮が起こ
り、また固相の溶解、析出等も起こるため極めて緻密な
焼結体が得られる。
Liquid phase sintering means that sintering is carried out in a state where a liquid phase partially exists in the sintering process. In this case, significant contraction occurs in the process in which the liquid phase penetrates into the gaps between the residual solid phase particles. As a result, solid phase dissolution, precipitation, etc. also occur, so that an extremely dense sintered body can be obtained.

【0014】導電性粉末に低融点金属、ガラス等を混合
していない従来技術によると、銅粉末の焼成後の空隙率
は24%であった。したがって、24%以上の、焼成中
に溶融する金属粉末、あるいは、ガラス粉末を混合する
と、本来導電体として機能する銅粉末の一部が低融点金
属あるいはガラスによって置換されることになるから、
層間導電路の電気抵抗が増大することになる。
According to the prior art in which the conductive powder is not mixed with a low melting point metal, glass, etc., the porosity of the copper powder after firing was 24%. Therefore, when 24% or more of metal powder that melts during firing or glass powder is mixed, a part of the copper powder that originally functions as a conductor will be replaced by the low-melting metal or glass,
The electrical resistance of the interlayer conductive path will increase.

【0015】[0015]

【実施例】以下、本発明の実施例を説明する。 (第1実施例)図1(A)〜(E)は、第1実施例のセ
ラミック回路基板の製造工程説明図である。この図にお
いて、1はグリーンシート、2はバイアホール、3は銅
ビスマス混合粉末、4は配線パターン、5は積層体、6
は多層セラミック回路基板、7は層間導体路である。こ
の実施例によるセラミック回路基板の製造工程を説明す
る。
EXAMPLES Examples of the present invention will be described below. (First Embodiment) FIGS. 1 (A) to 1 (E) are views for explaining a manufacturing process of a ceramic circuit board according to the first embodiment. In this figure, 1 is a green sheet, 2 is a via hole, 3 is a copper-bismuth mixed powder, 4 is a wiring pattern, 5 is a laminated body, 6
Is a multilayer ceramic circuit board, and 7 is an interlayer conductor path. The manufacturing process of the ceramic circuit board according to this embodiment will be described.

【0016】第1工程(図1(A)参照) アルミナ230g、ホウケイ酸ガラス230g、シリカ
ガラス230g、可塑剤、バインダを加えて混練してス
ラリー状にする。このスラリーを脱泡処理した後、ドク
ターブレード法によって成形して厚さ300μmのグリ
ーンシート1を形成する。
First step (see FIG. 1A) 230 g of alumina, 230 g of borosilicate glass, 230 g of silica glass, a plasticizer and a binder are added and kneaded to form a slurry. After defoaming this slurry, it is molded by a doctor blade method to form a green sheet 1 having a thickness of 300 μm.

【0017】第2工程(図1(B)参照) 第1工程によって形成したグリーンシート1にバイアホ
ール2を形成し、このバイアホール2に、銅粉末90V
ol%、ビスマス粉末10Vol%を含む混合粉末3を
充填する。
Second step (see FIG. 1B) A via hole 2 is formed in the green sheet 1 formed in the first step, and 90 V of copper powder is formed in the via hole 2.
The mixed powder 3 containing ol% and 10 vol% of bismuth powder is filled.

【0018】第3工程(図1(C)参照) このグリーンシートの表面に、銅ペーストによって、必
要な形状の配線パターン4をスクリーン印刷する。
Third step (see FIG. 1C) A wiring pattern 4 having a required shape is screen-printed on the surface of the green sheet with a copper paste.

【0019】第4工程(図1(D)参照) 第3工程によって形成されたグリーンシート1,1を複
数層積層し、プレスすることによって積層体5を形成す
る。
Fourth Step (See FIG. 1D) A plurality of green sheets 1, 1 formed in the third step are laminated and pressed to form a laminate 5.

【0020】第5工程(図1(E)参照) 第4工程によって形成された積層体5を窒素中で焼成し
て多層セラミック回路基板6にする。この焼成によっ
て、銅粉末が液相焼結され、その空隙にビスマスが充填
された高密度の層間導体路7が形成される。
Fifth Step (See FIG. 1E) The laminated body 5 formed in the fourth step is fired in nitrogen to form a multilayer ceramic circuit board 6. By this firing, the copper powder is liquid-phase sintered to form the high-density interlayer conductor path 7 in which the voids are filled with bismuth.

【0021】このように、従来技術によると空隙であっ
た部分にビスマスが充填されるため、後の工程による化
学溶剤等の浸透を防ぐことができる。上記の説明におい
ては、ビスマス粉末を用いたが、In,Pb,Sn等他
の低融点の金属を用いることができる。
As described above, according to the conventional technique, the vacant spaces are filled with bismuth, so that it is possible to prevent the permeation of the chemical solvent and the like in the subsequent steps. Although bismuth powder is used in the above description, other low melting point metals such as In, Pb and Sn can be used.

【0022】(第2実施例)この実施例によるセラミッ
ク回路基板の製造工程を説明する。
(Second Embodiment) A manufacturing process of a ceramic circuit board according to this embodiment will be described.

【0023】第1工程 アルミナ230g、ホウケイ酸ガラス230g、シリカ
ガラス230g、可塑剤、バインダを加えて混練してス
ラリー状にする。このスラリーを脱泡処理した後、ドク
ターブレード法によって成形して厚さ300μmのグリ
ーンシートを形成する。
First step: 230 g of alumina, 230 g of borosilicate glass, 230 g of silica glass, a plasticizer and a binder are added and kneaded to form a slurry. After defoaming the slurry, the slurry is molded by a doctor blade method to form a green sheet having a thickness of 300 μm.

【0024】第2工程 第1工程によって形成したグリーンシートにバイアホー
ルを形成し、このバイアホールに、銅粉末90Vol
%、スズ(Sn)38%鉛(Pb)合金(はんだ)粉末
10Vol%を含む混合粉末を充填する。
Second Step A via hole is formed in the green sheet formed in the first step, and 90 Vol of copper powder is filled in the via hole.
%, Tin (Sn) 38% lead (Pb) alloy (solder) powder 10 vol%, and a mixed powder is filled.

【0025】第3工程 このグリーンシートの表面に、銅ペーストによって配線
パターンをスクリーン印刷する。
Third Step A wiring pattern is screen-printed on the surface of the green sheet with a copper paste.

【0026】第4工程 第3工程によって形成されたグリーンシートを複数層積
層し、プレスして積層体を形成する。
Fourth Step A plurality of green sheets formed in the third step are laminated and pressed to form a laminate.

【0027】第5工程 第4工程によって形成された積層体を窒素中で焼成して
多層基板とする。この焼成によって、銅粉末が低融点の
Sn−Pb合金の存在の下で液相焼結されるため、高密
度で空隙の少ない層間導体路が形成される。
Fifth Step The laminated body formed in the fourth step is fired in nitrogen to obtain a multilayer substrate. By this firing, the copper powder is liquid-phase sintered in the presence of the Sn-Pb alloy having a low melting point, so that an interlayer conductor path having high density and few voids is formed.

【0028】このように、従来技術によると空隙であっ
た部分にSn−Pb合金が充填されるため、後の工程に
よる化学溶剤等の浸透を防ぐことができ、かつ、空隙を
合金で埋める分だけ電気抵抗を低減することができる。
なお、前記のSn−Pb合金の他に、Sn−Au,Sn
−Ag,Sn−Sb,Au−Si,Au−Ge等を用い
ることができる。
As described above, since the Sn-Pb alloy is filled in the portion which is the void according to the conventional technique, the permeation of the chemical solvent or the like in the subsequent step can be prevented, and the void is filled with the alloy. Only the electric resistance can be reduced.
In addition to the above Sn-Pb alloy, Sn-Au, Sn
-Ag, Sn-Sb, Au-Si, Au-Ge, etc. can be used.

【0029】(第3実施例)この実施例によるセラミッ
ク回路基板の製造工程を説明する。
(Third Embodiment) A process for manufacturing a ceramic circuit board according to this embodiment will be described.

【0030】第1工程 アルミナ230g、ホウケイ酸ガラス230g、シリカ
ガラス230g、可塑剤、バインダを加えて混練してス
ラリー状にし、脱泡処理した後、ドクターブレード法に
よって成形して厚さ300μmのグリーンシートを形成
する。
First step: 230 g of alumina, 230 g of borosilicate glass, 230 g of silica glass, plasticizer and binder are added and kneaded to form a slurry, which is then defoamed and then molded by a doctor blade method to obtain a green having a thickness of 300 μm. Form a sheet.

【0031】第2工程 第1工程によって形成したグリーンシートにバイアホー
ルを形成し、このバイアホールに、銅粉末90Vol
%、ガラス粉末10Vol%を含む混合粉末を充填す
る。
Second Step A via hole is formed in the green sheet formed in the first step, and 90 Vol of copper powder is filled in the via hole.
%, And a mixed powder containing 10% by volume of glass powder.

【0032】第3工程 第2工程によって形成したグリーンシートの表面に、銅
ペーストによって必要な配線パターンを形成する。
Third Step On the surface of the green sheet formed in the second step, a necessary wiring pattern is formed with copper paste.

【0033】第4工程 第3工程によって形成されたグリーンシートを複数層積
層し、プレスして積層体を形成する。
Fourth Step A plurality of green sheets formed in the third step are laminated and pressed to form a laminate.

【0034】第5工程 第4工程によって形成された積層体を窒素中で焼成して
多層基板とする。この焼成によって、銅粉末が焼結さ
れ、従来技術によると空隙であった部分にガラスが充填
されるため、後の工程による化学溶剤等の浸透を防ぎ、
層間導電路の劣化を防ぐことができる。
Fifth Step The laminated body formed in the fourth step is fired in nitrogen to form a multilayer substrate. By this firing, the copper powder is sintered, and according to the conventional technology, glass is filled in the part that was a void, so that the permeation of a chemical solvent or the like in a later step is prevented,
It is possible to prevent deterioration of the interlayer conductive path.

【0035】[0035]

【発明の効果】以上説明したように、本発明によると、
銅粉末等の導電性粉末の焼成時に溶融する金属粉末を一
種類以上混合することにより、焼結を液相焼結とし、高
密度で空隙のより少ない導体を形成することが可能にな
る。
As described above, according to the present invention,
By mixing one or more kinds of metal powders that melt during firing of conductive powder such as copper powder, it becomes possible to form liquid phase sintering and form a conductor with high density and less voids.

【0036】この導電性粉末に混合する焼成中に溶融す
る金属粉末の一部を、焼成中に溶融する合金粉末あるい
は焼成中に溶融するガラス粉末に置き換えても、ほぼ同
様の効果が得られる。したがって、セラミック回路基
板、特に、多層セラミック回路基板の信頼性向上に寄与
するところが大きい。
Even if a part of the metal powder that is melted during firing mixed with the conductive powder is replaced with an alloy powder that melts during firing or a glass powder that melts during firing, almost the same effect can be obtained. Therefore, it greatly contributes to the improvement of the reliability of the ceramic circuit board, especially the multilayer ceramic circuit board.

【図面の簡単な説明】[Brief description of drawings]

【図1】(A)〜(E)は第1実施例のセラミック回路
基板の製造工程説明図である。
1A to 1E are explanatory views of a manufacturing process of a ceramic circuit board according to a first embodiment.

【符号の説明】 1 グリーンシート 2 バイアホール 3 銅ビスマス混合粉末 4 配線パターン 5 積層体 6 多層セラミック回路基板 7 層間導体路[Explanation of symbols] 1 green sheet 2 via hole 3 copper-bismuth mixed powder 4 wiring pattern 5 laminated body 6 multilayer ceramic circuit board 7 interlayer conductor path

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 セラミック粉末に可塑剤、溶剤等を添加
して形成したグリーンシートにバイアホールを穿設し、
該バイアホールに導電性粉末を充填して焼成するセラミ
ック回路基板の製造方法において、該バイアホールに充
填する導電性粉末に焼成中に溶融する金属粉末を一種以
上混合して該導電性粉末を液相焼結することを特徴とす
るセラミック回路基板の製造方法。
1. A via hole is formed in a green sheet formed by adding a plasticizer, a solvent and the like to ceramic powder,
In a method for manufacturing a ceramic circuit board in which conductive powder is filled in the via hole and fired, one or more metal powders that are melted during firing are mixed with the conductive powder filled in the via hole to form a liquid solution of the conductive powder. A method of manufacturing a ceramic circuit board, which comprises performing phase sintering.
【請求項2】 焼成中に溶融する金属粉末の少なくとも
一部を、焼成中に溶融する金属合金粉末に置き換えるこ
とを特徴とする請求項1に記載されたセラミック回路基
板の製造方法。
2. The method for manufacturing a ceramic circuit board according to claim 1, wherein at least a part of the metal powder that melts during firing is replaced with a metal alloy powder that melts during firing.
【請求項3】 焼成中に溶融する金属粉末の少なくとも
一部を、焼成中に溶融する一種以上のガラス粉末に置き
換えることを特徴とする請求項1に記載されたセラミッ
ク回路基板の製造方法。
3. The method of manufacturing a ceramic circuit board according to claim 1, wherein at least a part of the metal powder that melts during firing is replaced with one or more glass powders that melt during firing.
【請求項4】 バイアホールに導電性粉末を充填し、そ
の表面に配線層を形成したグリーンシートを複数層積層
した後に焼成することを特徴とする請求項1ないし請求
項3のいずれか1項に記載されたセラミック回路基板の
製造方法。
4. The via hole is filled with a conductive powder, and a plurality of green sheets having a wiring layer formed on the surface thereof are laminated and then fired. A method for manufacturing a ceramic circuit board described in 1.
【請求項5】 導電性粉末に混合する、焼成中に溶融す
る金属粉末あるいはガラス粉末の混合割合が24Vol
%以下であることを特徴とする請求項1ないし請求項4
のいずれか1項に記載されたセラミック回路基板の製造
方法。
5. The mixing ratio of the metal powder or the glass powder, which is mixed with the conductive powder and melts during firing, is 24 Vol.
% Or less, Claim 1 thru | or Claim 4 characterized by the above-mentioned.
A method for manufacturing a ceramic circuit board according to any one of 1.
JP17400292A 1992-07-01 1992-07-01 Manufacture of ceramic circuit board Withdrawn JPH0621655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17400292A JPH0621655A (en) 1992-07-01 1992-07-01 Manufacture of ceramic circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17400292A JPH0621655A (en) 1992-07-01 1992-07-01 Manufacture of ceramic circuit board

Publications (1)

Publication Number Publication Date
JPH0621655A true JPH0621655A (en) 1994-01-28

Family

ID=15970934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17400292A Withdrawn JPH0621655A (en) 1992-07-01 1992-07-01 Manufacture of ceramic circuit board

Country Status (1)

Country Link
JP (1) JPH0621655A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000046877A2 (en) * 1999-02-04 2000-08-10 Gul Technologies Singapore Ltd. Printed circuit boards with solid interconnect and method of producing the same
WO2020160343A1 (en) * 2019-01-31 2020-08-06 Samtec, Inc. Electrically conductive vias and methods for producing same
US11107702B2 (en) 2015-04-02 2021-08-31 Samtec, Inc. Method for creating through-connected vias and conductors on a substrate
US11646246B2 (en) 2016-11-18 2023-05-09 Samtec, Inc. Method of fabricating a glass substrate with a plurality of vias
US12009225B2 (en) 2018-03-30 2024-06-11 Samtec, Inc. Electrically conductive vias and methods for producing same
US12100647B2 (en) 2019-09-30 2024-09-24 Samtec, Inc. Electrically conductive vias and methods for producing same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000046877A2 (en) * 1999-02-04 2000-08-10 Gul Technologies Singapore Ltd. Printed circuit boards with solid interconnect and method of producing the same
WO2000046877A3 (en) * 1999-02-04 2002-06-13 Gul Technologies Singapore Ltd Printed circuit boards with solid interconnect and method of producing the same
US11107702B2 (en) 2015-04-02 2021-08-31 Samtec, Inc. Method for creating through-connected vias and conductors on a substrate
US11646246B2 (en) 2016-11-18 2023-05-09 Samtec, Inc. Method of fabricating a glass substrate with a plurality of vias
US12009225B2 (en) 2018-03-30 2024-06-11 Samtec, Inc. Electrically conductive vias and methods for producing same
WO2020160343A1 (en) * 2019-01-31 2020-08-06 Samtec, Inc. Electrically conductive vias and methods for producing same
US12100647B2 (en) 2019-09-30 2024-09-24 Samtec, Inc. Electrically conductive vias and methods for producing same

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A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19991005