JPH06216390A - Transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a TFT having small unevenness of transistor characteristics by increasing an effective channel length without increasing a cell size of a transistor, suppressing a short channel effect which becomes a problem in a fine TFT, and preventing a variation in the channel length due to misregistration of the resist pattern, etc. CONSTITUTION:The transistor comprises a gate electrode 28 formed in the bottom of a recess 26, a gate insulating layer 30 formed to be introduced into the recess 26, and a semiconductor layer 32 formed to be introduced into the recess 26 and laminated on the layer 30, wherein a channel region 34 is formed on the layer 32 part introduced into the recess 26. After a semiconductor layer 44 is so formed as to be introduced into the recess 26, an insulating layer 48 is buried only in the surface of the semiconductor layer, with the layer 48 as a mask impurity ions are implanted in the layer 44, and a channel region 50 is formed in a self-alignment with the semiconductor layer in the recess 26.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method of manufacturing the same, and more particularly, to a structure of a thin film transistor capable of increasing the effective channel length of the thin film transistor without increasing the size of the transistor and its manufacture. Regarding the method.

[0002]

2. Description of the Related Art A thin film transistor (TFT) is being developed as a load transistor of a static memory (SRAM) or a drive circuit of a liquid crystal device. TFT
Then, a channel region, a source region and a drain region of a MOS transistor are formed in a semiconductor layer made of polysilicon.

FIG. 9 shows a sectional structure of a main part of a conventional TFT. The TFT 2 shown in FIG. 9 is a T having a bottom gate structure.
FT, the gate electrode 6 is formed on the insulating layer 4, the surface thereof is covered with the gate insulating layer 8, and the semiconductor layer 10 formed of a polysilicon film or the like is formed on the surface of the gate insulating layer.
Are stacked. In the semiconductor layer 10, a channel region 12 is formed immediately above the gate electrode 6, and a source region is formed on both sides of the channel region 12.
Drain regions 14, 14 are formed.

[0004]

In such a TFT 2, the channel length of the channel region 12 is reduced with the miniaturization of the LSI, and the deterioration of the transistor characteristics such as the short channel effect becomes a problem.

In the conventional TFT, as a method for improving the short channel effect, it has been reported that the concentration of the source / drain regions is reduced and the thickness of the gate insulating layer is reduced. However, the former method may cause a problem of deterioration of the rising characteristics of the transistor due to deterioration of the S value due to the parasitic transistor, and the latter method may cause a problem of leakage through the gate insulating layer.
Each has merits and demerits, and other improvement methods have been required.

In addition, a TFT has also been developed, in which an offset structure is provided particularly in the drain region to weaken the electric field strength at the drain junction and prevent a drain leak current when the transistor is turned off. However, since this TFT uses an offset structure,
There are problems that the cell area of the transistor increases and the rising characteristics of the transistor deteriorate.

Further, with the miniaturization of TFTs, when ion implantation for forming a channel region and source / drain regions in a semiconductor layer is performed, a deviation of the channel region relative to the gate electrode is caused due to misalignment of resist patterns. And the effective channel length is further shortened.

The present invention has been made in view of the above circumstances, without increasing the cell size of a transistor,
A first object is to increase the effective channel length and suppress the short channel effect which is a problem in a fine TFT.
A second object of the present invention is to prevent a variation in channel length due to misalignment of resist patterns and to obtain a TFT with less variation in transistor characteristics.

[0009]

In order to achieve the first object, the thin film transistor of the present invention has a gate electrode formed at the bottom of a recess and a gate formed so as to enter the recess. An insulating layer and a semiconductor layer formed so as to enter the recess and to be stacked on the gate insulating layer, and a channel region is formed in the semiconductor layer portion entering the recess. It is characterized by being

The recess can be formed, for example, by forming an insulating sidewall or by etching the insulating layer in a predetermined pattern. A conductive sidewall may be formed on the inner wall of the recess. In that case, the conductive sidewall is connected to the gate electrode and functions as a gate electrode.

A method of manufacturing a thin film transistor that achieves the first object of the present invention comprises a step of forming a recess in a pattern in which a gate electrode is formed in an insulating layer, and a gate electrode at the bottom of the recess. A step of forming a gate insulating layer so as to enter the recess, and a step of forming a semiconductor layer so as to enter the recess and be laminated on the gate insulating layer, While forming a channel region in the semiconductor layer portion that has entered the recess,
In the semiconductor layer portion located on both sides of the channel region,
Forming a drain region.

A method of manufacturing a thin film transistor which achieves the second object of the present invention is the same as the above manufacturing method, except that after the semiconductor layer is formed so as to enter the recess, the surface of the semiconductor layer that enters the recess is formed. Only embedded insulating layer,
Using the insulating layer embedded only in this recess as a mask,
Impurity ions are implanted into the semiconductor layer, the channel region is formed in a self-aligned manner with respect to the semiconductor layer portion located in the recess, and the source / drain regions are self-aligned with the semiconductor layer portions located on both sides of the channel region. It is characterized in that it is formed.

In the above manufacturing method, when the gate electrode is formed on the bottom of the recess, conductive sidewalls connected to the gate electrode may be formed on the inner wall of the recess.

[0014]

In the thin film transistor of the present invention, since the channel region of the transistor is formed in the semiconductor layer portion that has entered the recess, the channel region is not limited to the horizontal two-dimensional direction, but the three-dimensional direction including the vertical direction. Is formed. As a result, the effective channel length can be increased even if the cell size of the transistor is reduced. As a result, it is possible to prevent the short channel effect while miniaturizing the thin film transistor. Moreover, since the present invention does not adopt means for reducing the concentration of the source / drain regions and thinning the gate insulating layer, there is no problem with these means.

According to the method of manufacturing a thin film transistor of the present invention, it is possible to efficiently manufacture a thin film transistor capable of preventing the short channel effect while miniaturizing the transistor. In particular, in the present invention in which a channel region is formed in a self-aligned manner with respect to a semiconductor layer portion located in the recess by ion-implanting impurities into the semiconductor layer using the insulating layer embedded only in the recess as a mask,
The channel length is prevented from fluctuating due to misalignment of the resist pattern, and the transistor characteristics have little variation.
FT can be obtained.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A thin film transistor (TFT) and a method of manufacturing the same according to an embodiment of the present invention will be described below in detail with reference to the drawings. 1 is a cross-sectional view of a main part of a thin film transistor according to an embodiment of the present invention, FIGS.
5 is a cross-sectional view of a main part of a thin film transistor according to another embodiment of the present invention, FIG. 5 is a cross-sectional view of a main part of a thin film transistor according to another embodiment of the present invention, and FIG. 6 is a view showing a manufacturing process of the thin film transistor of the same embodiment. 7 is a partial sectional view of a thin film transistor according to still another embodiment of the present invention.
FIG. 8 is a cross-sectional view of the essential parts showing the manufacturing process of the thin film transistor of the embodiment.

As shown in FIG. 1, a thin film transistor (TFT) 20 according to an embodiment of the present invention is a bottom gate structure TFT formed on an insulating layer 22. The insulating layer 22 is an interlayer insulating layer formed on a semiconductor substrate such as a silicon single crystal wafer. The insulating layer 22 as an interlayer insulating layer is made of, for example, silicon oxide, silicon nitride, PSG, BPSG, or the like. In addition, TFT
20 is an insulating layer 2 when used in a liquid crystal display device or the like.
It is also possible to form it on an insulating substrate such as a glass substrate without forming the second.

In order to form the TFT 20 on the insulating layer 22, the gate electrode 28 is formed on the insulating layer 22 at the bottom of the recess 26 formed by the insulating sidewall 24. The recess 26 is formed in a pattern in which the gate electrode 28 is formed, and the width of the recess corresponds to the gate electrode width, and is about 0.5 μm, for example. The depth of the recess 26 formed by the insulating sidewall 24 is
For example, it is about 100 to 200 nm.

The gate electrode 2 formed on the bottom of the recess 26
8 is made of, for example, a polysilicon film, and the film thickness thereof is not particularly limited and is, for example, about 30 to 50 nm. The gate insulating layer 30 is stacked in the recess 26 having the gate electrode 28 formed at the bottom. The gate insulating layer 30 is, for example, a silicon oxide film formed by a thermal oxidation method or a CVD method, an ONO laminated film (SiO2
/ SiN / SiO2) and the like. The film thickness of the gate insulating layer 30 is not particularly limited and is, for example, 20 nm to 5 nm.
It is about 0 nm.

The semiconductor layer 3 is formed on the surface of the gate insulating layer 30.
2 is formed so as to enter the recess 26.
The semiconductor layer 30 is made of, for example, an active polysilicon layer, and the gate electrode 28 is formed in the recess 26 formed at the bottom.
A channel region 34 of the TFT is formed, and source / drain regions 36, 36 are formed on both sides thereof.

The thickness of the semiconductor layer 32 is not particularly limited, but is, for example, about 5 to 40 nm. The source / drain regions 36 are formed by introducing impurities into the polysilicon layer forming the semiconductor layer 32.
When the FT is a P-type transistor, P-type impurities are introduced by an ion implantation method or the like. The ion implantation conditions are not particularly limited, but, for example, BF ₂ is used, and 10
With the implantation energy of KeV, the condition of the dose amount of 1 to 5 × 10 ¹⁴ cm ⁻² can be adopted.

In the TFT 20 of the present embodiment, since the channel region 34 of the transistor is formed in the semiconductor layer portion that has entered the recess 26, the channel region 34 is not limited to the two-dimensional horizontal direction but the vertical direction. Is formed in a three-dimensional direction including. As a result, the effective channel length can be increased even if the cell size of the transistor is reduced. As a result, it is possible to prevent the short channel effect while achieving miniaturization of the TFT. Moreover, in the present embodiment, since the means for reducing the concentration of the source / drain regions 36 and the thinning of the gate insulating layer 30 are not adopted, there is no problem with these means.

Next, a method of manufacturing the TFT according to this embodiment will be described with reference to FIGS. As shown in FIG. 2A, a polysilicon layer that will eventually become a gate electrode is formed on the surface of the insulating layer 22 by a CVD method or the like, and the polysilicon layer is etched by a gate electrode pattern. , A polysilicon layer 28 'having a predetermined pattern is formed.
The film thickness of the polysilicon layer 28 'is formed to be thicker than the film thickness of the finally obtained gate electrode, for example, 130 nm.
It is a degree. For this polysilicon layer 28 ', for example, BF ₂ is used to have P ⁺ conductivity, and 20K
Ion implantation is performed under the conditions of an implantation energy of eV and a dose amount of 1 × 10 ¹⁵ cm ⁻² .

After that, as shown in FIG. 2B, an insulating layer 24 'for forming insulating sidewalls is laminated on the surface of the insulating layer 22 on which the polysilicon layer 28' is formed. The insulating layer 24 'is preferably made of an insulating material different from that of the insulating layer 22, and is made of, for example, silicon oxide formed by the CVD method. This insulating layer 24 '
Is formed with a film thickness equal to or larger than that of the polysilicon layer 28 ', and the film thickness is, for example, 200 nm. Next, the insulating layer 24 'is etched back by anisotropic etching such as RIE to form insulating sidewalls 24, 24 shown in FIG. 2C on both sides of the polysilicon layer 28'.

Next, the polysilicon layer 28 'is etched by RIE or the like under the condition that a selection ratio with respect to the silicon oxide or the like which constitutes the insulating sidewall 24 can be obtained.
As shown in (D), a recess 26 is formed inside the insulating sidewall 24, and a polysilicon layer is left at the bottom of the recess 26 to form a gate electrode 28. The gate electrode 28 obtained by etching the polysilicon layer has a film thickness of, for example, about 30 nm. As a result, the height of the insulating sidewall 24 is 130 nm.
The gate electrode 28 is formed to have a thickness of 30 nm at the bottom of the recess 26 having a depth of 130 nm formed by the insulating sidewall 24.

Next, as shown in FIG. 3E, a gate insulating layer 30 is formed so as to enter the inside of the recess 26 formed by the insulating sidewall 24. In this embodiment, as the gate insulating layer 30, a silicon oxide layer having a thickness of about 40 nm is deposited by the TEOS-CVD method, and then 800 ° C.
It is formed by performing wet oxidation for about 30 minutes. The surface of the gate insulating layer 30 has a CV of about 550 ° C.
An amorphous silicon layer is formed by the D method, and the temperature is 600 ° C.
By performing low temperature annealing for a long time, the amorphous silicon layer is polycrystallized to obtain the semiconductor layer 32 composed of the active polysilicon layer. The film thickness is, for example, 10 nm
Is. The semiconductor layer 32 is formed by RIE with a pattern of the active region.
Etched by

Finally, as shown in FIG. 3 (F), the recess 2
Form resist film 38 so that it is located only on top of 6
Then, using this resist film 38 as a mask, the source / drain is removed.
Ion implantation for forming the in-region is performed. P-type TFT
When using a transistor, the ion implantation is BF₂ For
1 × 10 at an injection energy of 10 KeV¹⁴cm ^-2
It is performed under the condition of the dose amount. With this ion implantation,
The portion of the semiconductor layer 32 not covered with the dysto film 38 is
The source / drain region 36 is formed, and the resist film 38 is formed.
Of the semiconductor layer 32 located in the more covered recess 26
A channel region 34 is formed in the portion.

In the method of manufacturing the TFT according to the present embodiment, the TFT 20 capable of preventing the short channel effect can be efficiently manufactured while miniaturizing the transistor. Next, the T according to the second embodiment of the present invention.
The FT 41 will be described with reference to FIG. 4, the members common to the embodiment shown in FIGS. 1 to 3 are designated by the same reference numerals, and the description thereof is partially omitted. In the TFT 41 of the embodiment shown in FIG. 4, the insulating sidewalls 24, 24 are
Conductive sidewalls 40, 40 are formed on the inner wall of the recess 26 formed by. The conductive sidewalls 40, 40 are made of, for example, the same conductive polysilicon as the polysilicon forming the gate electrode 28,
It is connected to the gate electrode 28 at its bottom. The conductive sidewalls 40 made of conductive polysilicon can be formed in the same manner by using the technique of forming the insulating sidewalls 24.

The conductive sidewall 40 is formed in the recess 26.
This conductive sidewall 40 is provided on the inner wall of the
Also functions as a gate electrode, and the influence of the gate voltage on the channel region 34 formed in the semiconductor layer portion that has entered the recess 26 becomes certain, which is more preferable. Other functions and effects are similar to those of the embodiment shown in FIGS.

Next, a third embodiment of the present invention will be described with reference to FIGS. TFT 5 of the embodiment shown in FIG.
Reference numeral 1 denotes a bottom-gate TFT, and members common to those in the above-described embodiments are designated by common member numbers, and description thereof is partially omitted.

In the TFT shown in FIG. 5, on the insulating layer 22,
The insulating layer 42 is laminated, and the gate electrode 43 is formed on the inner bottom of the recess 26 formed in the insulating layer 42.
The insulating layer 42 is preferably made of an insulating material different from that of the insulating layer 22, for example, silicon oxide. When it is not necessary to strictly control the depth of the recess 26, the insulating layer 42 and the insulating layer 22 may be made of the same insulating material. When the insulating materials of different materials are used, by selecting the etching processing conditions, the surface of the insulating layer 22 is used as an etching stopper.
This is because the recess 26 can be formed.

The recess 26 is formed in a pattern in which the gate electrode 43 is formed, and the width of the recess corresponds to the width of the gate electrode and is, for example, about 0.5 μm. The depth of the recess 26 is, for example, about 80 to 200 nm. The gate electrode 43 formed on the bottom of the recess 26 is made of, for example, a polysilicon film, and the film thickness thereof is not particularly limited and is, for example, about 30 to 50 nm. The gate insulating layer 30 is stacked in the recess 26 having the gate electrode 43 formed at the bottom. Gate insulating layer 3
0 is a silicon oxide film formed by, for example, a thermal oxidation method or a CVD method, an ONO laminated film (SiO2 / SiN / S).
iO2) etc. The film thickness of the gate insulating layer 30 is not particularly limited and is, for example, about 20 nm to 50 nm.

The semiconductor layer 4 is formed on the surface of the gate insulating layer 30.
4 is formed so as to enter the recess 26.
The semiconductor layer 44 is made of, for example, an active polysilicon layer, and is formed in the recess 26 in which the gate electrode 43 is formed at the bottom.
A channel region 50 of the TFT is formed, and source / drain regions 52, 52 are formed on both sides thereof. An insulating layer 48 is formed on the surface of the semiconductor layer 44 located in the recess 26.
Is embedded. The insulating layer 48 is embedded by a method described later and is made of, for example, silicon oxide.

The thickness of the semiconductor layer 44 is not particularly limited, but is, for example, about 5 to 40 nm. The source / drain regions 52, 52 are formed by introducing an impurity into the polysilicon layer forming the semiconductor layer 44. When the TFT is a P-type transistor, the P-type impurity is formed by an ion implantation method or the like. be introduced.

In this embodiment, the source / drain regions 52, 52 are formed by adopting the manufacturing method described later.
Are formed in a self-aligned manner. Next, T according to the present embodiment
A method of manufacturing the FT will be described. First, as shown in FIG. 6A, an insulating layer 42 made of silicon oxide or the like is formed on the surface of the insulating layer 22 by a CVD method or the like, and a resist film is used for the insulating layer 42. The recesses 26 are formed in a pattern in which the gate electrode is formed by etching treatment such as RIE. The thickness of the insulating layer 42 is, for example, 100
nm. The width of the recess 26 is, for example, 0.5 μm, and the depth thereof is 100 nm.

Next, as shown in FIG. 6B, the recess 26
On the surface of the insulating layer 42, the gate electrode
Then, a polysilicon layer 43 'is formed. Polysilicon
The film thickness of the layer 43 'is the film thickness of the finally obtained gate electrode.
It is formed thicker than that, and has a thickness of, for example, about 300 nm.
This polysilicon layer 43 'has, for example, P⁺Conductivity
BF to have₂ Injection of 20 KeV
1 × 10 in energy ¹⁵cm^-2Under the condition of the dose amount of
Injection.

After that, as shown in FIG. 6C, the recess 2
The polysilicon layer 43 ′ is entirely etched back so that the polysilicon layer remains only on the bottom of 6 to obtain the gate electrode 43. The film thickness of the gate electrode 43 is, for example, 30 nm. Then, the gate insulating layer 30 is formed so as to enter the recess 26 of the insulating layer 42. In this embodiment, the gate insulating layer 30 is formed by depositing a silicon oxide layer of about 40 nm by the TEOS-CVD method, and then performing wet oxidation at 800 ° C. for about 30 minutes. An amorphous silicon layer is formed on the surface of the gate insulating layer 30 by a CVD method at about 550 ° C., and a low temperature annealing process is performed at 600 ° C. for 10 hours to polycrystallize the amorphous silicon layer and activate it. A semiconductor layer 44 composed of a polysilicon layer is obtained. The film thickness is, for example, 10 nm.
The semiconductor layer 44 is etched by RIE or the like in the pattern of the active region.

After that, the insulating layer 4 for embedding is formed so as to enter the recess 26 and to have the surface flattened.
8'is formed into a film. The embedded insulating layer 48 'is preferably composed of a silicon oxide layer formed by the ECR-plasma CVD method in order to maintain the flatness of the surface.

After that, as shown in FIG. 5, the buried insulating layer 48 'is entirely etched back to remove the insulating layer 48' except in the recess 26, and the buried insulating layer 48 remains only in the recess 26. To do so. Finally, ion implantation for source / drain region formation is performed in a self-aligned manner using the buried insulating layer 48 as a mask. When the TFT is a P-type transistor, BF ₂ is used for ion implantation.
The implantation energy is 0 KeV and the dose is 1 × 10 ¹⁴ cm ^-2 . The projected range Rp at the time of this ion implantation is preferably small so that the ions are implanted only into the semiconductor layer 44 not covered with the buried insulating layer 48, and for example, Rp is preferably about 7 nm. By this ion implantation, the buried insulating layer 48 is formed.
Source / drain regions 52, 52 are formed in the portion of the semiconductor layer 44 which is not covered with, and a channel region 50 is formed in the portion of the semiconductor layer 44 located in the recess 26 which is covered by the buried insulating layer 48. To be done.

In the method of manufacturing the TFT according to the present embodiment, the TFT 51 capable of preventing the short channel effect can be efficiently manufactured while miniaturizing the transistor. In particular, according to the present embodiment, impurities are ion-implanted into the semiconductor layer 44 by using the buried insulating layer 48 embedded only in the recess 26 as a mask, and the semiconductor layer portion located in the recess 26 is exposed. Since the channel region is formed in a self-aligned manner, it is possible to prevent a variation in channel length due to misalignment of resist patterns, etc., and to obtain a TFT with less variation in transistor characteristics.

Next, a fourth embodiment of the present invention will be described with reference to FIGS. TFT 6 of the embodiment shown in FIG.
1 is a modified example of the embodiment shown in FIGS.
Members common to the examples are given common member numbers,
The description is partially omitted.

In the TFT shown in FIG. 7, on the insulating layer 22,
The insulating layer 42 is laminated, and the gate electrode 53 is formed on the inner bottom of the recess 26 formed in the insulating layer 42.
Further, particularly in this embodiment, the conductive sidewalls 54, 54 are formed integrally with the gate electrode 53 on the inner wall of the recess 26. Other configurations are similar to those of the embodiment shown in FIGS.

In the TFT 61 according to this embodiment, the TFTs shown in FIGS.
In addition to having the same effect as the embodiment shown in FIG. 5, by providing the conductive sidewalls 54, 54 on the inner wall of the recess 26, the conductive sidewalls 54, 54 also function as the gate electrode and the recess 26 This has the effect of ensuring the influence of the gate voltage on the channel region 50 formed in the semiconductor layer portion that has entered.

Next, a method of manufacturing the TFT 61 according to this embodiment will be described. First, as shown in FIG. 8A, an insulating layer 42 made of silicon oxide or the like is formed on the surface of the insulating layer 22 by a CVD method or the like.
The etching process such as RIE using the resist film is used to form the recesses 26 in the pattern for forming the gate electrodes. The film thickness of the insulating layer 42 is, for example, 100 nm. The width of the recess 26 is, for example, 0.5 μm, and the depth thereof is 100 nm.

Next, as shown in FIG. 8B, the recess 26
On the surface of the insulating layer 42, the gate electrode
Then, a polysilicon layer 53 'is formed. Polysilicon
The film thickness of the layer 53 'is the film thickness of the finally obtained gate electrode.
It is formed thicker than that, and has a thickness of, for example, about 300 nm.
This polysilicon layer 53 'has, for example, P⁺Conductivity
BF to have₂ Injection of 20 KeV
1 × 10 in energy ¹⁵cm^-2Under the condition of the dose amount of
Injection.

After that, as shown in FIG.
The entire polysilicon layer 53 'is etched back so that the polysilicon layer remains only on the bottom of 6 to obtain the gate electrode 53. At that time, by appropriately combining anisotropic etching such as RIE with isotropic etching, the polysilicon layer is left at the bottom of the recess 26 to form the gate electrode 53, and at the same time, the recess is formed. Conductive sidewalls 54 are formed on the inner walls of 26. The conductive sidewall 54 may be formed separately from the gate electrode 53 and connected to each other. The film thickness of the gate electrode 43 is, for example, 30 nm.

Next, the gate insulating layer 30 is formed so as to enter the recess 26 of the insulating layer 42. In this embodiment, as the gate insulating layer 30, a silicon oxide layer having a thickness of about 40 nm is deposited by the TEOS-CVD method, and then 800 ° C., 3
It is formed by performing wet oxidation for about 0 minutes. The surface of the gate insulating layer 30 has a CV of about 550 ° C.
An amorphous silicon layer is formed by the D method, and the temperature is 600 ° C.
By performing low temperature annealing for a long time, the amorphous silicon layer is polycrystallized to obtain the semiconductor layer 44 composed of the active polysilicon layer. The film thickness is, for example, 10 nm
Is. The semiconductor layer 44 is formed by RIE with a pattern of the active region.
Etched by

After that, the insulating layer 4 for embedding is embedded in the recess 26 so that the surface is flattened.
8'is formed into a film. The embedded insulating layer 48 'is preferably composed of a silicon oxide layer formed by the ECR-plasma CVD method in order to maintain the flatness of the surface.

After that, as shown in FIG. 7, the buried insulating layer 48 ′ is entirely etched back to remove the insulating layer 48 ′ except in the recess 26, and the buried insulating layer 48 remains only in the recess 26. To do so. Finally, ion implantation for source / drain region formation is performed in a self-aligned manner using the buried insulating layer 48 as a mask. When the TFT is a P-type transistor, BF ₂ is used for ion implantation.
The implantation energy is 0 KeV and the dose is 1 × 10 ¹⁴ cm ^-2 . The projected range Rp at the time of this ion implantation is preferably small so that the ions are implanted only into the semiconductor layer 44 not covered with the buried insulating layer 48, and for example, Rp is preferably about 7 nm. By this ion implantation, the buried insulating layer 48 is formed.
Source / drain regions 52, 52 are formed in the portion of the semiconductor layer 44 which is not covered with, and a channel region 50 is formed in the portion of the semiconductor layer 44 located in the recess 26 which is covered by the buried insulating layer 48. To be done.

In the method of manufacturing the TFT according to this embodiment, the TFT 61 capable of preventing the short channel effect can be efficiently manufactured while miniaturizing the transistor. In particular, according to the present embodiment, impurities are ion-implanted into the semiconductor layer 44 by using the buried insulating layer 48 embedded only in the recess 26 as a mask, and the semiconductor layer portion located in the recess 26 is exposed. Since the channel region is formed in a self-aligned manner, it is possible to prevent a variation in channel length due to misalignment of resist patterns, etc., and to obtain a TFT with less variation in transistor characteristics.

The present invention is not limited to the above-mentioned embodiments, but can be variously modified within the scope of the present invention. For example, the present invention can be applied to a top gate structure T
It can also be applied to FT.

[0052]

As described above, according to the present invention, since the channel region of the transistor is formed in the semiconductor layer portion which is recessed, the effective channel is obtained even if the cell size of the transistor is reduced. The length can be lengthened. As a result, it is possible to prevent the short channel effect while miniaturizing the thin film transistor. Moreover, since the present invention does not adopt means for reducing the concentration of the source / drain regions and thinning the gate insulating layer, there is no problem with these means.

According to the method of manufacturing a thin film transistor of the present invention, it is possible to efficiently manufacture a thin film transistor capable of preventing the short channel effect while miniaturizing the transistor. In particular, in the present invention in which a channel region is formed in a self-aligned manner with respect to a semiconductor layer portion located in the recess by ion-implanting impurities into the semiconductor layer using the insulating layer embedded only in the recess as a mask,
The channel length is prevented from fluctuating due to misalignment of the resist pattern, and the transistor characteristics have little variation.
FT can be obtained.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a main part of a thin film transistor according to an embodiment of the present invention.

FIG. 2 is a main-portion cross-sectional view showing the manufacturing process of the thin film transistor of the embodiment.

FIG. 3 is a main-portion cross-sectional view showing the manufacturing process of the thin film transistor of the embodiment.

FIG. 4 is a cross-sectional view of a main part of a thin film transistor according to another embodiment of the present invention.

FIG. 5 is a cross-sectional view of a main part of a thin film transistor according to another embodiment of the present invention.

FIG. 6 is a main-portion cross-sectional view showing the manufacturing process of the thin-film transistor of the embodiment.

FIG. 7 is a cross-sectional view of essential parts of a thin film transistor according to still another embodiment of the present invention.

FIG. 8 is a main-portion cross-sectional view showing the manufacturing process of the thin-film transistor of the same Example.

FIG. 9 is a cross-sectional view of a main part of a thin film transistor according to a conventional example.

[Explanation of symbols]

20, 41, 51, 61 ... Thin film transistor (TF
T) 22 ... Insulating layer 24 ... Insulating sidewall 26 ... Recess 28, 43, 53 ... Gate electrode 30 ... Gate insulating layer 32, 44 ... Semiconductor layer 34, 50 ... Channel region 36, 52 ... Source / drain region 40 … Conductive sidewall

Claims (6)

[Claims] 1. A gate electrode formed on the bottom of a recess, a gate insulating layer formed so as to enter the recess, and a gate insulating layer laminated so as to enter the recess and on the gate insulating layer. A thin film transistor having a semiconductor layer formed as described above, and a channel region is formed in the semiconductor layer portion that has entered the recess. 2. The thin film transistor according to claim 1, wherein the recess is formed by an insulating sidewall. 3. The conductive sidewall is formed on an inner wall of the recess, and the conductive sidewall is connected to the gate electrode and functions as a gate electrode. Thin film transistor. 4. A step of forming a recess in an insulating layer in a pattern in which a gate electrode is formed, a step of forming a gate electrode at the bottom of the recess, and a gate so as to enter the recess. A step of forming an insulating layer, a step of forming a semiconductor layer so as to enter the recess and further being laminated on the gate insulating layer, and a step of forming a channel region in the part of the semiconductor layer entering the recess. And a step of forming source / drain regions in the semiconductor layer portions located on both sides of the channel region. 5. After forming a semiconductor layer so as to enter the recess, an insulating layer is embedded only in the surface of the semiconductor layer entering the recess, and the insulating layer embedded only in the recess is used as a mask. By implanting impurities into the semiconductor layer, the channel region is formed in a self-aligned manner with respect to the semiconductor layer portion located in the recess, and the source / drain regions are self-aligned with the semiconductor layer portions located on both sides of the channel region. The method for manufacturing a thin film transistor according to claim 4, wherein the thin film transistor is formed in a uniform manner. 6. The thin film transistor according to claim 4, wherein when forming the gate electrode on the bottom of the recess, conductive sidewalls connected to the gate electrode are formed on the inner wall of the recess. Production method.